git.sur5r.net Git - u-boot/blob - drivers/spi/ti_qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013, Texas Instruments, Incorporated
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/omap.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14 #include <asm/gpio.h>
  15 #include <asm/omap_gpio.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/ti-common/ti-edma3.h>
  18
  19 /* ti qpsi register bit masks */
  20 #define QSPI_TIMEOUT                    2000000
  21 #define QSPI_FCLK                       192000000
  22 /* clock control */
  23 #define QSPI_CLK_EN                     BIT(31)
  24 #define QSPI_CLK_DIV_MAX                0xffff
  25 /* command */
  26 #define QSPI_EN_CS(n)                   (n << 28)
  27 #define QSPI_WLEN(n)                    ((n-1) << 19)
  28 #define QSPI_3_PIN                      BIT(18)
  29 #define QSPI_RD_SNGL                    BIT(16)
  30 #define QSPI_WR_SNGL                    (2 << 16)
  31 #define QSPI_INVAL                      (4 << 16)
  32 #define QSPI_RD_QUAD                    (7 << 16)
  33 /* device control */
  34 #define QSPI_DD(m, n)                   (m << (3 + n*8))
  35 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  36 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  37 #define QSPI_CKPOL(n)                   (1 << (n*8))
  38 /* status */
  39 #define QSPI_WC                         BIT(1)
  40 #define QSPI_BUSY                       BIT(0)
  41 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  42 #define QSPI_XFER_DONE                  QSPI_WC
  43 #define MM_SWITCH                       0x01
  44 #define MEM_CS(cs)                      ((cs + 1) << 8)
  45 #define MEM_CS_UNSELECT                 0xfffff0ff
  46 #define MMAP_START_ADDR_DRA             0x5c000000
  47 #define MMAP_START_ADDR_AM43x           0x30000000
  48 #define CORE_CTRL_IO                    0x4a002558
  49
  50 #define QSPI_CMD_READ                   (0x3 << 0)
  51 #define QSPI_CMD_READ_QUAD              (0x6b << 0)
  52 #define QSPI_CMD_READ_FAST              (0x0b << 0)
  53 #define QSPI_SETUP0_NUM_A_BYTES         (0x2 << 8)
  54 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
  55 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
  56 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  57 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  58 #define QSPI_CMD_WRITE                  (0x2 << 16)
  59 #define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
  60
  61 /* ti qspi register set */
  62 struct ti_qspi_regs {
  63         u32 pid;
  64         u32 pad0[3];
  65         u32 sysconfig;
  66         u32 pad1[3];
  67         u32 int_stat_raw;
  68         u32 int_stat_en;
  69         u32 int_en_set;
  70         u32 int_en_ctlr;
  71         u32 intc_eoi;
  72         u32 pad2[3];
  73         u32 clk_ctrl;
  74         u32 dc;
  75         u32 cmd;
  76         u32 status;
  77         u32 data;
  78         u32 setup0;
  79         u32 setup1;
  80         u32 setup2;
  81         u32 setup3;
  82         u32 memswitch;
  83         u32 data1;
  84         u32 data2;
  85         u32 data3;
  86 };
  87
  88 /* ti qspi priv */
  89 struct ti_qspi_priv {
  90         struct spi_slave slave;
  91         struct ti_qspi_regs *base;
  92         void *ctrl_mod_mmap;
  93         unsigned int mode;
  94         u32 cmd;
  95         u32 dc;
  96 };
  97
  98 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
  99 {
 100         uint clk_div;
 101
 102         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 103
 104         if (!hz)
 105                 clk_div = 0;
 106         else
 107                 clk_div = (QSPI_FCLK / hz) - 1;
 108
 109         /* disable SCLK */
 110         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 111                &priv->base->clk_ctrl);
 112
 113         /* assign clk_div values */
 114         if (clk_div < 0)
 115                 clk_div = 0;
 116         else if (clk_div > QSPI_CLK_DIV_MAX)
 117                 clk_div = QSPI_CLK_DIV_MAX;
 118
 119         /* enable SCLK */
 120         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 121 }
 122
 123 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 124 {
 125         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 126         /* dummy readl to ensure bus sync */
 127         readl(&priv->base->cmd);
 128 }
 129
 130 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
 131 {
 132         priv->dc = 0;
 133         if (mode & SPI_CPHA)
 134                 priv->dc |= QSPI_CKPHA(0);
 135         if (mode & SPI_CPOL)
 136                 priv->dc |= QSPI_CKPOL(0);
 137         if (mode & SPI_CS_HIGH)
 138                 priv->dc |= QSPI_CSPOL(0);
 139
 140         return 0;
 141 }
 142
 143 static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
 144 {
 145         writel(priv->dc, &priv->base->dc);
 146         writel(0, &priv->base->cmd);
 147         writel(0, &priv->base->data);
 148
 149         priv->dc <<= cs * 8;
 150         writel(priv->dc, &priv->base->dc);
 151
 152         return 0;
 153 }
 154
 155 static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
 156 {
 157         writel(0, &priv->base->dc);
 158         writel(0, &priv->base->cmd);
 159         writel(0, &priv->base->data);
 160 }
 161
 162 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 163 {
 164         u32 val;
 165
 166         val = readl(ctrl_mod_mmap);
 167         if (enable)
 168                 val |= MEM_CS(cs);
 169         else
 170                 val &= MEM_CS_UNSELECT;
 171         writel(val, ctrl_mod_mmap);
 172 }
 173
 174 static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
 175                         const void *dout, void *din, unsigned long flags,
 176                         u32 cs)
 177 {
 178         uint words = bitlen >> 3; /* fixed 8-bit word length */
 179         const uchar *txp = dout;
 180         uchar *rxp = din;
 181         uint status;
 182         int timeout;
 183
 184         /* Setup mmap flags */
 185         if (flags & SPI_XFER_MMAP) {
 186                 writel(MM_SWITCH, &priv->base->memswitch);
 187                 if (priv->ctrl_mod_mmap)
 188                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
 189                 return 0;
 190         } else if (flags & SPI_XFER_MMAP_END) {
 191                 writel(~MM_SWITCH, &priv->base->memswitch);
 192                 if (priv->ctrl_mod_mmap)
 193                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
 194                 return 0;
 195         }
 196
 197         if (bitlen == 0)
 198                 return -1;
 199
 200         if (bitlen % 8) {
 201                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 202                 return -1;
 203         }
 204
 205         /* Setup command reg */
 206         priv->cmd = 0;
 207         priv->cmd |= QSPI_WLEN(8);
 208         priv->cmd |= QSPI_EN_CS(cs);
 209         if (priv->mode & SPI_3WIRE)
 210                 priv->cmd |= QSPI_3_PIN;
 211         priv->cmd |= 0xfff;
 212
 213 /* FIXME: This delay is required for successfull
 214  * completion of read/write/erase. Once its root
 215  * caused, it will be remove from the driver.
 216  */
 217 #ifdef CONFIG_AM43XX
 218         udelay(100);
 219 #endif
 220         while (words--) {
 221                 if (txp) {
 222                         debug("tx cmd %08x dc %08x data %02x\n",
 223                               priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
 224                         writel(*txp++, &priv->base->data);
 225                         writel(priv->cmd | QSPI_WR_SNGL,
 226                                &priv->base->cmd);
 227                         status = readl(&priv->base->status);
 228                         timeout = QSPI_TIMEOUT;
 229                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 230                                 if (--timeout < 0) {
 231                                         printf("spi_xfer: TX timeout!\n");
 232                                         return -1;
 233                                 }
 234                                 status = readl(&priv->base->status);
 235                         }
 236                         debug("tx done, status %08x\n", status);
 237                 }
 238                 if (rxp) {
 239                         priv->cmd |= QSPI_RD_SNGL;
 240                         debug("rx cmd %08x dc %08x\n",
 241                               priv->cmd, priv->dc);
 242                         #ifdef CONFIG_DRA7XX
 243                                 udelay(500);
 244                         #endif
 245                         writel(priv->cmd, &priv->base->cmd);
 246                         status = readl(&priv->base->status);
 247                         timeout = QSPI_TIMEOUT;
 248                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 249                                 if (--timeout < 0) {
 250                                         printf("spi_xfer: RX timeout!\n");
 251                                         return -1;
 252                                 }
 253                                 status = readl(&priv->base->status);
 254                         }
 255                         *rxp++ = readl(&priv->base->data);
 256                         debug("rx done, status %08x, read %02x\n",
 257                               status, *(rxp-1));
 258                 }
 259         }
 260
 261         /* Terminate frame */
 262         if (flags & SPI_XFER_END)
 263                 ti_qspi_cs_deactivate(priv);
 264
 265         return 0;
 266 }
 267
 268 /* TODO: control from sf layer to here through dm-spi */
 269 #ifdef CONFIG_TI_EDMA3
 270 void spi_flash_copy_mmap(void *data, void *offset, size_t len)
 271 {
 272         unsigned int                    addr = (unsigned int) (data);
 273         unsigned int                    edma_slot_num = 1;
 274
 275         /* Invalidate the area, so no writeback into the RAM races with DMA */
 276         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 277
 278         /* enable edma3 clocks */
 279         enable_edma3_clocks();
 280
 281         /* Call edma3 api to do actual DMA transfer     */
 282         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 283
 284         /* disable edma3 clocks */
 285         disable_edma3_clocks();
 286
 287         *((unsigned int *)offset) += len;
 288 }
 289 #endif
 290
 291 static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
 292 {
 293         return container_of(slave, struct ti_qspi_priv, slave);
 294 }
 295
 296 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 297 {
 298         return 1;
 299 }
 300
 301 void spi_cs_activate(struct spi_slave *slave)
 302 {
 303         /* CS handled in xfer */
 304         return;
 305 }
 306
 307 void spi_cs_deactivate(struct spi_slave *slave)
 308 {
 309         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 310         ti_qspi_cs_deactivate(priv);
 311 }
 312
 313 void spi_init(void)
 314 {
 315         /* nothing to do */
 316 }
 317
 318 static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
 319 {
 320         u32 memval = 0;
 321
 322 #ifdef CONFIG_QSPI_QUAD_SUPPORT
 323         struct spi_slave *slave = &priv->slave;
 324         memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
 325                         QSPI_SETUP0_NUM_D_BYTES_8_BITS |
 326                         QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
 327                         QSPI_NUM_DUMMY_BITS);
 328         slave->mode_rx = SPI_RX_QUAD;
 329 #else
 330         memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
 331                         QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
 332                         QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
 333                         QSPI_NUM_DUMMY_BITS;
 334 #endif
 335
 336         writel(memval, &priv->base->setup0);
 337 }
 338
 339 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 340                                   unsigned int max_hz, unsigned int mode)
 341 {
 342         struct ti_qspi_priv *priv;
 343
 344 #ifdef CONFIG_AM43XX
 345         gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
 346         gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
 347 #endif
 348
 349         priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
 350         if (!priv) {
 351                 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
 352                 return NULL;
 353         }
 354
 355         priv->base = (struct ti_qspi_regs *)QSPI_BASE;
 356         priv->mode = mode;
 357 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 358         priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
 359         priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
 360 #else
 361         priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
 362 #endif
 363
 364         ti_spi_set_speed(priv, max_hz);
 365
 366 #ifdef CONFIG_TI_SPI_MMAP
 367         ti_spi_setup_spi_register(priv);
 368 #endif
 369
 370         return &priv->slave;
 371 }
 372
 373 void spi_free_slave(struct spi_slave *slave)
 374 {
 375         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 376         free(priv);
 377 }
 378
 379 int spi_claim_bus(struct spi_slave *slave)
 380 {
 381         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 382
 383         debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
 384         __ti_qspi_set_mode(priv, priv->mode);
 385         return __ti_qspi_claim_bus(priv, priv->slave.cs);
 386 }
 387 void spi_release_bus(struct spi_slave *slave)
 388 {
 389         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 390
 391         debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
 392         __ti_qspi_release_bus(priv);
 393 }
 394
 395 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 396              void *din, unsigned long flags)
 397 {
 398         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 399
 400         debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
 401               priv->slave.bus, priv->slave.cs, bitlen, flags);
 402         return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
 403 }