4 * Copyright (C) 2013, Texas Instruments, Incorporated
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
16 #include <asm/omap_gpio.h>
17 #include <asm/omap_common.h>
18 #include <asm/ti-common/ti-edma3.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 /* ti qpsi register bit masks */
23 #define QSPI_TIMEOUT 2000000
24 #define QSPI_FCLK 192000000
25 #define QSPI_DRA7XX_FCLK 76800000
26 #define QSPI_WLEN_MAX_BITS 128
27 #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
28 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
30 #define QSPI_CLK_EN BIT(31)
31 #define QSPI_CLK_DIV_MAX 0xffff
33 #define QSPI_EN_CS(n) (n << 28)
34 #define QSPI_WLEN(n) ((n-1) << 19)
35 #define QSPI_3_PIN BIT(18)
36 #define QSPI_RD_SNGL BIT(16)
37 #define QSPI_WR_SNGL (2 << 16)
38 #define QSPI_INVAL (4 << 16)
39 #define QSPI_RD_QUAD (7 << 16)
41 #define QSPI_DD(m, n) (m << (3 + n*8))
42 #define QSPI_CKPHA(n) (1 << (2 + n*8))
43 #define QSPI_CSPOL(n) (1 << (1 + n*8))
44 #define QSPI_CKPOL(n) (1 << (n*8))
46 #define QSPI_WC BIT(1)
47 #define QSPI_BUSY BIT(0)
48 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
49 #define QSPI_XFER_DONE QSPI_WC
50 #define MM_SWITCH 0x01
51 #define MEM_CS(cs) ((cs + 1) << 8)
52 #define MEM_CS_UNSELECT 0xfffff8ff
53 #define MMAP_START_ADDR_DRA 0x5c000000
54 #define MMAP_START_ADDR_AM43x 0x30000000
55 #define CORE_CTRL_IO 0x4a002558
57 #define QSPI_CMD_READ (0x3 << 0)
58 #define QSPI_CMD_READ_DUAL (0x6b << 0)
59 #define QSPI_CMD_READ_QUAD (0x6c << 0)
60 #define QSPI_CMD_READ_FAST (0x0b << 0)
61 #define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
62 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
63 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
64 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
65 #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
66 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
67 #define QSPI_CMD_WRITE (0x12 << 16)
68 #define QSPI_NUM_DUMMY_BITS (0x0 << 24)
70 /* ti qspi register set */
100 struct spi_slave slave;
106 struct ti_qspi_regs *base;
114 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
121 clk_div = (priv->fclk / hz) - 1;
123 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
126 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
127 &priv->base->clk_ctrl);
129 /* assign clk_div values */
132 else if (clk_div > QSPI_CLK_DIV_MAX)
133 clk_div = QSPI_CLK_DIV_MAX;
136 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
139 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
141 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
142 /* dummy readl to ensure bus sync */
143 readl(&priv->base->cmd);
146 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
150 priv->dc |= QSPI_CKPHA(0);
152 priv->dc |= QSPI_CKPOL(0);
153 if (mode & SPI_CS_HIGH)
154 priv->dc |= QSPI_CSPOL(0);
159 static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
161 writel(priv->dc, &priv->base->dc);
162 writel(0, &priv->base->cmd);
163 writel(0, &priv->base->data);
166 writel(priv->dc, &priv->base->dc);
171 static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
173 writel(0, &priv->base->dc);
174 writel(0, &priv->base->cmd);
175 writel(0, &priv->base->data);
178 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
182 val = readl(ctrl_mod_mmap);
186 val &= MEM_CS_UNSELECT;
187 writel(val, ctrl_mod_mmap);
190 static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
191 const void *dout, void *din, unsigned long flags,
194 uint words = bitlen >> 3; /* fixed 8-bit word length */
195 const uchar *txp = dout;
200 /* Setup mmap flags */
201 if (flags & SPI_XFER_MMAP) {
202 writel(MM_SWITCH, &priv->base->memswitch);
203 if (priv->ctrl_mod_mmap)
204 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
206 } else if (flags & SPI_XFER_MMAP_END) {
207 writel(~MM_SWITCH, &priv->base->memswitch);
208 if (priv->ctrl_mod_mmap)
209 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
217 debug("spi_xfer: Non byte aligned SPI transfer\n");
221 /* Setup command reg */
223 priv->cmd |= QSPI_WLEN(8);
224 priv->cmd |= QSPI_EN_CS(cs);
225 if (priv->mode & SPI_3WIRE)
226 priv->cmd |= QSPI_3_PIN;
229 /* FIXME: This delay is required for successfull
230 * completion of read/write/erase. Once its root
231 * caused, it will be remove from the driver.
242 if (words >= QSPI_WLEN_MAX_BYTES) {
243 u32 *txbuf = (u32 *)txp;
246 data = cpu_to_be32(*txbuf++);
247 writel(data, &priv->base->data3);
248 data = cpu_to_be32(*txbuf++);
249 writel(data, &priv->base->data2);
250 data = cpu_to_be32(*txbuf++);
251 writel(data, &priv->base->data1);
252 data = cpu_to_be32(*txbuf++);
253 writel(data, &priv->base->data);
254 cmd &= ~QSPI_WLEN_MASK;
255 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
256 xfer_len = QSPI_WLEN_MAX_BYTES;
258 writeb(*txp, &priv->base->data);
261 debug("tx cmd %08x dc %08x\n",
262 cmd | QSPI_WR_SNGL, priv->dc);
263 writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
264 status = readl(&priv->base->status);
265 timeout = QSPI_TIMEOUT;
266 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
268 printf("spi_xfer: TX timeout!\n");
271 status = readl(&priv->base->status);
274 debug("tx done, status %08x\n", status);
277 debug("rx cmd %08x dc %08x\n",
278 ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
279 writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
280 status = readl(&priv->base->status);
281 timeout = QSPI_TIMEOUT;
282 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
284 printf("spi_xfer: RX timeout!\n");
287 status = readl(&priv->base->status);
289 *rxp++ = readl(&priv->base->data);
291 debug("rx done, status %08x, read %02x\n",
297 /* Terminate frame */
298 if (flags & SPI_XFER_END)
299 ti_qspi_cs_deactivate(priv);
304 /* TODO: control from sf layer to here through dm-spi */
305 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
306 void spi_flash_copy_mmap(void *data, void *offset, size_t len)
308 unsigned int addr = (unsigned int) (data);
309 unsigned int edma_slot_num = 1;
311 /* Invalidate the area, so no writeback into the RAM races with DMA */
312 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
314 /* enable edma3 clocks */
315 enable_edma3_clocks();
317 /* Call edma3 api to do actual DMA transfer */
318 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
320 /* disable edma3 clocks */
321 disable_edma3_clocks();
323 *((unsigned int *)offset) += len;
327 #ifndef CONFIG_DM_SPI
329 static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
331 return container_of(slave, struct ti_qspi_priv, slave);
334 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
339 void spi_cs_activate(struct spi_slave *slave)
341 /* CS handled in xfer */
345 void spi_cs_deactivate(struct spi_slave *slave)
347 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
348 ti_qspi_cs_deactivate(priv);
356 static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
360 #ifdef CONFIG_QSPI_QUAD_SUPPORT
361 struct spi_slave *slave = &priv->slave;
362 memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
363 QSPI_SETUP0_NUM_D_BYTES_8_BITS |
364 QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
365 QSPI_NUM_DUMMY_BITS);
366 slave->mode_rx = SPI_RX_QUAD;
368 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
369 QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
370 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
374 writel(memval, &priv->base->setup0);
377 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
378 unsigned int max_hz, unsigned int mode)
380 struct ti_qspi_priv *priv;
383 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
384 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
387 priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
389 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
393 priv->base = (struct ti_qspi_regs *)QSPI_BASE;
395 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
396 priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
397 priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
398 priv->fclk = QSPI_DRA7XX_FCLK;
400 priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
401 priv->fclk = QSPI_FCLK;
404 ti_spi_set_speed(priv, max_hz);
406 #ifdef CONFIG_TI_SPI_MMAP
407 ti_spi_setup_spi_register(priv);
413 void spi_free_slave(struct spi_slave *slave)
415 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
419 int spi_claim_bus(struct spi_slave *slave)
421 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
423 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
424 __ti_qspi_set_mode(priv, priv->mode);
425 return __ti_qspi_claim_bus(priv, priv->slave.cs);
427 void spi_release_bus(struct spi_slave *slave)
429 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
431 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
432 __ti_qspi_release_bus(priv);
435 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
436 void *din, unsigned long flags)
438 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
440 debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
441 priv->slave.bus, priv->slave.cs, bitlen, flags);
442 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
445 #else /* CONFIG_DM_SPI */
447 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
448 struct spi_slave *slave,
452 u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
455 writel(0, &priv->base->setup0);
459 memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
463 memval |= QSPI_CMD_READ_QUAD;
464 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
465 memval |= QSPI_SETUP0_READ_QUAD;
466 slave->mode_rx = SPI_RX_QUAD;
469 memval |= QSPI_CMD_READ_DUAL;
470 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
471 memval |= QSPI_SETUP0_READ_DUAL;
474 memval |= QSPI_CMD_READ;
475 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
476 memval |= QSPI_SETUP0_READ_NORMAL;
480 writel(memval, &priv->base->setup0);
484 static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
486 struct ti_qspi_priv *priv = dev_get_priv(bus);
488 ti_spi_set_speed(priv, max_hz);
493 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
495 struct ti_qspi_priv *priv = dev_get_priv(bus);
496 return __ti_qspi_set_mode(priv, mode);
499 static int ti_qspi_claim_bus(struct udevice *dev)
501 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
502 struct spi_slave *slave = dev_get_parent_priv(dev);
503 struct ti_qspi_priv *priv;
507 priv = dev_get_priv(bus);
509 if (slave_plat->cs > priv->num_cs) {
510 debug("invalid qspi chip select\n");
514 __ti_qspi_setup_memorymap(priv, slave, true);
516 return __ti_qspi_claim_bus(priv, slave_plat->cs);
519 static int ti_qspi_release_bus(struct udevice *dev)
521 struct spi_slave *slave = dev_get_parent_priv(dev);
522 struct ti_qspi_priv *priv;
526 priv = dev_get_priv(bus);
528 __ti_qspi_setup_memorymap(priv, slave, false);
529 __ti_qspi_release_bus(priv);
534 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
535 const void *dout, void *din, unsigned long flags)
537 struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
538 struct ti_qspi_priv *priv;
542 priv = dev_get_priv(bus);
544 if (slave->cs > priv->num_cs) {
545 debug("invalid qspi chip select\n");
549 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
552 static int ti_qspi_probe(struct udevice *bus)
554 struct ti_qspi_priv *priv = dev_get_priv(bus);
556 priv->fclk = dev_get_driver_data(bus);
561 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
563 struct ti_qspi_priv *priv = dev_get_priv(bus);
564 const void *blob = gd->fdt_blob;
565 int node = bus->of_offset;
569 priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
571 priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
573 addr = dev_get_addr_index(bus, 2);
574 mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
575 priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
577 priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
578 if (priv->max_hz < 0) {
579 debug("Error: Max frequency missing\n");
582 priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
584 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
585 (int)priv->base, priv->max_hz);
590 static int ti_qspi_child_pre_probe(struct udevice *dev)
592 struct spi_slave *slave = dev_get_parent_priv(dev);
593 struct udevice *bus = dev_get_parent(dev);
594 struct ti_qspi_priv *priv = dev_get_priv(bus);
596 slave->memory_map = priv->memory_map;
600 static const struct dm_spi_ops ti_qspi_ops = {
601 .claim_bus = ti_qspi_claim_bus,
602 .release_bus = ti_qspi_release_bus,
603 .xfer = ti_qspi_xfer,
604 .set_speed = ti_qspi_set_speed,
605 .set_mode = ti_qspi_set_mode,
608 static const struct udevice_id ti_qspi_ids[] = {
609 { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
610 { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
614 U_BOOT_DRIVER(ti_qspi) = {
617 .of_match = ti_qspi_ids,
619 .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
620 .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
621 .probe = ti_qspi_probe,
622 .child_pre_probe = ti_qspi_child_pre_probe,
624 #endif /* CONFIG_DM_SPI */