1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2012 The Chromium OS Authors.
5 * TSC calibration codes are adapted from Linux kernel
6 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
15 #include <asm/i8254.h>
16 #include <asm/ibmpc.h>
18 #include <asm/u-boot-x86.h>
20 #define MAX_NUM_FREQS 9
22 DECLARE_GLOBAL_DATA_PTR;
25 * According to Intel 64 and IA-32 System Programming Guide,
26 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
27 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
28 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
29 * so we need manually differentiate SoC families. This is what the
30 * field msr_plat does.
33 u8 x86_family; /* CPU family */
34 u8 x86_model; /* model */
35 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
37 u32 freqs[MAX_NUM_FREQS];
40 static struct freq_desc freq_desc_tables[] = {
42 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
44 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
45 /* TNG - Intel Atom processor Z3400 series */
46 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
47 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
48 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
49 /* ANN - Intel Atom processor Z3500 series */
50 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
51 /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
52 { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
53 80000, 93300, 90000, 88900, 87500 } },
55 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
58 static int match_cpu(u8 family, u8 model)
62 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
63 if ((family == freq_desc_tables[i].x86_family) &&
64 (model == freq_desc_tables[i].x86_model))
71 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
72 #define id_to_freq(cpu_index, freq_id) \
73 (freq_desc_tables[cpu_index].freqs[freq_id])
76 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
77 * reliable and the frequency is known (provided by HW).
79 * On these platforms PIT/HPET is generally not available so calibration won't
80 * work at all and there is no other clocksource to act as a watchdog for the
81 * TSC, so we have no other choice than to trust it.
83 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
85 static unsigned long __maybe_unused cpu_mhz_from_msr(void)
87 u32 lo, hi, ratio, freq_id, freq;
91 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
94 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
98 if (freq_desc_tables[cpu_index].msr_plat) {
99 rdmsr(MSR_PLATFORM_INFO, lo, hi);
100 ratio = (lo >> 8) & 0xff;
102 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
103 ratio = (hi >> 8) & 0x1f;
105 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
107 if (freq_desc_tables[cpu_index].msr_plat == 2) {
108 /* TODO: Figure out how best to deal with this */
110 debug("Using frequency: %u KHz\n", freq);
112 /* Get FSB FREQ ID */
113 rdmsr(MSR_FSB_FREQ, lo, hi);
115 freq = id_to_freq(cpu_index, freq_id);
116 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
120 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
121 res = freq * ratio / 1000;
122 debug("TSC runs at %lu MHz\n", res);
128 * This reads the current MSB of the PIT counter, and
129 * checks if we are running on sufficiently fast and
130 * non-virtualized hardware.
132 * Our expectations are:
134 * - the PIT is running at roughly 1.19MHz
136 * - each IO is going to take about 1us on real hardware,
137 * but we allow it to be much faster (by a factor of 10) or
138 * _slightly_ slower (ie we allow up to a 2us read+counter
139 * update - anything else implies a unacceptably slow CPU
140 * or PIT for the fast calibration to work.
142 * - with 256 PIT ticks to read the value, we have 214us to
143 * see the same MSB (and overhead like doing a single TSC
144 * read per MSB value etc).
146 * - We're doing 2 reads per loop (LSB, MSB), and we expect
147 * them each to take about a microsecond on real hardware.
148 * So we expect a count value of around 100. But we'll be
149 * generous, and accept anything over 50.
151 * - if the PIT is stuck, and we see *many* more reads, we
152 * return early (and the next caller of pit_expect_msb()
153 * then consider it a failure when they don't see the
154 * next expected value).
156 * These expectations mean that we know that we have seen the
157 * transition from one expected value to another with a fairly
158 * high accuracy, and we didn't miss any events. We can thus
159 * use the TSC value at the transitions to calculate a pretty
160 * good value for the TSC frequencty.
162 static inline int pit_verify_msb(unsigned char val)
166 return inb(0x42) == val;
169 static inline int pit_expect_msb(unsigned char val, u64 *tscp,
170 unsigned long *deltap)
173 u64 tsc = 0, prev_tsc = 0;
175 for (count = 0; count < 50000; count++) {
176 if (!pit_verify_msb(val))
181 *deltap = rdtsc() - prev_tsc;
185 * We require _some_ success, but the quality control
186 * will be based on the error terms on the TSC values.
192 * How many MSB values do we want to see? We aim for
193 * a maximum error rate of 500ppm (in practice the
194 * real error is much smaller), but refuse to spend
195 * more than 50ms on it.
197 #define MAX_QUICK_PIT_MS 50
198 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
200 static unsigned long __maybe_unused quick_pit_calibrate(void)
204 unsigned long d1, d2;
206 /* Set the Gate high, disable speaker */
207 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
210 * Counter 2, mode 0 (one-shot), binary count
212 * NOTE! Mode 2 decrements by two (and then the
213 * output is flipped each time, giving the same
214 * final output frequency as a decrement-by-one),
215 * so mode 0 is much better when looking at the
220 /* Start at 0xffff */
225 * The PIT starts counting at the next edge, so we
226 * need to delay for a microsecond. The easiest way
227 * to do that is to just read back the 16-bit counter
232 if (pit_expect_msb(0xff, &tsc, &d1)) {
233 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
234 if (!pit_expect_msb(0xff-i, &delta, &d2))
238 * Iterate until the error is less than 500 ppm
241 if (d1+d2 >= delta >> 11)
245 * Check the PIT one more time to verify that
246 * all TSC reads were stable wrt the PIT.
248 * This also guarantees serialization of the
249 * last cycle read ('d2') in pit_expect_msb.
251 if (!pit_verify_msb(0xfe - i))
256 debug("Fast TSC calibration failed\n");
261 * Ok, if we get here, then we've seen the
262 * MSB of the PIT decrement 'i' times, and the
263 * error has shrunk to less than 500 ppm.
265 * As a result, we can depend on there not being
266 * any odd delays anywhere, and the TSC reads are
267 * reliable (within the error).
269 * kHz = ticks / time-in-seconds / 1000;
270 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
271 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
273 delta *= PIT_TICK_RATE;
274 delta /= (i*256*1000);
275 debug("Fast TSC calibration using PIT\n");
279 /* Get the speed of the TSC timer in MHz */
280 unsigned notrace long get_tbclk_mhz(void)
282 return get_tbclk() / 1000000;
285 static ulong get_ms_timer(void)
287 return (get_ticks() * 1000) / get_tbclk();
290 ulong get_timer(ulong base)
292 return get_ms_timer() - base;
295 ulong notrace timer_get_us(void)
297 return get_ticks() / get_tbclk_mhz();
300 ulong timer_get_boot_us(void)
302 return timer_get_us();
305 void __udelay(unsigned long usec)
307 u64 now = get_ticks();
310 stop = now + usec * get_tbclk_mhz();
312 while ((int64_t)(stop - get_ticks()) > 0)
313 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
315 * Add a 'pause' instruction on qemu target,
316 * to give other VCPUs a chance to run.
318 asm volatile("pause");
324 static int tsc_timer_get_count(struct udevice *dev, u64 *count)
326 u64 now_tick = rdtsc();
328 *count = now_tick - gd->arch.tsc_base;
333 static void tsc_timer_ensure_setup(void)
335 if (gd->arch.tsc_base)
337 gd->arch.tsc_base = rdtsc();
340 * If there is no clock frequency specified in the device tree,
341 * calibrate it by ourselves.
343 if (!gd->arch.clock_rate) {
344 unsigned long fast_calibrate;
346 fast_calibrate = cpu_mhz_from_msr();
347 if (!fast_calibrate) {
348 fast_calibrate = quick_pit_calibrate();
350 panic("TSC frequency is ZERO");
353 gd->arch.clock_rate = fast_calibrate * 1000000;
357 static int tsc_timer_probe(struct udevice *dev)
359 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
361 tsc_timer_ensure_setup();
362 uc_priv->clock_rate = gd->arch.clock_rate;
367 unsigned long notrace timer_early_get_rate(void)
369 tsc_timer_ensure_setup();
371 return gd->arch.clock_rate;
374 u64 notrace timer_early_get_count(void)
376 return rdtsc() - gd->arch.tsc_base;
379 static const struct timer_ops tsc_timer_ops = {
380 .get_count = tsc_timer_get_count,
383 static const struct udevice_id tsc_timer_ids[] = {
384 { .compatible = "x86,tsc-timer", },
388 U_BOOT_DRIVER(tsc_timer) = {
391 .of_match = tsc_timer_ids,
392 .probe = tsc_timer_probe,
393 .ops = &tsc_timer_ops,
394 .flags = DM_FLAG_PRE_RELOC,