2 * Copyright (c) 2012 The Chromium OS Authors.
4 * TSC calibration codes are adapted from Linux kernel
5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
7 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/i8254.h>
17 #include <asm/ibmpc.h>
19 #include <asm/u-boot-x86.h>
21 /* CPU reference clock frequency: in KHz */
23 #define FREQ_100 99840
24 #define FREQ_133 133200
25 #define FREQ_166 166400
27 #define MAX_NUM_FREQS 8
29 DECLARE_GLOBAL_DATA_PTR;
32 * According to Intel 64 and IA-32 System Programming Guide,
33 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
34 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
35 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
36 * so we need manually differentiate SoC families. This is what the
37 * field msr_plat does.
40 u8 x86_family; /* CPU family */
41 u8 x86_model; /* model */
42 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
44 u32 freqs[MAX_NUM_FREQS];
47 static struct freq_desc freq_desc_tables[] = {
49 { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
51 { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
53 { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
55 { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
57 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
59 { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
62 static int match_cpu(u8 family, u8 model)
66 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
67 if ((family == freq_desc_tables[i].x86_family) &&
68 (model == freq_desc_tables[i].x86_model))
75 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
76 #define id_to_freq(cpu_index, freq_id) \
77 (freq_desc_tables[cpu_index].freqs[freq_id])
80 * Do MSR calibration only for known/supported CPUs.
82 * Returns the calibration value or 0 if MSR calibration failed.
84 static unsigned long __maybe_unused try_msr_calibrate_tsc(void)
86 u32 lo, hi, ratio, freq_id, freq;
90 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
93 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
97 if (freq_desc_tables[cpu_index].msr_plat) {
98 rdmsr(MSR_PLATFORM_INFO, lo, hi);
99 ratio = (lo >> 8) & 0xff;
101 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
102 ratio = (hi >> 8) & 0x1f;
104 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
109 if (freq_desc_tables[cpu_index].msr_plat == 2) {
110 /* TODO: Figure out how best to deal with this */
112 debug("Using frequency: %u KHz\n", freq);
114 /* Get FSB FREQ ID */
115 rdmsr(MSR_FSB_FREQ, lo, hi);
117 freq = id_to_freq(cpu_index, freq_id);
118 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
124 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
125 res = freq * ratio / 1000;
126 debug("TSC runs at %lu MHz\n", res);
131 debug("Fast TSC calibration using MSR failed\n");
136 * This reads the current MSB of the PIT counter, and
137 * checks if we are running on sufficiently fast and
138 * non-virtualized hardware.
140 * Our expectations are:
142 * - the PIT is running at roughly 1.19MHz
144 * - each IO is going to take about 1us on real hardware,
145 * but we allow it to be much faster (by a factor of 10) or
146 * _slightly_ slower (ie we allow up to a 2us read+counter
147 * update - anything else implies a unacceptably slow CPU
148 * or PIT for the fast calibration to work.
150 * - with 256 PIT ticks to read the value, we have 214us to
151 * see the same MSB (and overhead like doing a single TSC
152 * read per MSB value etc).
154 * - We're doing 2 reads per loop (LSB, MSB), and we expect
155 * them each to take about a microsecond on real hardware.
156 * So we expect a count value of around 100. But we'll be
157 * generous, and accept anything over 50.
159 * - if the PIT is stuck, and we see *many* more reads, we
160 * return early (and the next caller of pit_expect_msb()
161 * then consider it a failure when they don't see the
162 * next expected value).
164 * These expectations mean that we know that we have seen the
165 * transition from one expected value to another with a fairly
166 * high accuracy, and we didn't miss any events. We can thus
167 * use the TSC value at the transitions to calculate a pretty
168 * good value for the TSC frequencty.
170 static inline int pit_verify_msb(unsigned char val)
174 return inb(0x42) == val;
177 static inline int pit_expect_msb(unsigned char val, u64 *tscp,
178 unsigned long *deltap)
181 u64 tsc = 0, prev_tsc = 0;
183 for (count = 0; count < 50000; count++) {
184 if (!pit_verify_msb(val))
189 *deltap = rdtsc() - prev_tsc;
193 * We require _some_ success, but the quality control
194 * will be based on the error terms on the TSC values.
200 * How many MSB values do we want to see? We aim for
201 * a maximum error rate of 500ppm (in practice the
202 * real error is much smaller), but refuse to spend
203 * more than 50ms on it.
205 #define MAX_QUICK_PIT_MS 50
206 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
208 static unsigned long __maybe_unused quick_pit_calibrate(void)
212 unsigned long d1, d2;
214 /* Set the Gate high, disable speaker */
215 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
218 * Counter 2, mode 0 (one-shot), binary count
220 * NOTE! Mode 2 decrements by two (and then the
221 * output is flipped each time, giving the same
222 * final output frequency as a decrement-by-one),
223 * so mode 0 is much better when looking at the
228 /* Start at 0xffff */
233 * The PIT starts counting at the next edge, so we
234 * need to delay for a microsecond. The easiest way
235 * to do that is to just read back the 16-bit counter
240 if (pit_expect_msb(0xff, &tsc, &d1)) {
241 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
242 if (!pit_expect_msb(0xff-i, &delta, &d2))
246 * Iterate until the error is less than 500 ppm
249 if (d1+d2 >= delta >> 11)
253 * Check the PIT one more time to verify that
254 * all TSC reads were stable wrt the PIT.
256 * This also guarantees serialization of the
257 * last cycle read ('d2') in pit_expect_msb.
259 if (!pit_verify_msb(0xfe - i))
264 debug("Fast TSC calibration failed\n");
269 * Ok, if we get here, then we've seen the
270 * MSB of the PIT decrement 'i' times, and the
271 * error has shrunk to less than 500 ppm.
273 * As a result, we can depend on there not being
274 * any odd delays anywhere, and the TSC reads are
275 * reliable (within the error).
277 * kHz = ticks / time-in-seconds / 1000;
278 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
279 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
281 delta *= PIT_TICK_RATE;
282 delta /= (i*256*1000);
283 debug("Fast TSC calibration using PIT\n");
287 /* Get the speed of the TSC timer in MHz */
288 unsigned notrace long get_tbclk_mhz(void)
290 return get_tbclk() / 1000000;
293 static ulong get_ms_timer(void)
295 return (get_ticks() * 1000) / get_tbclk();
298 ulong get_timer(ulong base)
300 return get_ms_timer() - base;
303 ulong notrace timer_get_us(void)
305 return get_ticks() / get_tbclk_mhz();
308 ulong timer_get_boot_us(void)
310 return timer_get_us();
313 void __udelay(unsigned long usec)
315 u64 now = get_ticks();
318 stop = now + usec * get_tbclk_mhz();
320 while ((int64_t)(stop - get_ticks()) > 0)
321 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
323 * Add a 'pause' instruction on qemu target,
324 * to give other VCPUs a chance to run.
326 asm volatile("pause");
332 static int tsc_timer_get_count(struct udevice *dev, u64 *count)
334 u64 now_tick = rdtsc();
336 *count = now_tick - gd->arch.tsc_base;
341 static int tsc_timer_probe(struct udevice *dev)
343 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
345 gd->arch.tsc_base = rdtsc();
348 * If there is no clock frequency specified in the device tree,
349 * calibrate it by ourselves.
351 if (!uc_priv->clock_rate) {
352 unsigned long fast_calibrate;
354 fast_calibrate = try_msr_calibrate_tsc();
355 if (!fast_calibrate) {
356 fast_calibrate = quick_pit_calibrate();
358 panic("TSC frequency is ZERO");
361 uc_priv->clock_rate = fast_calibrate * 1000000;
367 static const struct timer_ops tsc_timer_ops = {
368 .get_count = tsc_timer_get_count,
371 static const struct udevice_id tsc_timer_ids[] = {
372 { .compatible = "x86,tsc-timer", },
376 U_BOOT_DRIVER(tsc_timer) = {
379 .of_match = tsc_timer_ids,
380 .probe = tsc_timer_probe,
381 .ops = &tsc_timer_ops,
382 .flags = DM_FLAG_PRE_RELOC,