]> git.sur5r.net Git - u-boot/blob - drivers/tsec.c
[PATCH] nand: Fix patch merge problem
[u-boot] / drivers / tsec.c
1 /*
2  * Freescale Three Speed Ethernet Controller driver
3  *
4  * This software may be used and distributed according to the
5  * terms of the GNU Public License, Version 2, incorporated
6  * herein by reference.
7  *
8  * Copyright 2004 Freescale Semiconductor.
9  * (C) Copyright 2003, Motorola, Inc.
10  * author Andy Fleming
11  *
12  */
13
14 #include <config.h>
15 #include <common.h>
16 #include <malloc.h>
17 #include <net.h>
18 #include <command.h>
19
20 #if defined(CONFIG_TSEC_ENET)
21 #include "tsec.h"
22 #include "miiphy.h"
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #define TX_BUF_CNT              2
27
28 static uint rxIdx;              /* index of the current RX buffer */
29 static uint txIdx;              /* index of the current TX buffer */
30
31 typedef volatile struct rtxbd {
32         txbd8_t txbd[TX_BUF_CNT];
33         rxbd8_t rxbd[PKTBUFSRX];
34 } RTXBD;
35
36 struct tsec_info_struct {
37         unsigned int phyaddr;
38         u32 flags;
39         unsigned int phyregidx;
40 };
41
42 /* The tsec_info structure contains 3 values which the
43  * driver uses to determine how to operate a given ethernet
44  * device. The information needed is:
45  *  phyaddr - The address of the PHY which is attached to
46  *      the given device.
47  *
48  *  flags - This variable indicates whether the device
49  *      supports gigabit speed ethernet, and whether it should be
50  *      in reduced mode.
51  *
52  *  phyregidx - This variable specifies which ethernet device
53  *      controls the MII Management registers which are connected
54  *      to the PHY.  For now, only TSEC1 (index 0) has
55  *      access to the PHYs, so all of the entries have "0".
56  *
57  * The values specified in the table are taken from the board's
58  * config file in include/configs/.  When implementing a new
59  * board with ethernet capability, it is necessary to define:
60  *   TSECn_PHY_ADDR
61  *   TSECn_PHYIDX
62  *
63  * for n = 1,2,3, etc.  And for FEC:
64  *   FEC_PHY_ADDR
65  *   FEC_PHYIDX
66  */
67 static struct tsec_info_struct tsec_info[] = {
68 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
69         {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
70 #elif defined(CONFIG_MPC86XX_TSEC1)
71         {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
72 #else
73         {0, 0, 0},
74 #endif
75 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
76         {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
77 #elif defined(CONFIG_MPC86XX_TSEC2)
78         {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
79 #else
80         {0, 0, 0},
81 #endif
82 #ifdef CONFIG_MPC85XX_FEC
83         {FEC_PHY_ADDR, 0, FEC_PHYIDX},
84 #else
85 #if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
86         {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
87 #else
88         {0, 0, 0},
89 #endif
90 #if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
91         {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
92 #else
93         {0, 0, 0},
94 #endif
95 #endif
96 };
97
98 #define MAXCONTROLLERS  (4)
99
100 static int relocated = 0;
101
102 static struct tsec_private *privlist[MAXCONTROLLERS];
103
104 #ifdef __GNUC__
105 static RTXBD rtx __attribute__ ((aligned(8)));
106 #else
107 #error "rtx must be 64-bit aligned"
108 #endif
109
110 static int tsec_send(struct eth_device *dev,
111                      volatile void *packet, int length);
112 static int tsec_recv(struct eth_device *dev);
113 static int tsec_init(struct eth_device *dev, bd_t * bd);
114 static void tsec_halt(struct eth_device *dev);
115 static void init_registers(volatile tsec_t * regs);
116 static void startup_tsec(struct eth_device *dev);
117 static int init_phy(struct eth_device *dev);
118 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
119 uint read_phy_reg(struct tsec_private *priv, uint regnum);
120 struct phy_info *get_phy_info(struct eth_device *dev);
121 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
122 static void adjust_link(struct eth_device *dev);
123 static void relocate_cmds(void);
124 static int tsec_miiphy_write(char *devname, unsigned char addr,
125                              unsigned char reg, unsigned short value);
126 static int tsec_miiphy_read(char *devname, unsigned char addr,
127                             unsigned char reg, unsigned short *value);
128
129 /* Initialize device structure. Returns success if PHY
130  * initialization succeeded (i.e. if it recognizes the PHY)
131  */
132 int tsec_initialize(bd_t * bis, int index, char *devname)
133 {
134         struct eth_device *dev;
135         int i;
136         struct tsec_private *priv;
137
138         dev = (struct eth_device *)malloc(sizeof *dev);
139
140         if (NULL == dev)
141                 return 0;
142
143         memset(dev, 0, sizeof *dev);
144
145         priv = (struct tsec_private *)malloc(sizeof(*priv));
146
147         if (NULL == priv)
148                 return 0;
149
150         privlist[index] = priv;
151         priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
152         priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
153                                             tsec_info[index].phyregidx *
154                                             TSEC_SIZE);
155
156         priv->phyaddr = tsec_info[index].phyaddr;
157         priv->flags = tsec_info[index].flags;
158
159         sprintf(dev->name, devname);
160         dev->iobase = 0;
161         dev->priv = priv;
162         dev->init = tsec_init;
163         dev->halt = tsec_halt;
164         dev->send = tsec_send;
165         dev->recv = tsec_recv;
166
167         /* Tell u-boot to get the addr from the env */
168         for (i = 0; i < 6; i++)
169                 dev->enetaddr[i] = 0;
170
171         eth_register(dev);
172
173         /* Reset the MAC */
174         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
175         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
176
177 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
178         && !defined(BITBANGMII)
179         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
180 #endif
181
182         /* Try to initialize PHY here, and return */
183         return init_phy(dev);
184 }
185
186 /* Initializes data structures and registers for the controller,
187  * and brings the interface up.  Returns the link status, meaning
188  * that it returns success if the link is up, failure otherwise.
189  * This allows u-boot to find the first active controller.
190  */
191 int tsec_init(struct eth_device *dev, bd_t * bd)
192 {
193         uint tempval;
194         char tmpbuf[MAC_ADDR_LEN];
195         int i;
196         struct tsec_private *priv = (struct tsec_private *)dev->priv;
197         volatile tsec_t *regs = priv->regs;
198
199         /* Make sure the controller is stopped */
200         tsec_halt(dev);
201
202         /* Init MACCFG2.  Defaults to GMII */
203         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
204
205         /* Init ECNTRL */
206         regs->ecntrl = ECNTRL_INIT_SETTINGS;
207
208         /* Copy the station address into the address registers.
209          * Backwards, because little endian MACS are dumb */
210         for (i = 0; i < MAC_ADDR_LEN; i++) {
211                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
212         }
213         regs->macstnaddr1 = *((uint *) (tmpbuf));
214
215         tempval = *((uint *) (tmpbuf + 4));
216
217         regs->macstnaddr2 = tempval;
218
219         /* reset the indices to zero */
220         rxIdx = 0;
221         txIdx = 0;
222
223         /* Clear out (for the most part) the other registers */
224         init_registers(regs);
225
226         /* Ready the device for tx/rx */
227         startup_tsec(dev);
228
229         /* If there's no link, fail */
230         return priv->link;
231
232 }
233
234 /* Write value to the device's PHY through the registers
235  * specified in priv, modifying the register specified in regnum.
236  * It will wait for the write to be done (or for a timeout to
237  * expire) before exiting
238  */
239 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
240 {
241         volatile tsec_t *regbase = priv->phyregs;
242         uint phyid = priv->phyaddr;
243         int timeout = 1000000;
244
245         regbase->miimadd = (phyid << 8) | regnum;
246         regbase->miimcon = value;
247         asm("sync");
248
249         timeout = 1000000;
250         while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
251 }
252
253 /* Reads register regnum on the device's PHY through the
254  * registers specified in priv.  It lowers and raises the read
255  * command, and waits for the data to become valid (miimind
256  * notvalid bit cleared), and the bus to cease activity (miimind
257  * busy bit cleared), and then returns the value
258  */
259 uint read_phy_reg(struct tsec_private *priv, uint regnum)
260 {
261         uint value;
262         volatile tsec_t *regbase = priv->phyregs;
263         uint phyid = priv->phyaddr;
264
265         /* Put the address of the phy, and the register
266          * number into MIIMADD */
267         regbase->miimadd = (phyid << 8) | regnum;
268
269         /* Clear the command register, and wait */
270         regbase->miimcom = 0;
271         asm("sync");
272
273         /* Initiate a read command, and wait */
274         regbase->miimcom = MIIM_READ_COMMAND;
275         asm("sync");
276
277         /* Wait for the the indication that the read is done */
278         while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
279
280         /* Grab the value read from the PHY */
281         value = regbase->miimstat;
282
283         return value;
284 }
285
286 /* Discover which PHY is attached to the device, and configure it
287  * properly.  If the PHY is not recognized, then return 0
288  * (failure).  Otherwise, return 1
289  */
290 static int init_phy(struct eth_device *dev)
291 {
292         struct tsec_private *priv = (struct tsec_private *)dev->priv;
293         struct phy_info *curphy;
294         volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
295
296         /* Assign a Physical address to the TBI */
297         regs->tbipa = TBIPA_VALUE;
298         regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
299         regs->tbipa = TBIPA_VALUE;
300         asm("sync");
301
302         /* Reset MII (due to new addresses) */
303         priv->phyregs->miimcfg = MIIMCFG_RESET;
304         asm("sync");
305         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
306         asm("sync");
307         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
308
309         if (0 == relocated)
310                 relocate_cmds();
311
312         /* Get the cmd structure corresponding to the attached
313          * PHY */
314         curphy = get_phy_info(dev);
315
316         if (curphy == NULL) {
317                 priv->phyinfo = NULL;
318                 printf("%s: No PHY found\n", dev->name);
319
320                 return 0;
321         }
322
323         priv->phyinfo = curphy;
324
325         phy_run_commands(priv, priv->phyinfo->config);
326
327         return 1;
328 }
329
330 /*
331  * Returns which value to write to the control register.
332  * For 10/100, the value is slightly different
333  */
334 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
335 {
336         if (priv->flags & TSEC_GIGABIT)
337                 return MIIM_CONTROL_INIT;
338         else
339                 return MIIM_CR_INIT;
340 }
341
342 /* Parse the status register for link, and then do
343  * auto-negotiation
344  */
345 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
346 {
347         /*
348          * Wait if PHY is capable of autonegotiation and autonegotiation
349          * is not complete.
350          */
351         mii_reg = read_phy_reg(priv, MIIM_STATUS);
352         if ((mii_reg & PHY_BMSR_AUTN_ABLE)
353             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
354                 int i = 0;
355
356                 puts("Waiting for PHY auto negotiation to complete");
357                 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
358                          && (mii_reg & MIIM_STATUS_LINK))) {
359                         /*
360                          * Timeout reached ?
361                          */
362                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
363                                 puts(" TIMEOUT !\n");
364                                 priv->link = 0;
365                                 return 0;
366                         }
367
368                         if ((i++ % 1000) == 0) {
369                                 putc('.');
370                         }
371                         udelay(1000);   /* 1 ms */
372                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
373                 }
374                 puts(" done\n");
375                 priv->link = 1;
376                 udelay(500000); /* another 500 ms (results in faster booting) */
377         } else {
378                 priv->link = 1;
379         }
380
381         return 0;
382 }
383
384 /* Parse the 88E1011's status register for speed and duplex
385  * information
386  */
387 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
388 {
389         uint speed;
390
391         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
392
393         if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
394               (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
395                 int i = 0;
396
397                 puts("Waiting for PHY realtime link");
398                 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
399                          (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
400                         /*
401                          * Timeout reached ?
402                          */
403                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
404                                 puts(" TIMEOUT !\n");
405                                 priv->link = 0;
406                                 break;
407                         }
408
409                         if ((i++ % 1000) == 0) {
410                                 putc('.');
411                         }
412                         udelay(1000);   /* 1 ms */
413                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
414                 }
415                 puts(" done\n");
416                 udelay(500000); /* another 500 ms (results in faster booting) */
417         }
418
419         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
420                 priv->duplexity = 1;
421         else
422                 priv->duplexity = 0;
423
424         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
425
426         switch (speed) {
427         case MIIM_88E1011_PHYSTAT_GBIT:
428                 priv->speed = 1000;
429                 break;
430         case MIIM_88E1011_PHYSTAT_100:
431                 priv->speed = 100;
432                 break;
433         default:
434                 priv->speed = 10;
435         }
436
437         return 0;
438 }
439
440 /* Parse the cis8201's status register for speed and duplex
441  * information
442  */
443 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
444 {
445         uint speed;
446
447         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
448                 priv->duplexity = 1;
449         else
450                 priv->duplexity = 0;
451
452         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
453         switch (speed) {
454         case MIIM_CIS8201_AUXCONSTAT_GBIT:
455                 priv->speed = 1000;
456                 break;
457         case MIIM_CIS8201_AUXCONSTAT_100:
458                 priv->speed = 100;
459                 break;
460         default:
461                 priv->speed = 10;
462                 break;
463         }
464
465         return 0;
466 }
467
468 /* Parse the vsc8244's status register for speed and duplex
469  * information
470  */
471 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
472 {
473         uint speed;
474
475         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
476                 priv->duplexity = 1;
477         else
478                 priv->duplexity = 0;
479
480         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
481         switch (speed) {
482         case MIIM_VSC8244_AUXCONSTAT_GBIT:
483                 priv->speed = 1000;
484                 break;
485         case MIIM_VSC8244_AUXCONSTAT_100:
486                 priv->speed = 100;
487                 break;
488         default:
489                 priv->speed = 10;
490                 break;
491         }
492
493         return 0;
494 }
495
496 /* Parse the DM9161's status register for speed and duplex
497  * information
498  */
499 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
500 {
501         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
502                 priv->speed = 100;
503         else
504                 priv->speed = 10;
505
506         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
507                 priv->duplexity = 1;
508         else
509                 priv->duplexity = 0;
510
511         return 0;
512 }
513
514 /*
515  * Hack to write all 4 PHYs with the LED values
516  */
517 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
518 {
519         uint phyid;
520         volatile tsec_t *regbase = priv->phyregs;
521         int timeout = 1000000;
522
523         for (phyid = 0; phyid < 4; phyid++) {
524                 regbase->miimadd = (phyid << 8) | mii_reg;
525                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
526                 asm("sync");
527
528                 timeout = 1000000;
529                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
530         }
531
532         return MIIM_CIS8204_SLEDCON_INIT;
533 }
534
535 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
536 {
537         if (priv->flags & TSEC_REDUCED)
538                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
539         else
540                 return MIIM_CIS8204_EPHYCON_INIT;
541 }
542
543 /* Initialized required registers to appropriate values, zeroing
544  * those we don't care about (unless zero is bad, in which case,
545  * choose a more appropriate value)
546  */
547 static void init_registers(volatile tsec_t * regs)
548 {
549         /* Clear IEVENT */
550         regs->ievent = IEVENT_INIT_CLEAR;
551
552         regs->imask = IMASK_INIT_CLEAR;
553
554         regs->hash.iaddr0 = 0;
555         regs->hash.iaddr1 = 0;
556         regs->hash.iaddr2 = 0;
557         regs->hash.iaddr3 = 0;
558         regs->hash.iaddr4 = 0;
559         regs->hash.iaddr5 = 0;
560         regs->hash.iaddr6 = 0;
561         regs->hash.iaddr7 = 0;
562
563         regs->hash.gaddr0 = 0;
564         regs->hash.gaddr1 = 0;
565         regs->hash.gaddr2 = 0;
566         regs->hash.gaddr3 = 0;
567         regs->hash.gaddr4 = 0;
568         regs->hash.gaddr5 = 0;
569         regs->hash.gaddr6 = 0;
570         regs->hash.gaddr7 = 0;
571
572         regs->rctrl = 0x00000000;
573
574         /* Init RMON mib registers */
575         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
576
577         regs->rmon.cam1 = 0xffffffff;
578         regs->rmon.cam2 = 0xffffffff;
579
580         regs->mrblr = MRBLR_INIT_SETTINGS;
581
582         regs->minflr = MINFLR_INIT_SETTINGS;
583
584         regs->attr = ATTR_INIT_SETTINGS;
585         regs->attreli = ATTRELI_INIT_SETTINGS;
586
587 }
588
589 /* Configure maccfg2 based on negotiated speed and duplex
590  * reported by PHY handling code
591  */
592 static void adjust_link(struct eth_device *dev)
593 {
594         struct tsec_private *priv = (struct tsec_private *)dev->priv;
595         volatile tsec_t *regs = priv->regs;
596
597         if (priv->link) {
598                 if (priv->duplexity != 0)
599                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
600                 else
601                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
602
603                 switch (priv->speed) {
604                 case 1000:
605                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
606                                          | MACCFG2_GMII);
607                         break;
608                 case 100:
609                 case 10:
610                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
611                                          | MACCFG2_MII);
612
613                         /* If We're in reduced mode, we need
614                          * to say whether we're 10 or 100 MB.
615                          */
616                         if ((priv->speed == 100)
617                             && (priv->flags & TSEC_REDUCED))
618                                 regs->ecntrl |= ECNTRL_R100;
619                         else
620                                 regs->ecntrl &= ~(ECNTRL_R100);
621                         break;
622                 default:
623                         printf("%s: Speed was bad\n", dev->name);
624                         break;
625                 }
626
627                 printf("Speed: %d, %s duplex\n", priv->speed,
628                        (priv->duplexity) ? "full" : "half");
629
630         } else {
631                 printf("%s: No link.\n", dev->name);
632         }
633 }
634
635 /* Set up the buffers and their descriptors, and bring up the
636  * interface
637  */
638 static void startup_tsec(struct eth_device *dev)
639 {
640         int i;
641         struct tsec_private *priv = (struct tsec_private *)dev->priv;
642         volatile tsec_t *regs = priv->regs;
643
644         /* Point to the buffer descriptors */
645         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
646         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
647
648         /* Initialize the Rx Buffer descriptors */
649         for (i = 0; i < PKTBUFSRX; i++) {
650                 rtx.rxbd[i].status = RXBD_EMPTY;
651                 rtx.rxbd[i].length = 0;
652                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
653         }
654         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
655
656         /* Initialize the TX Buffer Descriptors */
657         for (i = 0; i < TX_BUF_CNT; i++) {
658                 rtx.txbd[i].status = 0;
659                 rtx.txbd[i].length = 0;
660                 rtx.txbd[i].bufPtr = 0;
661         }
662         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
663
664         /* Start up the PHY */
665         if(priv->phyinfo)
666                 phy_run_commands(priv, priv->phyinfo->startup);
667         adjust_link(dev);
668
669         /* Enable Transmit and Receive */
670         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
671
672         /* Tell the DMA it is clear to go */
673         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
674         regs->tstat = TSTAT_CLEAR_THALT;
675         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
676 }
677
678 /* This returns the status bits of the device.  The return value
679  * is never checked, and this is what the 8260 driver did, so we
680  * do the same.  Presumably, this would be zero if there were no
681  * errors
682  */
683 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
684 {
685         int i;
686         int result = 0;
687         struct tsec_private *priv = (struct tsec_private *)dev->priv;
688         volatile tsec_t *regs = priv->regs;
689
690         /* Find an empty buffer descriptor */
691         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
692                 if (i >= TOUT_LOOP) {
693                         debug("%s: tsec: tx buffers full\n", dev->name);
694                         return result;
695                 }
696         }
697
698         rtx.txbd[txIdx].bufPtr = (uint) packet;
699         rtx.txbd[txIdx].length = length;
700         rtx.txbd[txIdx].status |=
701             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
702
703         /* Tell the DMA to go */
704         regs->tstat = TSTAT_CLEAR_THALT;
705
706         /* Wait for buffer to be transmitted */
707         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
708                 if (i >= TOUT_LOOP) {
709                         debug("%s: tsec: tx error\n", dev->name);
710                         return result;
711                 }
712         }
713
714         txIdx = (txIdx + 1) % TX_BUF_CNT;
715         result = rtx.txbd[txIdx].status & TXBD_STATS;
716
717         return result;
718 }
719
720 static int tsec_recv(struct eth_device *dev)
721 {
722         int length;
723         struct tsec_private *priv = (struct tsec_private *)dev->priv;
724         volatile tsec_t *regs = priv->regs;
725
726         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
727
728                 length = rtx.rxbd[rxIdx].length;
729
730                 /* Send the packet up if there were no errors */
731                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
732                         NetReceive(NetRxPackets[rxIdx], length - 4);
733                 } else {
734                         printf("Got error %x\n",
735                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
736                 }
737
738                 rtx.rxbd[rxIdx].length = 0;
739
740                 /* Set the wrap bit if this is the last element in the list */
741                 rtx.rxbd[rxIdx].status =
742                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
743
744                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
745         }
746
747         if (regs->ievent & IEVENT_BSY) {
748                 regs->ievent = IEVENT_BSY;
749                 regs->rstat = RSTAT_CLEAR_RHALT;
750         }
751
752         return -1;
753
754 }
755
756 /* Stop the interface */
757 static void tsec_halt(struct eth_device *dev)
758 {
759         struct tsec_private *priv = (struct tsec_private *)dev->priv;
760         volatile tsec_t *regs = priv->regs;
761
762         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
763         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
764
765         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
766
767         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
768
769         /* Shut down the PHY, as needed */
770         if(priv->phyinfo)
771                 phy_run_commands(priv, priv->phyinfo->shutdown);
772 }
773
774 struct phy_info phy_info_M88E1011S = {
775         0x01410c6,
776         "Marvell 88E1011S",
777         4,
778         (struct phy_cmd[]){     /* config */
779                            /* Reset and configure the PHY */
780                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
781                            {0x1d, 0x1f, NULL},
782                            {0x1e, 0x200c, NULL},
783                            {0x1d, 0x5, NULL},
784                            {0x1e, 0x0, NULL},
785                            {0x1e, 0x100, NULL},
786                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
787                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
788                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
789                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
790                            {miim_end,}
791                            },
792         (struct phy_cmd[]){     /* startup */
793                            /* Status is read once to clear old link state */
794                            {MIIM_STATUS, miim_read, NULL},
795                            /* Auto-negotiate */
796                            {MIIM_STATUS, miim_read, &mii_parse_sr},
797                            /* Read the status */
798                            {MIIM_88E1011_PHY_STATUS, miim_read,
799                             &mii_parse_88E1011_psr},
800                            {miim_end,}
801                            },
802         (struct phy_cmd[]){     /* shutdown */
803                            {miim_end,}
804                            },
805 };
806
807 struct phy_info phy_info_M88E1111S = {
808         0x01410cc,
809         "Marvell 88E1111S",
810         4,
811         (struct phy_cmd[]){     /* config */
812                            /* Reset and configure the PHY */
813                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
814                            {0x1d, 0x1f, NULL},
815                            {0x1e, 0x200c, NULL},
816                            {0x1d, 0x5, NULL},
817                            {0x1e, 0x0, NULL},
818                            {0x1e, 0x100, NULL},
819                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
820                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
821                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
822                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
823                            {miim_end,}
824                            },
825         (struct phy_cmd[]){     /* startup */
826                            /* Status is read once to clear old link state */
827                            {MIIM_STATUS, miim_read, NULL},
828                            /* Auto-negotiate */
829                            {MIIM_STATUS, miim_read, &mii_parse_sr},
830                            /* Read the status */
831                            {MIIM_88E1011_PHY_STATUS, miim_read,
832                             &mii_parse_88E1011_psr},
833                            {miim_end,}
834                            },
835         (struct phy_cmd[]){     /* shutdown */
836                            {miim_end,}
837                            },
838 };
839
840 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
841 {
842         uint mii_data = read_phy_reg(priv, mii_reg);
843
844         /* Setting MIIM_88E1145_PHY_EXT_CR */
845         if (priv->flags & TSEC_REDUCED)
846                 return mii_data |
847                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
848         else
849                 return mii_data;
850 }
851
852 static struct phy_info phy_info_M88E1145 = {
853         0x01410cd,
854         "Marvell 88E1145",
855         4,
856         (struct phy_cmd[]){     /* config */
857                            /* Errata E0, E1 */
858                            {29, 0x001b, NULL},
859                            {30, 0x418f, NULL},
860                            {29, 0x0016, NULL},
861                            {30, 0xa2da, NULL},
862
863                            /* Reset and configure the PHY */
864                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
865                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
866                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
867                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
868                             NULL},
869                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
870                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
871                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
872                            {miim_end,}
873                            },
874         (struct phy_cmd[]){     /* startup */
875                            /* Status is read once to clear old link state */
876                            {MIIM_STATUS, miim_read, NULL},
877                            /* Auto-negotiate */
878                            {MIIM_STATUS, miim_read, &mii_parse_sr},
879                            {MIIM_88E1111_PHY_LED_CONTROL,
880                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
881                            /* Read the Status */
882                            {MIIM_88E1011_PHY_STATUS, miim_read,
883                             &mii_parse_88E1011_psr},
884                            {miim_end,}
885                            },
886         (struct phy_cmd[]){     /* shutdown */
887                            {miim_end,}
888                            },
889 };
890
891 struct phy_info phy_info_cis8204 = {
892         0x3f11,
893         "Cicada Cis8204",
894         6,
895         (struct phy_cmd[]){     /* config */
896                            /* Override PHY config settings */
897                            {MIIM_CIS8201_AUX_CONSTAT,
898                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
899                            /* Configure some basic stuff */
900                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
901                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
902                             &mii_cis8204_fixled},
903                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
904                             &mii_cis8204_setmode},
905                            {miim_end,}
906                            },
907         (struct phy_cmd[]){     /* startup */
908                            /* Read the Status (2x to make sure link is right) */
909                            {MIIM_STATUS, miim_read, NULL},
910                            /* Auto-negotiate */
911                            {MIIM_STATUS, miim_read, &mii_parse_sr},
912                            /* Read the status */
913                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
914                             &mii_parse_cis8201},
915                            {miim_end,}
916                            },
917         (struct phy_cmd[]){     /* shutdown */
918                            {miim_end,}
919                            },
920 };
921
922 /* Cicada 8201 */
923 struct phy_info phy_info_cis8201 = {
924         0xfc41,
925         "CIS8201",
926         4,
927         (struct phy_cmd[]){     /* config */
928                            /* Override PHY config settings */
929                            {MIIM_CIS8201_AUX_CONSTAT,
930                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
931                            /* Set up the interface mode */
932                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
933                             NULL},
934                            /* Configure some basic stuff */
935                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
936                            {miim_end,}
937                            },
938         (struct phy_cmd[]){     /* startup */
939                            /* Read the Status (2x to make sure link is right) */
940                            {MIIM_STATUS, miim_read, NULL},
941                            /* Auto-negotiate */
942                            {MIIM_STATUS, miim_read, &mii_parse_sr},
943                            /* Read the status */
944                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
945                             &mii_parse_cis8201},
946                            {miim_end,}
947                            },
948         (struct phy_cmd[]){     /* shutdown */
949                            {miim_end,}
950                            },
951 };
952 struct phy_info phy_info_VSC8244 = {
953         0x3f1b,
954         "Vitesse VSC8244",
955         6,
956         (struct phy_cmd[]){     /* config */
957                            /* Override PHY config settings */
958                            /* Configure some basic stuff */
959                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
960                            {miim_end,}
961                            },
962         (struct phy_cmd[]){     /* startup */
963                            /* Read the Status (2x to make sure link is right) */
964                            {MIIM_STATUS, miim_read, NULL},
965                            /* Auto-negotiate */
966                            {MIIM_STATUS, miim_read, &mii_parse_sr},
967                            /* Read the status */
968                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
969                             &mii_parse_vsc8244},
970                            {miim_end,}
971                            },
972         (struct phy_cmd[]){     /* shutdown */
973                            {miim_end,}
974                            },
975 };
976
977 struct phy_info phy_info_dm9161 = {
978         0x0181b88,
979         "Davicom DM9161E",
980         4,
981         (struct phy_cmd[]){     /* config */
982                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
983                            /* Do not bypass the scrambler/descrambler */
984                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
985                            /* Clear 10BTCSR to default */
986                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
987                             NULL},
988                            /* Configure some basic stuff */
989                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
990                            /* Restart Auto Negotiation */
991                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
992                            {miim_end,}
993                            },
994         (struct phy_cmd[]){     /* startup */
995                            /* Status is read once to clear old link state */
996                            {MIIM_STATUS, miim_read, NULL},
997                            /* Auto-negotiate */
998                            {MIIM_STATUS, miim_read, &mii_parse_sr},
999                            /* Read the status */
1000                            {MIIM_DM9161_SCSR, miim_read,
1001                             &mii_parse_dm9161_scsr},
1002                            {miim_end,}
1003                            },
1004         (struct phy_cmd[]){     /* shutdown */
1005                            {miim_end,}
1006                            },
1007 };
1008
1009 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1010 {
1011         unsigned int speed;
1012         if (priv->link) {
1013                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1014
1015                 switch (speed) {
1016                 case MIIM_LXT971_SR2_10HDX:
1017                         priv->speed = 10;
1018                         priv->duplexity = 0;
1019                         break;
1020                 case MIIM_LXT971_SR2_10FDX:
1021                         priv->speed = 10;
1022                         priv->duplexity = 1;
1023                         break;
1024                 case MIIM_LXT971_SR2_100HDX:
1025                         priv->speed = 100;
1026                         priv->duplexity = 0;
1027                 default:
1028                         priv->speed = 100;
1029                         priv->duplexity = 1;
1030                         break;
1031                 }
1032         } else {
1033                 priv->speed = 0;
1034                 priv->duplexity = 0;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static struct phy_info phy_info_lxt971 = {
1041         0x0001378e,
1042         "LXT971",
1043         4,
1044         (struct phy_cmd[]){     /* config */
1045                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1046                            {miim_end,}
1047                            },
1048         (struct phy_cmd[]){     /* startup - enable interrupts */
1049                            /* { 0x12, 0x00f2, NULL }, */
1050                            {MIIM_STATUS, miim_read, NULL},
1051                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1052                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1053                            {miim_end,}
1054                            },
1055         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1056                            {miim_end,}
1057                            },
1058 };
1059
1060 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1061  * information
1062  */
1063 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1064 {
1065         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1066
1067         case MIIM_DP83865_SPD_1000:
1068                 priv->speed = 1000;
1069                 break;
1070
1071         case MIIM_DP83865_SPD_100:
1072                 priv->speed = 100;
1073                 break;
1074
1075         default:
1076                 priv->speed = 10;
1077                 break;
1078
1079         }
1080
1081         if (mii_reg & MIIM_DP83865_DPX_FULL)
1082                 priv->duplexity = 1;
1083         else
1084                 priv->duplexity = 0;
1085
1086         return 0;
1087 }
1088
1089 struct phy_info phy_info_dp83865 = {
1090         0x20005c7,
1091         "NatSemi DP83865",
1092         4,
1093         (struct phy_cmd[]){     /* config */
1094                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1095                            {miim_end,}
1096                            },
1097         (struct phy_cmd[]){     /* startup */
1098                            /* Status is read once to clear old link state */
1099                            {MIIM_STATUS, miim_read, NULL},
1100                            /* Auto-negotiate */
1101                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1102                            /* Read the link and auto-neg status */
1103                            {MIIM_DP83865_LANR, miim_read,
1104                             &mii_parse_dp83865_lanr},
1105                            {miim_end,}
1106                            },
1107         (struct phy_cmd[]){     /* shutdown */
1108                            {miim_end,}
1109                            },
1110 };
1111
1112 struct phy_info *phy_info[] = {
1113 #if 0
1114         &phy_info_cis8201,
1115 #endif
1116         &phy_info_cis8204,
1117         &phy_info_M88E1011S,
1118         &phy_info_M88E1111S,
1119         &phy_info_M88E1145,
1120         &phy_info_dm9161,
1121         &phy_info_lxt971,
1122         &phy_info_VSC8244,
1123         &phy_info_dp83865,
1124         NULL
1125 };
1126
1127 /* Grab the identifier of the device's PHY, and search through
1128  * all of the known PHYs to see if one matches.  If so, return
1129  * it, if not, return NULL
1130  */
1131 struct phy_info *get_phy_info(struct eth_device *dev)
1132 {
1133         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1134         uint phy_reg, phy_ID;
1135         int i;
1136         struct phy_info *theInfo = NULL;
1137
1138         /* Grab the bits from PHYIR1, and put them in the upper half */
1139         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1140         phy_ID = (phy_reg & 0xffff) << 16;
1141
1142         /* Grab the bits from PHYIR2, and put them in the lower half */
1143         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1144         phy_ID |= (phy_reg & 0xffff);
1145
1146         /* loop through all the known PHY types, and find one that */
1147         /* matches the ID we read from the PHY. */
1148         for (i = 0; phy_info[i]; i++) {
1149                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
1150                         theInfo = phy_info[i];
1151         }
1152
1153         if (theInfo == NULL) {
1154                 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1155                 return NULL;
1156         } else {
1157                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1158         }
1159
1160         return theInfo;
1161 }
1162
1163 /* Execute the given series of commands on the given device's
1164  * PHY, running functions as necessary
1165  */
1166 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1167 {
1168         int i;
1169         uint result;
1170         volatile tsec_t *phyregs = priv->phyregs;
1171
1172         phyregs->miimcfg = MIIMCFG_RESET;
1173
1174         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1175
1176         while (phyregs->miimind & MIIMIND_BUSY) ;
1177
1178         for (i = 0; cmd->mii_reg != miim_end; i++) {
1179                 if (cmd->mii_data == miim_read) {
1180                         result = read_phy_reg(priv, cmd->mii_reg);
1181
1182                         if (cmd->funct != NULL)
1183                                 (*(cmd->funct)) (result, priv);
1184
1185                 } else {
1186                         if (cmd->funct != NULL)
1187                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1188                         else
1189                                 result = cmd->mii_data;
1190
1191                         write_phy_reg(priv, cmd->mii_reg, result);
1192
1193                 }
1194                 cmd++;
1195         }
1196 }
1197
1198 /* Relocate the function pointers in the phy cmd lists */
1199 static void relocate_cmds(void)
1200 {
1201         struct phy_cmd **cmdlistptr;
1202         struct phy_cmd *cmd;
1203         int i, j, k;
1204
1205         for (i = 0; phy_info[i]; i++) {
1206                 /* First thing's first: relocate the pointers to the
1207                  * PHY command structures (the structs were done) */
1208                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1209                                                   + gd->reloc_off);
1210                 phy_info[i]->name += gd->reloc_off;
1211                 phy_info[i]->config =
1212                     (struct phy_cmd *)((uint) phy_info[i]->config
1213                                        + gd->reloc_off);
1214                 phy_info[i]->startup =
1215                     (struct phy_cmd *)((uint) phy_info[i]->startup
1216                                        + gd->reloc_off);
1217                 phy_info[i]->shutdown =
1218                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1219                                        + gd->reloc_off);
1220
1221                 cmdlistptr = &phy_info[i]->config;
1222                 j = 0;
1223                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1224                         k = 0;
1225                         for (cmd = *cmdlistptr;
1226                              cmd->mii_reg != miim_end;
1227                              cmd++) {
1228                                 /* Only relocate non-NULL pointers */
1229                                 if (cmd->funct)
1230                                         cmd->funct += gd->reloc_off;
1231
1232                                 k++;
1233                         }
1234                         j++;
1235                 }
1236         }
1237
1238         relocated = 1;
1239 }
1240
1241 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
1242         && !defined(BITBANGMII)
1243
1244 struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
1245 {
1246         int i;
1247
1248         for (i = 0; i < MAXCONTROLLERS; i++) {
1249                 if (privlist[i]->phyaddr == phyaddr)
1250                         return privlist[i];
1251         }
1252
1253         return NULL;
1254 }
1255
1256 /*
1257  * Read a MII PHY register.
1258  *
1259  * Returns:
1260  *  0 on success
1261  */
1262 static int tsec_miiphy_read(char *devname, unsigned char addr,
1263                             unsigned char reg, unsigned short *value)
1264 {
1265         unsigned short ret;
1266         struct tsec_private *priv = get_priv_for_phy(addr);
1267
1268         if (NULL == priv) {
1269                 printf("Can't read PHY at address %d\n", addr);
1270                 return -1;
1271         }
1272
1273         ret = (unsigned short)read_phy_reg(priv, reg);
1274         *value = ret;
1275
1276         return 0;
1277 }
1278
1279 /*
1280  * Write a MII PHY register.
1281  *
1282  * Returns:
1283  *  0 on success
1284  */
1285 static int tsec_miiphy_write(char *devname, unsigned char addr,
1286                              unsigned char reg, unsigned short value)
1287 {
1288         struct tsec_private *priv = get_priv_for_phy(addr);
1289
1290         if (NULL == priv) {
1291                 printf("Can't write PHY at address %d\n", addr);
1292                 return -1;
1293         }
1294
1295         write_phy_reg(priv, reg, value);
1296
1297         return 0;
1298 }
1299
1300 #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1301                 && !defined(BITBANGMII) */
1302
1303 #endif /* CONFIG_TSEC_ENET */