2 * (C) Copyright 2004 Tundra Semiconductor Corp.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #ifdef CONFIG_TSI108_I2C
32 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
34 #define I2C_DELAY 100000
38 #define DPRINT(x) printf(x)
43 /* All functions assume that Tsi108 I2C block is the only master on the bus */
44 /* I2C read helper function */
46 static int i2c_read_byte(
47 uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
48 uchar chip_addr,/* I2C device address on the bus */
49 uint byte_addr, /* Byte address within I2C device */
50 uchar * buffer /* pointer to data buffer */
54 u32 to_count = I2C_DELAY;
55 u32 op_status = TSI108_I2C_TIMEOUT_ERR;
56 u32 chan_offset = TSI108_I2C_OFFSET;
58 DPRINT(("I2C read_byte() %d 0x%02x 0x%02x\n",
59 i2c_chan, chip_addr, byte_addr));
62 chan_offset = TSI108_I2C_SDRAM_OFFSET;
65 /* Check if I2C operation is in progress */
66 temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
68 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
71 /* Set device address and operation (read = 0) */
72 temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
73 ((chip_addr >> 3) & 0x0F);
74 *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) =
77 /* Issue the read command
78 * (at this moment all other parameters are 0
79 * (size = 1 byte, lane = 0)
82 *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) =
85 /* Wait until operation completed */
87 /* Read I2C operation status */
89 *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset +
93 (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START)))
97 (I2C_CNTRL2_I2C_CFGERR |
98 I2C_CNTRL2_I2C_TO_ERR))
100 op_status = TSI108_I2C_SUCCESS;
102 temp = *(u32 *) (CFG_TSI108_CSR_BASE +
106 *buffer = (u8) (temp & 0xFF);
108 /* report HW error */
109 op_status = TSI108_I2C_IF_ERROR;
111 DPRINT(("I2C HW error reported: 0x%02x\n", temp));
116 } while (to_count--);
118 op_status = TSI108_I2C_IF_BUSY;
120 DPRINT(("I2C Transaction start failed: 0x%02x\n", temp));
123 DPRINT(("I2C read_byte() status: 0x%02x\n", op_status));
128 * I2C Read interface as defined in "include/i2c.h" :
129 * chip_addr: I2C chip address, range 0..127
130 * (to read from SPD channel EEPROM use (0xD0 ... 0xD7)
131 * NOTE: The bit 7 in the chip_addr serves as a channel select.
132 * This hack is for enabling "isdram" command on Tsi108 boards
133 * without changes to common code. Used for I2C reads only.
134 * byte_addr: Memory or register address within the chip
135 * alen: Number of bytes to use for addr (typically 1, 2 for larger
136 * memories, 0 for register type devices with only one
138 * buffer: Pointer to destination buffer for data to be read
139 * len: How many bytes to read
141 * Returns: 0 on success, not 0 on failure
144 int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len)
146 u32 op_status = TSI108_I2C_PARAM_ERR;
149 /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/
150 if (0xD0 == (chip_addr & ~0x07)) {
154 /* Check for valid I2C address */
155 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
158 i2c_read_byte(i2c_if, chip_addr, byte_addr++,
161 if (TSI108_I2C_SUCCESS != op_status) {
162 DPRINT(("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
169 DPRINT(("I2C read() status: 0x%02x\n", op_status));
173 /* I2C write helper function */
175 static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
176 uint byte_addr, /* Byte address within I2C device */
177 uchar * buffer /* pointer to data buffer */
181 u32 to_count = I2C_DELAY;
182 u32 op_status = TSI108_I2C_TIMEOUT_ERR;
184 /* Check if I2C operation is in progress */
185 temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
189 (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
191 /* Place data into the I2C Tx Register */
192 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
193 I2C_TX_DATA) = (u32) * buffer;
195 /* Set device address and operation */
197 I2C_CNTRL1_I2CWRITE | (byte_addr << 16) |
198 ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F);
199 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
202 /* Issue the write command (at this moment all other parameters
203 * are 0 (size = 1 byte, lane = 0)
206 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
207 I2C_CNTRL2) = (I2C_CNTRL2_START);
209 op_status = TSI108_I2C_TIMEOUT_ERR;
211 /* Wait until operation completed */
213 // Read I2C operation status
215 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
219 (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
223 (I2C_CNTRL2_I2C_CFGERR |
224 I2C_CNTRL2_I2C_TO_ERR))) {
225 op_status = TSI108_I2C_SUCCESS;
227 /* report detected HW error */
228 op_status = TSI108_I2C_IF_ERROR;
230 DPRINT(("I2C HW error reported: 0x%02x\n", temp));
236 } while (to_count--);
238 op_status = TSI108_I2C_IF_BUSY;
240 DPRINT(("I2C Transaction start failed: 0x%02x\n", temp));
247 * I2C Write interface as defined in "include/i2c.h" :
248 * chip_addr: I2C chip address, range 0..127
249 * byte_addr: Memory or register address within the chip
250 * alen: Number of bytes to use for addr (typically 1, 2 for larger
251 * memories, 0 for register type devices with only one
253 * buffer: Pointer to data to be written
254 * len: How many bytes to write
256 * Returns: 0 on success, not 0 on failure
259 int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
262 u32 op_status = TSI108_I2C_PARAM_ERR;
264 /* Check for valid I2C address */
265 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
268 i2c_write_byte(chip_addr, byte_addr++, buffer++);
270 if (TSI108_I2C_SUCCESS != op_status) {
271 DPRINT(("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
282 * I2C interface function as defined in "include/i2c.h".
283 * Probe the given I2C chip address by reading single byte from offset 0.
284 * Returns 0 if a chip responded, not 0 on failure.
287 int i2c_probe(uchar chip)
292 * Try to read the first location of the chip.
293 * The Tsi108 HW doesn't support sending just the chip address
294 * and checkong for an <ACK> back.
296 return i2c_read(chip, 0, 1, (char *)&tmp, 1);
299 #endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */
300 #endif /* CONFIG_TSI108_I2C */