2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
14 * SPDX-License-Identifier: GPL-2.0
19 #include <dwc3-uboot.h>
20 #include <asm/dma-mapping.h>
21 #include <linux/ioport.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/gadget.h>
30 #include "linux-compat.h"
32 static LIST_HEAD(dwc3_list);
33 /* -------------------------------------------------------------------------- */
35 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
39 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
40 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
41 reg |= DWC3_GCTL_PRTCAPDIR(mode);
42 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
46 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
47 * @dwc: pointer to our context structure
49 static int dwc3_core_soft_reset(struct dwc3 *dwc)
53 /* Before Resetting PHY, put Core in Reset */
54 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
55 reg |= DWC3_GCTL_CORESOFTRESET;
56 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
58 /* Assert USB3 PHY reset */
59 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
60 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
61 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
63 /* Assert USB2 PHY reset */
64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
65 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
66 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
70 /* Clear USB3 PHY reset */
71 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
72 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
73 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
75 /* Clear USB2 PHY reset */
76 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
77 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
78 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
82 /* After PHYs are stable we can take Core out of reset state */
83 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
84 reg &= ~DWC3_GCTL_CORESOFTRESET;
85 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
91 * dwc3_free_one_event_buffer - Frees one event buffer
92 * @dwc: Pointer to our controller context structure
93 * @evt: Pointer to event buffer to be freed
95 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
96 struct dwc3_event_buffer *evt)
98 dma_free_coherent(evt->buf);
102 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
103 * @dwc: Pointer to our controller context structure
104 * @length: size of the event buffer
106 * Returns a pointer to the allocated event buffer structure on success
107 * otherwise ERR_PTR(errno).
109 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
112 struct dwc3_event_buffer *evt;
114 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
116 return ERR_PTR(-ENOMEM);
119 evt->length = length;
120 evt->buf = dma_alloc_coherent(length,
121 (unsigned long *)&evt->dma);
123 return ERR_PTR(-ENOMEM);
125 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
131 * dwc3_free_event_buffers - frees all allocated event buffers
132 * @dwc: Pointer to our controller context structure
134 static void dwc3_free_event_buffers(struct dwc3 *dwc)
136 struct dwc3_event_buffer *evt;
139 for (i = 0; i < dwc->num_event_buffers; i++) {
140 evt = dwc->ev_buffs[i];
142 dwc3_free_one_event_buffer(dwc, evt);
147 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
148 * @dwc: pointer to our controller context structure
149 * @length: size of event buffer
151 * Returns 0 on success otherwise negative errno. In the error case, dwc
152 * may contain some buffers allocated but not all which were requested.
154 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
159 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
160 dwc->num_event_buffers = num;
162 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
163 sizeof(*dwc->ev_buffs) * num);
167 for (i = 0; i < num; i++) {
168 struct dwc3_event_buffer *evt;
170 evt = dwc3_alloc_one_event_buffer(dwc, length);
172 dev_err(dwc->dev, "can't allocate event buffer\n");
175 dwc->ev_buffs[i] = evt;
182 * dwc3_event_buffers_setup - setup our allocated event buffers
183 * @dwc: pointer to our controller context structure
185 * Returns 0 on success otherwise negative errno.
187 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
189 struct dwc3_event_buffer *evt;
192 for (n = 0; n < dwc->num_event_buffers; n++) {
193 evt = dwc->ev_buffs[n];
194 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
195 evt->buf, (unsigned long long) evt->dma,
200 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
201 lower_32_bits(evt->dma));
202 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
203 upper_32_bits(evt->dma));
204 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
205 DWC3_GEVNTSIZ_SIZE(evt->length));
206 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
212 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
214 struct dwc3_event_buffer *evt;
217 for (n = 0; n < dwc->num_event_buffers; n++) {
218 evt = dwc->ev_buffs[n];
222 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
223 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
224 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
225 | DWC3_GEVNTSIZ_SIZE(0));
226 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
230 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
232 if (!dwc->has_hibernation)
235 if (!dwc->nr_scratch)
238 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
239 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
240 if (!dwc->scratchbuf)
246 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
248 dma_addr_t scratch_addr;
252 if (!dwc->has_hibernation)
255 if (!dwc->nr_scratch)
258 scratch_addr = dma_map_single(dwc->scratchbuf,
259 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
261 if (dma_mapping_error(dwc->dev, scratch_addr)) {
262 dev_err(dwc->dev, "failed to map scratch buffer\n");
267 dwc->scratch_addr = scratch_addr;
269 param = lower_32_bits(scratch_addr);
271 ret = dwc3_send_gadget_generic_command(dwc,
272 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
276 param = upper_32_bits(scratch_addr);
278 ret = dwc3_send_gadget_generic_command(dwc,
279 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
286 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
287 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
293 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
295 if (!dwc->has_hibernation)
298 if (!dwc->nr_scratch)
301 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
302 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
303 kfree(dwc->scratchbuf);
306 static void dwc3_core_num_eps(struct dwc3 *dwc)
308 struct dwc3_hwparams *parms = &dwc->hwparams;
310 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
311 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
313 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
314 dwc->num_in_eps, dwc->num_out_eps);
317 static void dwc3_cache_hwparams(struct dwc3 *dwc)
319 struct dwc3_hwparams *parms = &dwc->hwparams;
321 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
322 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
323 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
324 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
325 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
326 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
327 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
328 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
329 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
333 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
334 * @dwc: Pointer to our controller context structure
336 static void dwc3_phy_setup(struct dwc3 *dwc)
340 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
343 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
344 * to '0' during coreConsultant configuration. So default value
345 * will be '0' when the core is reset. Application needs to set it
346 * to '1' after the core initialization is completed.
348 if (dwc->revision > DWC3_REVISION_194A)
349 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
351 if (dwc->u2ss_inp3_quirk)
352 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
354 if (dwc->req_p1p2p3_quirk)
355 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
357 if (dwc->del_p1p2p3_quirk)
358 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
360 if (dwc->del_phy_power_chg_quirk)
361 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
363 if (dwc->lfps_filter_quirk)
364 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
366 if (dwc->rx_detect_poll_quirk)
367 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
369 if (dwc->tx_de_emphasis_quirk)
370 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
372 if (dwc->dis_u3_susphy_quirk)
373 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
375 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
379 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
382 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
383 * '0' during coreConsultant configuration. So default value will
384 * be '0' when the core is reset. Application needs to set it to
385 * '1' after the core initialization is completed.
387 if (dwc->revision > DWC3_REVISION_194A)
388 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
390 if (dwc->dis_u2_susphy_quirk)
391 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
393 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
399 * dwc3_core_init - Low-level initialization of DWC3 Core
400 * @dwc: Pointer to our controller context structure
402 * Returns 0 on success otherwise negative errno.
404 static int dwc3_core_init(struct dwc3 *dwc)
406 unsigned long timeout;
407 u32 hwparams4 = dwc->hwparams.hwparams4;
411 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
412 /* This should read as U3 followed by revision number */
413 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
414 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
420 /* Handle USB2.0-only core configuration */
421 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
422 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
423 if (dwc->maximum_speed == USB_SPEED_SUPER)
424 dwc->maximum_speed = USB_SPEED_HIGH;
427 /* issue device SoftReset too */
429 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
431 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
432 if (!(reg & DWC3_DCTL_CSFTRST))
437 dev_err(dwc->dev, "Reset Timed Out\n");
442 ret = dwc3_core_soft_reset(dwc);
446 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
447 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
449 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
450 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
452 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
453 * issue which would cause xHCI compliance tests to fail.
455 * Because of that we cannot enable clock gating on such
460 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
463 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
464 dwc->dr_mode == USB_DR_MODE_OTG) &&
465 (dwc->revision >= DWC3_REVISION_210A &&
466 dwc->revision <= DWC3_REVISION_250A))
467 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
469 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
471 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
472 /* enable hibernation here */
473 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
476 * REVISIT Enabling this bit so that host-mode hibernation
477 * will work. Device-mode hibernation is not yet implemented.
479 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
482 dev_dbg(dwc->dev, "No power optimization available\n");
485 /* check if current dwc3 is on simulation board */
486 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
487 dev_dbg(dwc->dev, "it is on FPGA board\n");
491 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
493 "disable_scramble cannot be used on non-FPGA builds\n");
495 if (dwc->disable_scramble_quirk && dwc->is_fpga)
496 reg |= DWC3_GCTL_DISSCRAMBLE;
498 reg &= ~DWC3_GCTL_DISSCRAMBLE;
500 if (dwc->u2exit_lfps_quirk)
501 reg |= DWC3_GCTL_U2EXIT_LFPS;
504 * WORKAROUND: DWC3 revisions <1.90a have a bug
505 * where the device can fail to connect at SuperSpeed
506 * and falls back to high-speed mode which causes
507 * the device to enter a Connect/Disconnect loop
509 if (dwc->revision < DWC3_REVISION_190A)
510 reg |= DWC3_GCTL_U2RSTECN;
512 dwc3_core_num_eps(dwc);
514 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
518 ret = dwc3_alloc_scratch_buffers(dwc);
522 ret = dwc3_setup_scratch_buffers(dwc);
529 dwc3_free_scratch_buffers(dwc);
535 static void dwc3_core_exit(struct dwc3 *dwc)
537 dwc3_free_scratch_buffers(dwc);
540 static int dwc3_core_init_mode(struct dwc3 *dwc)
544 switch (dwc->dr_mode) {
545 case USB_DR_MODE_PERIPHERAL:
546 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
547 ret = dwc3_gadget_init(dwc);
549 dev_err(dev, "failed to initialize gadget\n");
553 case USB_DR_MODE_HOST:
554 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
555 ret = dwc3_host_init(dwc);
557 dev_err(dev, "failed to initialize host\n");
561 case USB_DR_MODE_OTG:
562 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
563 ret = dwc3_host_init(dwc);
565 dev_err(dev, "failed to initialize host\n");
569 ret = dwc3_gadget_init(dwc);
571 dev_err(dev, "failed to initialize gadget\n");
576 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
583 static void dwc3_core_exit_mode(struct dwc3 *dwc)
585 switch (dwc->dr_mode) {
586 case USB_DR_MODE_PERIPHERAL:
587 dwc3_gadget_exit(dwc);
589 case USB_DR_MODE_HOST:
592 case USB_DR_MODE_OTG:
594 dwc3_gadget_exit(dwc);
602 #define DWC3_ALIGN_MASK (16 - 1)
605 * dwc3_uboot_init - dwc3 core uboot initialization code
606 * @dwc3_dev: struct dwc3_device containing initialization data
608 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
609 * kernel driver). Pointer to dwc3_device should be passed containing
610 * base address and other initialization data. Returns '0' on success and
611 * a negative value on failure.
613 * Generally called from board_usb_init() implemented in board file.
615 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
618 struct device *dev = NULL;
619 u8 lpm_nyet_threshold;
627 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
631 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
634 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
635 DWC3_GLOBALS_REGS_START);
637 /* default to highest possible threshold */
638 lpm_nyet_threshold = 0xff;
640 /* default to -3.5dB de-emphasis */
644 * default to assert utmi_sleep_n and use maximum allowed HIRD
645 * threshold value of 0b1100
649 dwc->maximum_speed = dwc3_dev->maximum_speed;
650 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
651 if (dwc3_dev->lpm_nyet_threshold)
652 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
653 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
654 if (dwc3_dev->hird_threshold)
655 hird_threshold = dwc3_dev->hird_threshold;
657 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
658 dwc->dr_mode = dwc3_dev->dr_mode;
660 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
661 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
662 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
663 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
664 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
665 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
666 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
667 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
668 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
669 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
671 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
672 if (dwc3_dev->tx_de_emphasis)
673 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
675 /* default to superspeed if no maximum_speed passed */
676 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
677 dwc->maximum_speed = USB_SPEED_SUPER;
679 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
680 dwc->tx_de_emphasis = tx_de_emphasis;
682 dwc->hird_threshold = hird_threshold
683 | (dwc->is_utmi_l1_suspend << 4);
685 dwc->index = dwc3_dev->index;
687 dwc3_cache_hwparams(dwc);
689 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
691 dev_err(dwc->dev, "failed to allocate event buffers\n");
695 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
696 dwc->dr_mode = USB_DR_MODE_HOST;
697 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
698 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
700 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
701 dwc->dr_mode = USB_DR_MODE_OTG;
703 ret = dwc3_core_init(dwc);
705 dev_err(dev, "failed to initialize core\n");
709 ret = dwc3_event_buffers_setup(dwc);
711 dev_err(dwc->dev, "failed to setup event buffers\n");
715 ret = dwc3_core_init_mode(dwc);
719 list_add_tail(&dwc->list, &dwc3_list);
724 dwc3_event_buffers_cleanup(dwc);
730 dwc3_free_event_buffers(dwc);
736 * dwc3_uboot_exit - dwc3 core uboot cleanup code
737 * @index: index of this controller
739 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
740 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
741 * should be passed and should match with the index passed in
742 * dwc3_device during init.
744 * Generally called from board file.
746 void dwc3_uboot_exit(int index)
750 list_for_each_entry(dwc, &dwc3_list, list) {
751 if (dwc->index != index)
754 dwc3_core_exit_mode(dwc);
755 dwc3_event_buffers_cleanup(dwc);
756 dwc3_free_event_buffers(dwc);
758 list_del(&dwc->list);
765 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
766 * @index: index of this controller
768 * Invokes dwc3 gadget interrupts.
770 * Generally called from board file.
772 void dwc3_uboot_handle_interrupt(int index)
774 struct dwc3 *dwc = NULL;
776 list_for_each_entry(dwc, &dwc3_list, list) {
777 if (dwc->index != index)
780 dwc3_gadget_uboot_handle_interrupt(dwc);
785 MODULE_ALIAS("platform:dwc3");
786 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
787 MODULE_LICENSE("GPL v2");
788 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");