2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
14 * SPDX-License-Identifier: GPL-2.0
19 #include <dwc3-uboot.h>
20 #include <asm/dma-mapping.h>
21 #include <linux/ioport.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/gadget.h>
30 #include "linux-compat.h"
32 static LIST_HEAD(dwc3_list);
33 /* -------------------------------------------------------------------------- */
35 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
39 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
40 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
41 reg |= DWC3_GCTL_PRTCAPDIR(mode);
42 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
46 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
47 * @dwc: pointer to our context structure
49 static int dwc3_core_soft_reset(struct dwc3 *dwc)
53 /* Before Resetting PHY, put Core in Reset */
54 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
55 reg |= DWC3_GCTL_CORESOFTRESET;
56 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
58 /* Assert USB3 PHY reset */
59 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
60 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
61 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
63 /* Assert USB2 PHY reset */
64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
65 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
66 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
70 /* Clear USB3 PHY reset */
71 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
72 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
73 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
75 /* Clear USB2 PHY reset */
76 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
77 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
78 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
82 /* After PHYs are stable we can take Core out of reset state */
83 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
84 reg &= ~DWC3_GCTL_CORESOFTRESET;
85 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
91 * dwc3_free_one_event_buffer - Frees one event buffer
92 * @dwc: Pointer to our controller context structure
93 * @evt: Pointer to event buffer to be freed
95 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
96 struct dwc3_event_buffer *evt)
98 dma_free_coherent(evt->buf);
102 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
103 * @dwc: Pointer to our controller context structure
104 * @length: size of the event buffer
106 * Returns a pointer to the allocated event buffer structure on success
107 * otherwise ERR_PTR(errno).
109 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
112 struct dwc3_event_buffer *evt;
114 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
116 return ERR_PTR(-ENOMEM);
119 evt->length = length;
120 evt->buf = dma_alloc_coherent(length,
121 (unsigned long *)&evt->dma);
123 return ERR_PTR(-ENOMEM);
129 * dwc3_free_event_buffers - frees all allocated event buffers
130 * @dwc: Pointer to our controller context structure
132 static void dwc3_free_event_buffers(struct dwc3 *dwc)
134 struct dwc3_event_buffer *evt;
137 for (i = 0; i < dwc->num_event_buffers; i++) {
138 evt = dwc->ev_buffs[i];
140 dwc3_free_one_event_buffer(dwc, evt);
145 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
146 * @dwc: pointer to our controller context structure
147 * @length: size of event buffer
149 * Returns 0 on success otherwise negative errno. In the error case, dwc
150 * may contain some buffers allocated but not all which were requested.
152 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
157 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
158 dwc->num_event_buffers = num;
160 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
161 sizeof(*dwc->ev_buffs) * num);
165 for (i = 0; i < num; i++) {
166 struct dwc3_event_buffer *evt;
168 evt = dwc3_alloc_one_event_buffer(dwc, length);
170 dev_err(dwc->dev, "can't allocate event buffer\n");
173 dwc->ev_buffs[i] = evt;
180 * dwc3_event_buffers_setup - setup our allocated event buffers
181 * @dwc: pointer to our controller context structure
183 * Returns 0 on success otherwise negative errno.
185 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
187 struct dwc3_event_buffer *evt;
190 for (n = 0; n < dwc->num_event_buffers; n++) {
191 evt = dwc->ev_buffs[n];
192 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
193 evt->buf, (unsigned long long) evt->dma,
198 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
199 lower_32_bits(evt->dma));
200 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
201 upper_32_bits(evt->dma));
202 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
203 DWC3_GEVNTSIZ_SIZE(evt->length));
204 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
210 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
212 struct dwc3_event_buffer *evt;
215 for (n = 0; n < dwc->num_event_buffers; n++) {
216 evt = dwc->ev_buffs[n];
220 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
221 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
222 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
223 | DWC3_GEVNTSIZ_SIZE(0));
224 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
228 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
230 if (!dwc->has_hibernation)
233 if (!dwc->nr_scratch)
236 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
237 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
238 if (!dwc->scratchbuf)
244 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
246 dma_addr_t scratch_addr;
250 if (!dwc->has_hibernation)
253 if (!dwc->nr_scratch)
256 scratch_addr = dma_map_single(dwc->scratchbuf,
257 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
259 if (dma_mapping_error(dwc->dev, scratch_addr)) {
260 dev_err(dwc->dev, "failed to map scratch buffer\n");
265 dwc->scratch_addr = scratch_addr;
267 param = lower_32_bits(scratch_addr);
269 ret = dwc3_send_gadget_generic_command(dwc,
270 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
274 param = upper_32_bits(scratch_addr);
276 ret = dwc3_send_gadget_generic_command(dwc,
277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
284 dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch *
285 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
291 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
293 if (!dwc->has_hibernation)
296 if (!dwc->nr_scratch)
299 dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch *
300 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
301 kfree(dwc->scratchbuf);
304 static void dwc3_core_num_eps(struct dwc3 *dwc)
306 struct dwc3_hwparams *parms = &dwc->hwparams;
308 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
309 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
311 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
312 dwc->num_in_eps, dwc->num_out_eps);
315 static void dwc3_cache_hwparams(struct dwc3 *dwc)
317 struct dwc3_hwparams *parms = &dwc->hwparams;
319 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
320 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
321 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
322 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
323 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
324 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
325 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
326 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
327 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
331 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
332 * @dwc: Pointer to our controller context structure
334 static void dwc3_phy_setup(struct dwc3 *dwc)
338 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
341 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
342 * to '0' during coreConsultant configuration. So default value
343 * will be '0' when the core is reset. Application needs to set it
344 * to '1' after the core initialization is completed.
346 if (dwc->revision > DWC3_REVISION_194A)
347 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
349 if (dwc->u2ss_inp3_quirk)
350 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
352 if (dwc->req_p1p2p3_quirk)
353 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
355 if (dwc->del_p1p2p3_quirk)
356 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
358 if (dwc->del_phy_power_chg_quirk)
359 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
361 if (dwc->lfps_filter_quirk)
362 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
364 if (dwc->rx_detect_poll_quirk)
365 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
367 if (dwc->tx_de_emphasis_quirk)
368 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
370 if (dwc->dis_u3_susphy_quirk)
371 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
373 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
377 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
380 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
381 * '0' during coreConsultant configuration. So default value will
382 * be '0' when the core is reset. Application needs to set it to
383 * '1' after the core initialization is completed.
385 if (dwc->revision > DWC3_REVISION_194A)
386 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
388 if (dwc->dis_u2_susphy_quirk)
389 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
391 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
397 * dwc3_core_init - Low-level initialization of DWC3 Core
398 * @dwc: Pointer to our controller context structure
400 * Returns 0 on success otherwise negative errno.
402 static int dwc3_core_init(struct dwc3 *dwc)
404 unsigned long timeout;
405 u32 hwparams4 = dwc->hwparams.hwparams4;
409 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
410 /* This should read as U3 followed by revision number */
411 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
412 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
418 /* Handle USB2.0-only core configuration */
419 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
420 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
421 if (dwc->maximum_speed == USB_SPEED_SUPER)
422 dwc->maximum_speed = USB_SPEED_HIGH;
425 /* issue device SoftReset too */
427 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
429 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
430 if (!(reg & DWC3_DCTL_CSFTRST))
435 dev_err(dwc->dev, "Reset Timed Out\n");
440 ret = dwc3_core_soft_reset(dwc);
444 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
445 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
447 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
448 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
450 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
451 * issue which would cause xHCI compliance tests to fail.
453 * Because of that we cannot enable clock gating on such
458 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
461 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
462 dwc->dr_mode == USB_DR_MODE_OTG) &&
463 (dwc->revision >= DWC3_REVISION_210A &&
464 dwc->revision <= DWC3_REVISION_250A))
465 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
467 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
469 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
470 /* enable hibernation here */
471 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
474 * REVISIT Enabling this bit so that host-mode hibernation
475 * will work. Device-mode hibernation is not yet implemented.
477 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
480 dev_dbg(dwc->dev, "No power optimization available\n");
483 /* check if current dwc3 is on simulation board */
484 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
485 dev_dbg(dwc->dev, "it is on FPGA board\n");
489 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
491 "disable_scramble cannot be used on non-FPGA builds\n");
493 if (dwc->disable_scramble_quirk && dwc->is_fpga)
494 reg |= DWC3_GCTL_DISSCRAMBLE;
496 reg &= ~DWC3_GCTL_DISSCRAMBLE;
498 if (dwc->u2exit_lfps_quirk)
499 reg |= DWC3_GCTL_U2EXIT_LFPS;
502 * WORKAROUND: DWC3 revisions <1.90a have a bug
503 * where the device can fail to connect at SuperSpeed
504 * and falls back to high-speed mode which causes
505 * the device to enter a Connect/Disconnect loop
507 if (dwc->revision < DWC3_REVISION_190A)
508 reg |= DWC3_GCTL_U2RSTECN;
510 dwc3_core_num_eps(dwc);
512 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
516 ret = dwc3_alloc_scratch_buffers(dwc);
520 ret = dwc3_setup_scratch_buffers(dwc);
527 dwc3_free_scratch_buffers(dwc);
533 static void dwc3_core_exit(struct dwc3 *dwc)
535 dwc3_free_scratch_buffers(dwc);
538 static int dwc3_core_init_mode(struct dwc3 *dwc)
542 switch (dwc->dr_mode) {
543 case USB_DR_MODE_PERIPHERAL:
544 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
545 ret = dwc3_gadget_init(dwc);
547 dev_err(dev, "failed to initialize gadget\n");
551 case USB_DR_MODE_HOST:
552 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
553 ret = dwc3_host_init(dwc);
555 dev_err(dev, "failed to initialize host\n");
559 case USB_DR_MODE_OTG:
560 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
561 ret = dwc3_host_init(dwc);
563 dev_err(dev, "failed to initialize host\n");
567 ret = dwc3_gadget_init(dwc);
569 dev_err(dev, "failed to initialize gadget\n");
574 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
581 static void dwc3_core_exit_mode(struct dwc3 *dwc)
583 switch (dwc->dr_mode) {
584 case USB_DR_MODE_PERIPHERAL:
585 dwc3_gadget_exit(dwc);
587 case USB_DR_MODE_HOST:
590 case USB_DR_MODE_OTG:
592 dwc3_gadget_exit(dwc);
600 #define DWC3_ALIGN_MASK (16 - 1)
603 * dwc3_uboot_init - dwc3 core uboot initialization code
604 * @dwc3_dev: struct dwc3_device containing initialization data
606 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
607 * kernel driver). Pointer to dwc3_device should be passed containing
608 * base address and other initialization data. Returns '0' on success and
609 * a negative value on failure.
611 * Generally called from board_usb_init() implemented in board file.
613 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
617 u8 lpm_nyet_threshold;
625 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
629 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
632 dwc->regs = (int *)(dwc3_dev->base + DWC3_GLOBALS_REGS_START);
634 /* default to highest possible threshold */
635 lpm_nyet_threshold = 0xff;
637 /* default to -3.5dB de-emphasis */
641 * default to assert utmi_sleep_n and use maximum allowed HIRD
642 * threshold value of 0b1100
646 dwc->maximum_speed = dwc3_dev->maximum_speed;
647 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
648 if (dwc3_dev->lpm_nyet_threshold)
649 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
650 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
651 if (dwc3_dev->hird_threshold)
652 hird_threshold = dwc3_dev->hird_threshold;
654 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
655 dwc->dr_mode = dwc3_dev->dr_mode;
657 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
658 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
659 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
660 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
661 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
662 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
663 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
664 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
665 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
666 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
668 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
669 if (dwc3_dev->tx_de_emphasis)
670 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
672 /* default to superspeed if no maximum_speed passed */
673 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
674 dwc->maximum_speed = USB_SPEED_SUPER;
676 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
677 dwc->tx_de_emphasis = tx_de_emphasis;
679 dwc->hird_threshold = hird_threshold
680 | (dwc->is_utmi_l1_suspend << 4);
682 dwc->index = dwc3_dev->index;
684 dwc3_cache_hwparams(dwc);
686 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
688 dev_err(dwc->dev, "failed to allocate event buffers\n");
692 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
693 dwc->dr_mode = USB_DR_MODE_HOST;
694 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
695 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
697 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
698 dwc->dr_mode = USB_DR_MODE_OTG;
700 ret = dwc3_core_init(dwc);
702 dev_err(dev, "failed to initialize core\n");
706 ret = dwc3_event_buffers_setup(dwc);
708 dev_err(dwc->dev, "failed to setup event buffers\n");
712 ret = dwc3_core_init_mode(dwc);
716 list_add_tail(&dwc->list, &dwc3_list);
721 dwc3_event_buffers_cleanup(dwc);
727 dwc3_free_event_buffers(dwc);
733 * dwc3_uboot_exit - dwc3 core uboot cleanup code
734 * @index: index of this controller
736 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
737 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
738 * should be passed and should match with the index passed in
739 * dwc3_device during init.
741 * Generally called from board file.
743 void dwc3_uboot_exit(int index)
747 list_for_each_entry(dwc, &dwc3_list, list) {
748 if (dwc->index != index)
751 dwc3_core_exit_mode(dwc);
752 dwc3_event_buffers_cleanup(dwc);
753 dwc3_free_event_buffers(dwc);
755 list_del(&dwc->list);
762 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
763 * @index: index of this controller
765 * Invokes dwc3 gadget interrupts.
767 * Generally called from board file.
769 void dwc3_uboot_handle_interrupt(int index)
771 struct dwc3 *dwc = NULL;
773 list_for_each_entry(dwc, &dwc3_list, list) {
774 if (dwc->index != index)
777 dwc3_gadget_uboot_handle_interrupt(dwc);
782 MODULE_ALIAS("platform:dwc3");
783 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
784 MODULE_LICENSE("GPL v2");
785 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");