2 * dwc3-omap.c - OMAP Specific Glue layer
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported
12 * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete()
14 * SPDX-License-Identifier: GPL-2.0
20 #include <dwc3-omap-uboot.h>
21 #include <linux/usb/dwc3-omap.h>
22 #include <linux/ioport.h>
24 #include <linux/usb/otg.h>
25 #include <linux/compat.h>
27 #include "linux-compat.h"
30 * All these registers belong to OMAP's Wrapper around the
31 * DesignWare USB3 Core.
34 #define USBOTGSS_REVISION 0x0000
35 #define USBOTGSS_SYSCONFIG 0x0010
36 #define USBOTGSS_IRQ_EOI 0x0020
37 #define USBOTGSS_EOI_OFFSET 0x0008
38 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
39 #define USBOTGSS_IRQSTATUS_0 0x0028
40 #define USBOTGSS_IRQENABLE_SET_0 0x002c
41 #define USBOTGSS_IRQENABLE_CLR_0 0x0030
42 #define USBOTGSS_IRQ0_OFFSET 0x0004
43 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030
44 #define USBOTGSS_IRQSTATUS_1 0x0034
45 #define USBOTGSS_IRQENABLE_SET_1 0x0038
46 #define USBOTGSS_IRQENABLE_CLR_1 0x003c
47 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040
48 #define USBOTGSS_IRQSTATUS_2 0x0044
49 #define USBOTGSS_IRQENABLE_SET_2 0x0048
50 #define USBOTGSS_IRQENABLE_CLR_2 0x004c
51 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050
52 #define USBOTGSS_IRQSTATUS_3 0x0054
53 #define USBOTGSS_IRQENABLE_SET_3 0x0058
54 #define USBOTGSS_IRQENABLE_CLR_3 0x005c
55 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
56 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
57 #define USBOTGSS_IRQSTATUS_MISC 0x0038
58 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c
59 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
60 #define USBOTGSS_IRQMISC_OFFSET 0x03fc
61 #define USBOTGSS_UTMI_OTG_CTRL 0x0080
62 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
63 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
64 #define USBOTGSS_TXFIFO_DEPTH 0x0508
65 #define USBOTGSS_RXFIFO_DEPTH 0x050c
66 #define USBOTGSS_MMRAM_OFFSET 0x0100
67 #define USBOTGSS_FLADJ 0x0104
68 #define USBOTGSS_DEBUG_CFG 0x0108
69 #define USBOTGSS_DEBUG_DATA 0x010c
70 #define USBOTGSS_DEV_EBC_EN 0x0110
71 #define USBOTGSS_DEBUG_OFFSET 0x0600
73 /* SYSCONFIG REGISTER */
74 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
76 /* IRQ_EOI REGISTER */
77 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
80 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
83 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
84 #define USBOTGSS_IRQMISC_OEVT (1 << 16)
85 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
86 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
87 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
88 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
89 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
90 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
91 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
92 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
94 /* UTMI_OTG_CTRL REGISTER */
95 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
96 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
97 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
98 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
100 /* UTMI_OTG_STATUS REGISTER */
101 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
102 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
103 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
104 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
105 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
106 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
107 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
122 struct list_head list;
126 static LIST_HEAD(dwc3_omap_list);
128 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
130 return readl(base + offset);
133 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
135 writel(value, base + offset);
138 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
140 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
141 omap->utmi_otg_offset);
144 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
146 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
147 omap->utmi_otg_offset, value);
151 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
153 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
157 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
159 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
160 omap->irq0_offset, value);
164 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
166 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
167 omap->irqmisc_offset);
170 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
172 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
173 omap->irqmisc_offset, value);
177 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
179 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
180 omap->irqmisc_offset, value);
184 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
186 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
187 omap->irq0_offset, value);
190 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
191 enum omap_dwc3_vbus_id_status status)
196 case OMAP_DWC3_ID_GROUND:
197 dev_dbg(omap->dev, "ID GND\n");
199 val = dwc3_omap_read_utmi_status(omap);
200 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
201 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
202 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
203 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
204 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
205 dwc3_omap_write_utmi_status(omap, val);
208 case OMAP_DWC3_VBUS_VALID:
209 dev_dbg(omap->dev, "VBUS Connect\n");
211 val = dwc3_omap_read_utmi_status(omap);
212 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
213 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
214 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
215 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
216 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
217 dwc3_omap_write_utmi_status(omap, val);
220 case OMAP_DWC3_ID_FLOAT:
221 case OMAP_DWC3_VBUS_OFF:
222 dev_dbg(omap->dev, "VBUS Disconnect\n");
224 val = dwc3_omap_read_utmi_status(omap);
225 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
226 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
227 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
228 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
229 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
230 dwc3_omap_write_utmi_status(omap, val);
234 dev_dbg(omap->dev, "invalid state\n");
238 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
240 struct dwc3_omap *omap = _omap;
243 reg = dwc3_omap_read_irqmisc_status(omap);
245 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
246 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
247 omap->dma_status = false;
250 if (reg & USBOTGSS_IRQMISC_OEVT)
251 dev_dbg(omap->dev, "OTG Event\n");
253 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
254 dev_dbg(omap->dev, "DRVVBUS Rise\n");
256 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
257 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
259 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
260 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
262 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
263 dev_dbg(omap->dev, "IDPULLUP Rise\n");
265 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
266 dev_dbg(omap->dev, "DRVVBUS Fall\n");
268 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
269 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
271 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
272 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
274 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
275 dev_dbg(omap->dev, "IDPULLUP Fall\n");
277 dwc3_omap_write_irqmisc_status(omap, reg);
279 reg = dwc3_omap_read_irq0_status(omap);
281 dwc3_omap_write_irq0_status(omap, reg);
286 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
290 /* enable all IRQs */
291 reg = USBOTGSS_IRQO_COREIRQ_ST;
292 dwc3_omap_write_irq0_set(omap, reg);
294 reg = (USBOTGSS_IRQMISC_OEVT |
295 USBOTGSS_IRQMISC_DRVVBUS_RISE |
296 USBOTGSS_IRQMISC_CHRGVBUS_RISE |
297 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
298 USBOTGSS_IRQMISC_IDPULLUP_RISE |
299 USBOTGSS_IRQMISC_DRVVBUS_FALL |
300 USBOTGSS_IRQMISC_CHRGVBUS_FALL |
301 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
302 USBOTGSS_IRQMISC_IDPULLUP_FALL);
304 dwc3_omap_write_irqmisc_set(omap, reg);
307 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
309 /* disable all IRQs */
310 dwc3_omap_write_irqmisc_set(omap, 0x00);
311 dwc3_omap_write_irq0_set(omap, 0x00);
314 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
317 * Differentiate between OMAP5 and AM437x.
319 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
320 * though there are changes in wrapper register offsets.
322 * Using dt compatible to differentiate AM437x.
325 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
326 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
327 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
328 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
329 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
333 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode)
337 reg = dwc3_omap_read_utmi_status(omap);
340 case DWC3_OMAP_UTMI_MODE_SW:
341 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
343 case DWC3_OMAP_UTMI_MODE_HW:
344 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
347 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
350 dwc3_omap_write_utmi_status(omap, reg);
354 * dwc3_omap_uboot_init - dwc3 omap uboot initialization code
355 * @dev: struct dwc3_omap_device containing initialization data
357 * Entry point for dwc3 omap driver (equivalent to dwc3_omap_probe in linux
358 * kernel driver). Pointer to dwc3_omap_device should be passed containing
359 * base address and other initialization data. Returns '0' on success and
360 * a negative value on failure.
362 * Generally called from board_usb_init() implemented in board file.
364 int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev)
368 struct dwc3_omap *omap;
370 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
374 omap->base = omap_dev->base;
375 omap->index = omap_dev->index;
377 dwc3_omap_map_offset(omap);
378 dwc3_omap_set_utmi_mode(omap, omap_dev->utmi_mode);
380 /* check the DMA Status */
381 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
382 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
384 dwc3_omap_set_mailbox(omap, omap_dev->vbus_id_status);
386 dwc3_omap_enable_irqs(omap);
387 list_add_tail(&omap->list, &dwc3_omap_list);
393 * dwc3_omap_uboot_exit - dwc3 omap uboot cleanup code
394 * @index: index of this controller
396 * Performs cleanup of memory allocated in dwc3_omap_uboot_init
397 * (equivalent to dwc3_omap_remove in linux). index of _this_ controller
398 * should be passed and should match with the index passed in
399 * dwc3_omap_device during init.
401 * Generally called from board file.
403 void dwc3_omap_uboot_exit(int index)
405 struct dwc3_omap *omap = NULL;
407 list_for_each_entry(omap, &dwc3_omap_list, list) {
408 if (omap->index != index)
411 dwc3_omap_disable_irqs(omap);
412 list_del(&omap->list);
419 * dwc3_omap_uboot_interrupt_status - check the status of interrupt
420 * @index: index of this controller
422 * Checks the status of interrupts and returns true if an interrupt
423 * is detected or false otherwise.
425 * Generally called from board file.
427 int dwc3_omap_uboot_interrupt_status(int index)
429 struct dwc3_omap *omap = NULL;
431 list_for_each_entry(omap, &dwc3_omap_list, list)
432 if (omap->index == index)
433 return dwc3_omap_interrupt(-1, omap);
438 MODULE_ALIAS("platform:omap-dwc3");
439 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
440 MODULE_LICENSE("GPL v2");
441 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");