2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
12 * commit c00552ebaf : Merge 3.18-rc7 into usb-next
14 * SPDX-License-Identifier: GPL-2.0
17 #include <linux/kernel.h>
18 #include <linux/list.h>
20 #include <linux/usb/ch9.h>
21 #include <linux/usb/gadget.h>
22 #include <linux/usb/composite.h>
28 #include "linux-compat.h"
30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
34 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
43 case EP0_STATUS_PHASE:
44 return "Status Phase";
50 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
53 struct dwc3_gadget_ep_cmd_params params;
59 dep = dwc->eps[epnum];
60 if (dep->flags & DWC3_EP_BUSY) {
61 dev_vdbg(dwc->dev, "%s still busy", dep->name);
67 trb->bpl = lower_32_bits(buf_dma);
68 trb->bph = upper_32_bits(buf_dma);
72 trb->ctrl |= (DWC3_TRB_CTRL_HWO
75 | DWC3_TRB_CTRL_ISP_IMI);
77 memset(¶ms, 0, sizeof(params));
78 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
79 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
81 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
82 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
84 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
88 dep->flags |= DWC3_EP_BUSY;
89 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
92 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
97 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
98 struct dwc3_request *req)
100 struct dwc3 *dwc = dep->dwc;
102 req->request.actual = 0;
103 req->request.status = -EINPROGRESS;
104 req->epnum = dep->number;
106 list_add_tail(&req->list, &dep->request_list);
109 * Gadget driver might not be quick enough to queue a request
110 * before we get a Transfer Not Ready event on this endpoint.
112 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
113 * flag is set, it's telling us that as soon as Gadget queues the
114 * required request, we should kick the transfer here because the
115 * IRQ we were waiting for is long gone.
117 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
120 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
122 if (dwc->ep0state != EP0_DATA_PHASE) {
123 dev_WARN(dwc->dev, "Unexpected pending request\n");
127 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
129 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
136 * In case gadget driver asked us to delay the STATUS phase,
139 if (dwc->delayed_status) {
142 direction = !dwc->ep0_expect_in;
143 dwc->delayed_status = false;
144 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
146 if (dwc->ep0state == EP0_STATUS_PHASE)
147 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
149 dev_dbg(dwc->dev, "too early for delayed status");
155 * Unfortunately we have uncovered a limitation wrt the Data Phase.
157 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
158 * come before issueing Start Transfer command, but if we do, we will
159 * miss situations where the host starts another SETUP phase instead of
160 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
161 * Layer Compliance Suite.
163 * The problem surfaces due to the fact that in case of back-to-back
164 * SETUP packets there will be no XferNotReady(DATA) generated and we
165 * will be stuck waiting for XferNotReady(DATA) forever.
167 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
168 * it tells us to start Data Phase right away. It also mentions that if
169 * we receive a SETUP phase instead of the DATA phase, core will issue
170 * XferComplete for the DATA phase, before actually initiating it in
171 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
172 * can only be used to print some debugging logs, as the core expects
173 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
174 * just so it completes right away, without transferring anything and,
175 * only then, we can go back to the SETUP phase.
177 * Because of this scenario, SNPS decided to change the programming
178 * model of control transfers and support on-demand transfers only for
179 * the STATUS phase. To fix the issue we have now, we will always wait
180 * for gadget driver to queue the DATA phase's struct usb_request, then
181 * start it right away.
183 * If we're actually in a 2-stage transfer, we will wait for
184 * XferNotReady(STATUS).
186 if (dwc->three_stage_setup) {
189 direction = dwc->ep0_expect_in;
190 dwc->ep0state = EP0_DATA_PHASE;
192 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
194 dep->flags &= ~DWC3_EP0_DIR_IN;
200 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
203 struct dwc3_request *req = to_dwc3_request(request);
204 struct dwc3_ep *dep = to_dwc3_ep(ep);
205 struct dwc3 *dwc = dep->dwc;
211 spin_lock_irqsave(&dwc->lock, flags);
212 if (!dep->endpoint.desc) {
213 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
219 /* we share one TRB for ep0/1 */
220 if (!list_empty(&dep->request_list)) {
225 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
226 request, dep->name, request->length,
227 dwc3_ep0_state_string(dwc->ep0state));
229 ret = __dwc3_gadget_ep0_queue(dep, req);
232 spin_unlock_irqrestore(&dwc->lock, flags);
237 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
241 /* reinitialize physical ep1 */
243 dep->flags = DWC3_EP_ENABLED;
245 /* stall is always issued on EP0 */
247 __dwc3_gadget_ep_set_halt(dep, 1, false);
248 dep->flags = DWC3_EP_ENABLED;
249 dwc->delayed_status = false;
251 if (!list_empty(&dep->request_list)) {
252 struct dwc3_request *req;
254 req = next_request(&dep->request_list);
255 dwc3_gadget_giveback(dep, req, -ECONNRESET);
258 dwc->ep0state = EP0_SETUP_PHASE;
259 dwc3_ep0_out_start(dwc);
262 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
264 struct dwc3_ep *dep = to_dwc3_ep(ep);
265 struct dwc3 *dwc = dep->dwc;
267 dwc3_ep0_stall_and_restart(dwc);
272 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
277 spin_lock_irqsave(&dwc->lock, flags);
278 ret = __dwc3_gadget_ep0_set_halt(ep, value);
279 spin_unlock_irqrestore(&dwc->lock, flags);
284 void dwc3_ep0_out_start(struct dwc3 *dwc)
288 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
289 DWC3_TRBCTL_CONTROL_SETUP);
293 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
296 u32 windex = le16_to_cpu(wIndex_le);
299 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
300 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
303 dep = dwc->eps[epnum];
304 if (dep->flags & DWC3_EP_ENABLED)
310 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
316 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
317 struct usb_ctrlrequest *ctrl)
323 __le16 *response_pkt;
325 recip = ctrl->bRequestType & USB_RECIP_MASK;
327 case USB_RECIP_DEVICE:
329 * LTM will be set once we know how to set this in HW.
331 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
333 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
334 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
335 if (reg & DWC3_DCTL_INITU1ENA)
336 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
337 if (reg & DWC3_DCTL_INITU2ENA)
338 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
343 case USB_RECIP_INTERFACE:
345 * Function Remote Wake Capable D0
346 * Function Remote Wakeup D1
350 case USB_RECIP_ENDPOINT:
351 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
355 if (dep->flags & DWC3_EP_STALL)
356 usb_status = 1 << USB_ENDPOINT_HALT;
362 response_pkt = (__le16 *) dwc->setup_buf;
363 *response_pkt = cpu_to_le16(usb_status);
366 dwc->ep0_usb_req.dep = dep;
367 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
368 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
369 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
371 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
374 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
375 struct usb_ctrlrequest *ctrl, int set)
383 enum usb_device_state state;
385 wValue = le16_to_cpu(ctrl->wValue);
386 wIndex = le16_to_cpu(ctrl->wIndex);
387 recip = ctrl->bRequestType & USB_RECIP_MASK;
388 state = dwc->gadget.state;
391 case USB_RECIP_DEVICE:
394 case USB_DEVICE_REMOTE_WAKEUP:
397 * 9.4.1 says only only for SS, in AddressState only for
398 * default control pipe
400 case USB_DEVICE_U1_ENABLE:
401 if (state != USB_STATE_CONFIGURED)
403 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
406 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
408 reg |= DWC3_DCTL_INITU1ENA;
410 reg &= ~DWC3_DCTL_INITU1ENA;
411 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
414 case USB_DEVICE_U2_ENABLE:
415 if (state != USB_STATE_CONFIGURED)
417 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
420 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
422 reg |= DWC3_DCTL_INITU2ENA;
424 reg &= ~DWC3_DCTL_INITU2ENA;
425 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
428 case USB_DEVICE_LTM_ENABLE:
431 case USB_DEVICE_TEST_MODE:
432 if ((wIndex & 0xff) != 0)
437 dwc->test_mode_nr = wIndex >> 8;
438 dwc->test_mode = true;
445 case USB_RECIP_INTERFACE:
447 case USB_INTRF_FUNC_SUSPEND:
448 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
449 /* XXX enable Low power suspend */
451 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
452 /* XXX enable remote wakeup */
460 case USB_RECIP_ENDPOINT:
462 case USB_ENDPOINT_HALT:
463 dep = dwc3_wIndex_to_dep(dwc, wIndex);
466 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
468 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
484 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
486 enum usb_device_state state = dwc->gadget.state;
490 addr = le16_to_cpu(ctrl->wValue);
492 dev_dbg(dwc->dev, "invalid device address %d", addr);
496 if (state == USB_STATE_CONFIGURED) {
497 dev_dbg(dwc->dev, "trying to set address when configured");
501 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
502 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
503 reg |= DWC3_DCFG_DEVADDR(addr);
504 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
507 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
509 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
514 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
518 spin_unlock(&dwc->lock);
519 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
520 spin_lock(&dwc->lock);
524 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
526 enum usb_device_state state = dwc->gadget.state;
531 dwc->start_config_issued = false;
532 cfg = le16_to_cpu(ctrl->wValue);
535 case USB_STATE_DEFAULT:
538 case USB_STATE_ADDRESS:
539 ret = dwc3_ep0_delegate_req(dwc, ctrl);
540 /* if the cfg matches and the cfg is non zero */
541 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
544 * only change state if set_config has already
545 * been processed. If gadget driver returns
546 * USB_GADGET_DELAYED_STATUS, we will wait
547 * to change the state on the next usb_ep_queue()
550 usb_gadget_set_state(&dwc->gadget,
551 USB_STATE_CONFIGURED);
554 * Enable transition to U1/U2 state when
555 * nothing is pending from application.
557 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
558 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
559 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
561 dwc->resize_fifos = true;
562 dev_dbg(dwc->dev, "resize FIFOs flag SET");
566 case USB_STATE_CONFIGURED:
567 ret = dwc3_ep0_delegate_req(dwc, ctrl);
569 usb_gadget_set_state(&dwc->gadget,
578 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
580 struct dwc3_ep *dep = to_dwc3_ep(ep);
581 struct dwc3 *dwc = dep->dwc;
595 memcpy(&timing, req->buf, sizeof(timing));
597 dwc->u1sel = timing.u1sel;
598 dwc->u1pel = timing.u1pel;
599 dwc->u2sel = le16_to_cpu(timing.u2sel);
600 dwc->u2pel = le16_to_cpu(timing.u2pel);
602 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
603 if (reg & DWC3_DCTL_INITU2ENA)
605 if (reg & DWC3_DCTL_INITU1ENA)
609 * According to Synopsys Databook, if parameter is
610 * greater than 125, a value of zero should be
611 * programmed in the register.
616 /* now that we have the time, issue DGCMD Set Sel */
617 ret = dwc3_send_gadget_generic_command(dwc,
618 DWC3_DGCMD_SET_PERIODIC_PAR, param);
622 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
625 enum usb_device_state state = dwc->gadget.state;
628 if (state == USB_STATE_DEFAULT)
631 wLength = le16_to_cpu(ctrl->wLength);
634 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
640 * To handle Set SEL we need to receive 6 bytes from Host. So let's
641 * queue a usb_request for 6 bytes.
643 * Remember, though, this controller can't handle non-wMaxPacketSize
644 * aligned transfers on the OUT direction, so we queue a request for
645 * wMaxPacketSize instead.
648 dwc->ep0_usb_req.dep = dep;
649 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
650 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
651 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
653 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
656 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
662 wValue = le16_to_cpu(ctrl->wValue);
663 wLength = le16_to_cpu(ctrl->wLength);
664 wIndex = le16_to_cpu(ctrl->wIndex);
666 if (wIndex || wLength)
670 * REVISIT It's unclear from Databook what to do with this
671 * value. For now, just cache it.
673 dwc->isoch_delay = wValue;
678 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
682 switch (ctrl->bRequest) {
683 case USB_REQ_GET_STATUS:
684 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
685 ret = dwc3_ep0_handle_status(dwc, ctrl);
687 case USB_REQ_CLEAR_FEATURE:
688 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
689 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
691 case USB_REQ_SET_FEATURE:
692 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
693 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
695 case USB_REQ_SET_ADDRESS:
696 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
697 ret = dwc3_ep0_set_address(dwc, ctrl);
699 case USB_REQ_SET_CONFIGURATION:
700 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
701 ret = dwc3_ep0_set_config(dwc, ctrl);
703 case USB_REQ_SET_SEL:
704 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
705 ret = dwc3_ep0_set_sel(dwc, ctrl);
707 case USB_REQ_SET_ISOCH_DELAY:
708 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
709 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
712 dev_vdbg(dwc->dev, "Forwarding to gadget driver");
713 ret = dwc3_ep0_delegate_req(dwc, ctrl);
720 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
721 const struct dwc3_event_depevt *event)
723 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
727 if (!dwc->gadget_driver)
730 len = le16_to_cpu(ctrl->wLength);
732 dwc->three_stage_setup = false;
733 dwc->ep0_expect_in = false;
734 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
736 dwc->three_stage_setup = true;
737 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
738 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
741 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
742 ret = dwc3_ep0_std_request(dwc, ctrl);
744 ret = dwc3_ep0_delegate_req(dwc, ctrl);
746 if (ret == USB_GADGET_DELAYED_STATUS)
747 dwc->delayed_status = true;
751 dwc3_ep0_stall_and_restart(dwc);
754 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
755 const struct dwc3_event_depevt *event)
757 struct dwc3_request *r = NULL;
758 struct usb_request *ur;
759 struct dwc3_trb *trb;
766 epnum = event->endpoint_number;
769 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
773 r = next_request(&ep0->request_list);
777 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
778 if (status == DWC3_TRBSTS_SETUP_PENDING) {
779 dev_dbg(dwc->dev, "Setup Pending received");
782 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
789 length = trb->size & DWC3_TRB_SIZE_MASK;
791 if (dwc->ep0_bounced) {
792 unsigned transfer_size = ur->length;
793 unsigned maxp = ep0->endpoint.maxpacket;
795 transfer_size += (maxp - (transfer_size % maxp));
796 transferred = min_t(u32, ur->length,
797 transfer_size - length);
798 memcpy(ur->buf, dwc->ep0_bounce, transferred);
800 transferred = ur->length - length;
803 ur->actual += transferred;
805 if ((epnum & 1) && ur->actual < ur->length) {
806 /* for some reason we did not get everything out */
808 dwc3_ep0_stall_and_restart(dwc);
810 dwc3_gadget_giveback(ep0, r, 0);
812 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
813 ur->length && ur->zero) {
816 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
818 ret = dwc3_ep0_start_trans(dwc, epnum,
819 dwc->ctrl_req_addr, 0,
820 DWC3_TRBCTL_CONTROL_DATA);
826 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
827 const struct dwc3_event_depevt *event)
829 struct dwc3_request *r;
831 struct dwc3_trb *trb;
837 if (!list_empty(&dep->request_list)) {
838 r = next_request(&dep->request_list);
840 dwc3_gadget_giveback(dep, r, 0);
843 if (dwc->test_mode) {
846 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
848 dev_dbg(dwc->dev, "Invalid Test #%d",
850 dwc3_ep0_stall_and_restart(dwc);
855 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
856 if (status == DWC3_TRBSTS_SETUP_PENDING)
857 dev_dbg(dwc->dev, "Setup Pending received");
859 dwc->ep0state = EP0_SETUP_PHASE;
860 dwc3_ep0_out_start(dwc);
863 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
864 const struct dwc3_event_depevt *event)
866 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
868 dep->flags &= ~DWC3_EP_BUSY;
869 dep->resource_index = 0;
870 dwc->setup_packet_pending = false;
872 switch (dwc->ep0state) {
873 case EP0_SETUP_PHASE:
874 dev_vdbg(dwc->dev, "Setup Phase");
875 dwc3_ep0_inspect_setup(dwc, event);
879 dev_vdbg(dwc->dev, "Data Phase");
880 dwc3_ep0_complete_data(dwc, event);
883 case EP0_STATUS_PHASE:
884 dev_vdbg(dwc->dev, "Status Phase");
885 dwc3_ep0_complete_status(dwc, event);
888 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
892 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
893 struct dwc3_ep *dep, struct dwc3_request *req)
897 req->direction = !!dep->number;
899 if (req->request.length == 0) {
900 ret = dwc3_ep0_start_trans(dwc, dep->number,
901 dwc->ctrl_req_addr, 0,
902 DWC3_TRBCTL_CONTROL_DATA);
903 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
904 && (dep->number == 0)) {
908 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
911 dev_dbg(dwc->dev, "failed to map request\n");
915 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
917 maxpacket = dep->endpoint.maxpacket;
918 transfer_size = roundup(req->request.length, maxpacket);
920 dwc->ep0_bounced = true;
923 * REVISIT in case request length is bigger than
924 * DWC3_EP0_BOUNCE_SIZE we will need two chained
925 * TRBs to handle the transfer.
927 ret = dwc3_ep0_start_trans(dwc, dep->number,
928 dwc->ep0_bounce_addr, transfer_size,
929 DWC3_TRBCTL_CONTROL_DATA);
931 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
934 dev_dbg(dwc->dev, "failed to map request\n");
938 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
939 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
945 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
947 struct dwc3 *dwc = dep->dwc;
950 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
951 : DWC3_TRBCTL_CONTROL_STATUS2;
953 return dwc3_ep0_start_trans(dwc, dep->number,
954 dwc->ctrl_req_addr, 0, type);
957 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
959 if (dwc->resize_fifos) {
960 dev_dbg(dwc->dev, "Resizing FIFOs");
961 dwc3_gadget_resize_tx_fifos(dwc);
962 dwc->resize_fifos = 0;
965 WARN_ON(dwc3_ep0_start_control_status(dep));
968 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
969 const struct dwc3_event_depevt *event)
971 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
973 __dwc3_ep0_do_control_status(dwc, dep);
976 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
978 struct dwc3_gadget_ep_cmd_params params;
982 if (!dep->resource_index)
985 cmd = DWC3_DEPCMD_ENDTRANSFER;
986 cmd |= DWC3_DEPCMD_CMDIOC;
987 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
988 memset(¶ms, 0, sizeof(params));
989 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
991 dep->resource_index = 0;
994 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
995 const struct dwc3_event_depevt *event)
997 dwc->setup_packet_pending = true;
999 switch (event->status) {
1000 case DEPEVT_STATUS_CONTROL_DATA:
1001 dev_vdbg(dwc->dev, "Control Data");
1004 * We already have a DATA transfer in the controller's cache,
1005 * if we receive a XferNotReady(DATA) we will ignore it, unless
1006 * it's for the wrong direction.
1008 * In that case, we must issue END_TRANSFER command to the Data
1009 * Phase we already have started and issue SetStall on the
1012 if (dwc->ep0_expect_in != event->endpoint_number) {
1013 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1015 dev_vdbg(dwc->dev, "Wrong direction for Data phase");
1016 dwc3_ep0_end_control_data(dwc, dep);
1017 dwc3_ep0_stall_and_restart(dwc);
1023 case DEPEVT_STATUS_CONTROL_STATUS:
1024 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1027 dev_vdbg(dwc->dev, "Control Status");
1029 dwc->ep0state = EP0_STATUS_PHASE;
1031 if (dwc->delayed_status) {
1032 WARN_ON_ONCE(event->endpoint_number != 1);
1033 dev_vdbg(dwc->dev, "Delayed Status");
1037 dwc3_ep0_do_control_status(dwc, event);
1041 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1042 const struct dwc3_event_depevt *event)
1044 u8 epnum = event->endpoint_number;
1046 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
1047 dwc3_ep_event_string(event->endpoint_event),
1048 epnum >> 1, (epnum & 1) ? "in" : "out",
1049 dwc3_ep0_state_string(dwc->ep0state));
1051 switch (event->endpoint_event) {
1052 case DWC3_DEPEVT_XFERCOMPLETE:
1053 dwc3_ep0_xfer_complete(dwc, event);
1056 case DWC3_DEPEVT_XFERNOTREADY:
1057 dwc3_ep0_xfernotready(dwc, event);
1060 case DWC3_DEPEVT_XFERINPROGRESS:
1061 case DWC3_DEPEVT_RXTXFIFOEVT:
1062 case DWC3_DEPEVT_STREAMEVT:
1063 case DWC3_DEPEVT_EPCMDCMPLT: