2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
12 * commit c00552ebaf : Merge 3.18-rc7 into usb-next
14 * SPDX-License-Identifier: GPL-2.0
17 #include <linux/kernel.h>
18 #include <linux/list.h>
20 #include <linux/usb/ch9.h>
21 #include <linux/usb/gadget.h>
22 #include <linux/usb/composite.h>
28 #include "linux-compat.h"
30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
34 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
43 case EP0_STATUS_PHASE:
44 return "Status Phase";
50 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
51 u32 len, u32 type, unsigned chain)
53 struct dwc3_gadget_ep_cmd_params params;
59 dep = dwc->eps[epnum];
60 if (dep->flags & DWC3_EP_BUSY) {
61 dev_vdbg(dwc->dev, "%s still busy", dep->name);
65 trb = &dwc->ep0_trb[dep->free_slot];
70 trb->bpl = lower_32_bits(buf_dma);
71 trb->bph = upper_32_bits(buf_dma);
75 trb->ctrl |= (DWC3_TRB_CTRL_HWO
76 | DWC3_TRB_CTRL_ISP_IMI);
79 trb->ctrl |= DWC3_TRB_CTRL_CHN;
81 trb->ctrl |= (DWC3_TRB_CTRL_IOC
84 dwc3_flush_cache((int)buf_dma, len);
85 dwc3_flush_cache((int)trb, sizeof(*trb));
90 memset(¶ms, 0, sizeof(params));
91 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
92 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
94 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
95 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
97 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
101 dep->flags |= DWC3_EP_BUSY;
102 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
105 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
110 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
111 struct dwc3_request *req)
113 struct dwc3 *dwc = dep->dwc;
115 req->request.actual = 0;
116 req->request.status = -EINPROGRESS;
117 req->epnum = dep->number;
119 list_add_tail(&req->list, &dep->request_list);
122 * Gadget driver might not be quick enough to queue a request
123 * before we get a Transfer Not Ready event on this endpoint.
125 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
126 * flag is set, it's telling us that as soon as Gadget queues the
127 * required request, we should kick the transfer here because the
128 * IRQ we were waiting for is long gone.
130 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
133 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
135 if (dwc->ep0state != EP0_DATA_PHASE) {
136 dev_WARN(dwc->dev, "Unexpected pending request\n");
140 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
142 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
149 * In case gadget driver asked us to delay the STATUS phase,
152 if (dwc->delayed_status) {
155 direction = !dwc->ep0_expect_in;
156 dwc->delayed_status = false;
157 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
159 if (dwc->ep0state == EP0_STATUS_PHASE)
160 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
162 dev_dbg(dwc->dev, "too early for delayed status");
168 * Unfortunately we have uncovered a limitation wrt the Data Phase.
170 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
171 * come before issueing Start Transfer command, but if we do, we will
172 * miss situations where the host starts another SETUP phase instead of
173 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
174 * Layer Compliance Suite.
176 * The problem surfaces due to the fact that in case of back-to-back
177 * SETUP packets there will be no XferNotReady(DATA) generated and we
178 * will be stuck waiting for XferNotReady(DATA) forever.
180 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
181 * it tells us to start Data Phase right away. It also mentions that if
182 * we receive a SETUP phase instead of the DATA phase, core will issue
183 * XferComplete for the DATA phase, before actually initiating it in
184 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
185 * can only be used to print some debugging logs, as the core expects
186 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
187 * just so it completes right away, without transferring anything and,
188 * only then, we can go back to the SETUP phase.
190 * Because of this scenario, SNPS decided to change the programming
191 * model of control transfers and support on-demand transfers only for
192 * the STATUS phase. To fix the issue we have now, we will always wait
193 * for gadget driver to queue the DATA phase's struct usb_request, then
194 * start it right away.
196 * If we're actually in a 2-stage transfer, we will wait for
197 * XferNotReady(STATUS).
199 if (dwc->three_stage_setup) {
202 direction = dwc->ep0_expect_in;
203 dwc->ep0state = EP0_DATA_PHASE;
205 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
207 dep->flags &= ~DWC3_EP0_DIR_IN;
213 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
216 struct dwc3_request *req = to_dwc3_request(request);
217 struct dwc3_ep *dep = to_dwc3_ep(ep);
218 struct dwc3 *dwc = dep->dwc;
224 spin_lock_irqsave(&dwc->lock, flags);
225 if (!dep->endpoint.desc) {
226 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
232 /* we share one TRB for ep0/1 */
233 if (!list_empty(&dep->request_list)) {
238 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
239 request, dep->name, request->length,
240 dwc3_ep0_state_string(dwc->ep0state));
242 ret = __dwc3_gadget_ep0_queue(dep, req);
245 spin_unlock_irqrestore(&dwc->lock, flags);
250 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
254 /* reinitialize physical ep1 */
256 dep->flags = DWC3_EP_ENABLED;
258 /* stall is always issued on EP0 */
260 __dwc3_gadget_ep_set_halt(dep, 1, false);
261 dep->flags = DWC3_EP_ENABLED;
262 dwc->delayed_status = false;
264 if (!list_empty(&dep->request_list)) {
265 struct dwc3_request *req;
267 req = next_request(&dep->request_list);
268 dwc3_gadget_giveback(dep, req, -ECONNRESET);
271 dwc->ep0state = EP0_SETUP_PHASE;
272 dwc3_ep0_out_start(dwc);
275 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
277 struct dwc3_ep *dep = to_dwc3_ep(ep);
278 struct dwc3 *dwc = dep->dwc;
280 dwc3_ep0_stall_and_restart(dwc);
285 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
290 spin_lock_irqsave(&dwc->lock, flags);
291 ret = __dwc3_gadget_ep0_set_halt(ep, value);
292 spin_unlock_irqrestore(&dwc->lock, flags);
297 void dwc3_ep0_out_start(struct dwc3 *dwc)
301 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
302 DWC3_TRBCTL_CONTROL_SETUP, 0);
306 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
309 u32 windex = le16_to_cpu(wIndex_le);
312 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
313 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
316 dep = dwc->eps[epnum];
317 if (dep->flags & DWC3_EP_ENABLED)
323 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
329 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
330 struct usb_ctrlrequest *ctrl)
336 __le16 *response_pkt;
338 recip = ctrl->bRequestType & USB_RECIP_MASK;
340 case USB_RECIP_DEVICE:
342 * LTM will be set once we know how to set this in HW.
344 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
346 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
347 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
348 if (reg & DWC3_DCTL_INITU1ENA)
349 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
350 if (reg & DWC3_DCTL_INITU2ENA)
351 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
356 case USB_RECIP_INTERFACE:
358 * Function Remote Wake Capable D0
359 * Function Remote Wakeup D1
363 case USB_RECIP_ENDPOINT:
364 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
368 if (dep->flags & DWC3_EP_STALL)
369 usb_status = 1 << USB_ENDPOINT_HALT;
375 response_pkt = (__le16 *) dwc->setup_buf;
376 *response_pkt = cpu_to_le16(usb_status);
379 dwc->ep0_usb_req.dep = dep;
380 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
381 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
382 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
384 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
387 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
388 struct usb_ctrlrequest *ctrl, int set)
396 enum usb_device_state state;
398 wValue = le16_to_cpu(ctrl->wValue);
399 wIndex = le16_to_cpu(ctrl->wIndex);
400 recip = ctrl->bRequestType & USB_RECIP_MASK;
401 state = dwc->gadget.state;
404 case USB_RECIP_DEVICE:
407 case USB_DEVICE_REMOTE_WAKEUP:
410 * 9.4.1 says only only for SS, in AddressState only for
411 * default control pipe
413 case USB_DEVICE_U1_ENABLE:
414 if (state != USB_STATE_CONFIGURED)
416 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
419 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
421 reg |= DWC3_DCTL_INITU1ENA;
423 reg &= ~DWC3_DCTL_INITU1ENA;
424 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
427 case USB_DEVICE_U2_ENABLE:
428 if (state != USB_STATE_CONFIGURED)
430 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
433 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
435 reg |= DWC3_DCTL_INITU2ENA;
437 reg &= ~DWC3_DCTL_INITU2ENA;
438 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
441 case USB_DEVICE_LTM_ENABLE:
444 case USB_DEVICE_TEST_MODE:
445 if ((wIndex & 0xff) != 0)
450 dwc->test_mode_nr = wIndex >> 8;
451 dwc->test_mode = true;
458 case USB_RECIP_INTERFACE:
460 case USB_INTRF_FUNC_SUSPEND:
461 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
462 /* XXX enable Low power suspend */
464 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
465 /* XXX enable remote wakeup */
473 case USB_RECIP_ENDPOINT:
475 case USB_ENDPOINT_HALT:
476 dep = dwc3_wIndex_to_dep(dwc, wIndex);
479 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
481 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
497 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
499 enum usb_device_state state = dwc->gadget.state;
503 addr = le16_to_cpu(ctrl->wValue);
505 dev_dbg(dwc->dev, "invalid device address %d", addr);
509 if (state == USB_STATE_CONFIGURED) {
510 dev_dbg(dwc->dev, "trying to set address when configured");
514 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
515 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
516 reg |= DWC3_DCFG_DEVADDR(addr);
517 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
520 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
522 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
527 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
531 spin_unlock(&dwc->lock);
532 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
533 spin_lock(&dwc->lock);
537 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
539 enum usb_device_state state = dwc->gadget.state;
544 dwc->start_config_issued = false;
545 cfg = le16_to_cpu(ctrl->wValue);
548 case USB_STATE_DEFAULT:
551 case USB_STATE_ADDRESS:
552 ret = dwc3_ep0_delegate_req(dwc, ctrl);
553 /* if the cfg matches and the cfg is non zero */
554 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
557 * only change state if set_config has already
558 * been processed. If gadget driver returns
559 * USB_GADGET_DELAYED_STATUS, we will wait
560 * to change the state on the next usb_ep_queue()
563 usb_gadget_set_state(&dwc->gadget,
564 USB_STATE_CONFIGURED);
567 * Enable transition to U1/U2 state when
568 * nothing is pending from application.
570 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
571 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
572 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
574 dwc->resize_fifos = true;
575 dev_dbg(dwc->dev, "resize FIFOs flag SET");
579 case USB_STATE_CONFIGURED:
580 ret = dwc3_ep0_delegate_req(dwc, ctrl);
582 usb_gadget_set_state(&dwc->gadget,
591 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
593 struct dwc3_ep *dep = to_dwc3_ep(ep);
594 struct dwc3 *dwc = dep->dwc;
608 memcpy(&timing, req->buf, sizeof(timing));
610 dwc->u1sel = timing.u1sel;
611 dwc->u1pel = timing.u1pel;
612 dwc->u2sel = le16_to_cpu(timing.u2sel);
613 dwc->u2pel = le16_to_cpu(timing.u2pel);
615 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
616 if (reg & DWC3_DCTL_INITU2ENA)
618 if (reg & DWC3_DCTL_INITU1ENA)
622 * According to Synopsys Databook, if parameter is
623 * greater than 125, a value of zero should be
624 * programmed in the register.
629 /* now that we have the time, issue DGCMD Set Sel */
630 ret = dwc3_send_gadget_generic_command(dwc,
631 DWC3_DGCMD_SET_PERIODIC_PAR, param);
635 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
638 enum usb_device_state state = dwc->gadget.state;
641 if (state == USB_STATE_DEFAULT)
644 wLength = le16_to_cpu(ctrl->wLength);
647 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
653 * To handle Set SEL we need to receive 6 bytes from Host. So let's
654 * queue a usb_request for 6 bytes.
656 * Remember, though, this controller can't handle non-wMaxPacketSize
657 * aligned transfers on the OUT direction, so we queue a request for
658 * wMaxPacketSize instead.
661 dwc->ep0_usb_req.dep = dep;
662 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
663 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
664 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
666 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
669 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
675 wValue = le16_to_cpu(ctrl->wValue);
676 wLength = le16_to_cpu(ctrl->wLength);
677 wIndex = le16_to_cpu(ctrl->wIndex);
679 if (wIndex || wLength)
683 * REVISIT It's unclear from Databook what to do with this
684 * value. For now, just cache it.
686 dwc->isoch_delay = wValue;
691 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
695 switch (ctrl->bRequest) {
696 case USB_REQ_GET_STATUS:
697 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
698 ret = dwc3_ep0_handle_status(dwc, ctrl);
700 case USB_REQ_CLEAR_FEATURE:
701 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
702 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
704 case USB_REQ_SET_FEATURE:
705 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
706 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
708 case USB_REQ_SET_ADDRESS:
709 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
710 ret = dwc3_ep0_set_address(dwc, ctrl);
712 case USB_REQ_SET_CONFIGURATION:
713 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
714 ret = dwc3_ep0_set_config(dwc, ctrl);
716 case USB_REQ_SET_SEL:
717 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
718 ret = dwc3_ep0_set_sel(dwc, ctrl);
720 case USB_REQ_SET_ISOCH_DELAY:
721 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
722 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
725 dev_vdbg(dwc->dev, "Forwarding to gadget driver");
726 ret = dwc3_ep0_delegate_req(dwc, ctrl);
733 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
734 const struct dwc3_event_depevt *event)
736 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
740 if (!dwc->gadget_driver)
743 len = le16_to_cpu(ctrl->wLength);
745 dwc->three_stage_setup = false;
746 dwc->ep0_expect_in = false;
747 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
749 dwc->three_stage_setup = true;
750 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
751 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
754 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
755 ret = dwc3_ep0_std_request(dwc, ctrl);
757 ret = dwc3_ep0_delegate_req(dwc, ctrl);
759 if (ret == USB_GADGET_DELAYED_STATUS)
760 dwc->delayed_status = true;
764 dwc3_ep0_stall_and_restart(dwc);
767 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
768 const struct dwc3_event_depevt *event)
770 struct dwc3_request *r = NULL;
771 struct usb_request *ur;
772 struct dwc3_trb *trb;
774 unsigned transfer_size = 0;
782 epnum = event->endpoint_number;
785 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
789 r = next_request(&ep0->request_list);
793 dwc3_flush_cache((int)trb, sizeof(*trb));
795 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
796 if (status == DWC3_TRBSTS_SETUP_PENDING) {
797 dev_dbg(dwc->dev, "Setup Pending received");
800 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
808 length = trb->size & DWC3_TRB_SIZE_MASK;
810 maxp = ep0->endpoint.maxpacket;
812 if (dwc->ep0_bounced) {
814 * Handle the first TRB before handling the bounce buffer if
815 * the request length is greater than the bounce buffer size.
817 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
818 transfer_size = (ur->length / maxp) * maxp;
819 transferred = transfer_size - length;
820 buf = (u8 *)buf + transferred;
821 ur->actual += transferred;
824 dwc3_flush_cache((int)trb, sizeof(*trb));
825 length = trb->size & DWC3_TRB_SIZE_MASK;
830 transfer_size = roundup((ur->length - transfer_size),
832 transferred = min_t(u32, ur->length - transferred,
833 transfer_size - length);
834 dwc3_flush_cache((int)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
835 memcpy(buf, dwc->ep0_bounce, transferred);
837 transferred = ur->length - length;
840 ur->actual += transferred;
842 if ((epnum & 1) && ur->actual < ur->length) {
843 /* for some reason we did not get everything out */
845 dwc3_ep0_stall_and_restart(dwc);
847 dwc3_gadget_giveback(ep0, r, 0);
849 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
850 ur->length && ur->zero) {
853 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
855 ret = dwc3_ep0_start_trans(dwc, epnum,
856 dwc->ctrl_req_addr, 0,
857 DWC3_TRBCTL_CONTROL_DATA, 0);
863 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
864 const struct dwc3_event_depevt *event)
866 struct dwc3_request *r;
868 struct dwc3_trb *trb;
874 if (!list_empty(&dep->request_list)) {
875 r = next_request(&dep->request_list);
877 dwc3_gadget_giveback(dep, r, 0);
880 if (dwc->test_mode) {
883 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
885 dev_dbg(dwc->dev, "Invalid Test #%d",
887 dwc3_ep0_stall_and_restart(dwc);
892 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
893 if (status == DWC3_TRBSTS_SETUP_PENDING)
894 dev_dbg(dwc->dev, "Setup Pending received");
896 dwc->ep0state = EP0_SETUP_PHASE;
897 dwc3_ep0_out_start(dwc);
900 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
901 const struct dwc3_event_depevt *event)
903 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
905 dep->flags &= ~DWC3_EP_BUSY;
906 dep->resource_index = 0;
907 dwc->setup_packet_pending = false;
909 switch (dwc->ep0state) {
910 case EP0_SETUP_PHASE:
911 dev_vdbg(dwc->dev, "Setup Phase");
912 dwc3_ep0_inspect_setup(dwc, event);
916 dev_vdbg(dwc->dev, "Data Phase");
917 dwc3_ep0_complete_data(dwc, event);
920 case EP0_STATUS_PHASE:
921 dev_vdbg(dwc->dev, "Status Phase");
922 dwc3_ep0_complete_status(dwc, event);
925 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
929 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
930 struct dwc3_ep *dep, struct dwc3_request *req)
934 req->direction = !!dep->number;
936 if (req->request.length == 0) {
937 ret = dwc3_ep0_start_trans(dwc, dep->number,
938 dwc->ctrl_req_addr, 0,
939 DWC3_TRBCTL_CONTROL_DATA, 0);
940 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
941 (dep->number == 0)) {
942 u32 transfer_size = 0;
945 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
948 dev_dbg(dwc->dev, "failed to map request\n");
952 maxpacket = dep->endpoint.maxpacket;
953 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
954 transfer_size = (req->request.length / maxpacket) *
956 ret = dwc3_ep0_start_trans(dwc, dep->number,
959 DWC3_TRBCTL_CONTROL_DATA, 1);
962 transfer_size = roundup((req->request.length - transfer_size),
965 dwc->ep0_bounced = true;
968 * REVISIT in case request length is bigger than
969 * DWC3_EP0_BOUNCE_SIZE we will need two chained
970 * TRBs to handle the transfer.
972 ret = dwc3_ep0_start_trans(dwc, dep->number,
973 dwc->ep0_bounce_addr, transfer_size,
974 DWC3_TRBCTL_CONTROL_DATA, 0);
976 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
979 dev_dbg(dwc->dev, "failed to map request\n");
983 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
985 DWC3_TRBCTL_CONTROL_DATA, 0);
991 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
993 struct dwc3 *dwc = dep->dwc;
996 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
997 : DWC3_TRBCTL_CONTROL_STATUS2;
999 return dwc3_ep0_start_trans(dwc, dep->number,
1000 dwc->ctrl_req_addr, 0, type, 0);
1003 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1005 if (dwc->resize_fifos) {
1006 dev_dbg(dwc->dev, "Resizing FIFOs");
1007 dwc3_gadget_resize_tx_fifos(dwc);
1008 dwc->resize_fifos = 0;
1011 WARN_ON(dwc3_ep0_start_control_status(dep));
1014 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1015 const struct dwc3_event_depevt *event)
1017 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1019 __dwc3_ep0_do_control_status(dwc, dep);
1022 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1024 struct dwc3_gadget_ep_cmd_params params;
1028 if (!dep->resource_index)
1031 cmd = DWC3_DEPCMD_ENDTRANSFER;
1032 cmd |= DWC3_DEPCMD_CMDIOC;
1033 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1034 memset(¶ms, 0, sizeof(params));
1035 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1037 dep->resource_index = 0;
1040 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1041 const struct dwc3_event_depevt *event)
1043 dwc->setup_packet_pending = true;
1045 switch (event->status) {
1046 case DEPEVT_STATUS_CONTROL_DATA:
1047 dev_vdbg(dwc->dev, "Control Data");
1050 * We already have a DATA transfer in the controller's cache,
1051 * if we receive a XferNotReady(DATA) we will ignore it, unless
1052 * it's for the wrong direction.
1054 * In that case, we must issue END_TRANSFER command to the Data
1055 * Phase we already have started and issue SetStall on the
1058 if (dwc->ep0_expect_in != event->endpoint_number) {
1059 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1061 dev_vdbg(dwc->dev, "Wrong direction for Data phase");
1062 dwc3_ep0_end_control_data(dwc, dep);
1063 dwc3_ep0_stall_and_restart(dwc);
1069 case DEPEVT_STATUS_CONTROL_STATUS:
1070 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1073 dev_vdbg(dwc->dev, "Control Status");
1075 dwc->ep0state = EP0_STATUS_PHASE;
1077 if (dwc->delayed_status) {
1078 WARN_ON_ONCE(event->endpoint_number != 1);
1079 dev_vdbg(dwc->dev, "Delayed Status");
1083 dwc3_ep0_do_control_status(dwc, event);
1087 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1088 const struct dwc3_event_depevt *event)
1090 u8 epnum = event->endpoint_number;
1092 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
1093 dwc3_ep_event_string(event->endpoint_event),
1094 epnum >> 1, (epnum & 1) ? "in" : "out",
1095 dwc3_ep0_state_string(dwc->ep0state));
1097 switch (event->endpoint_event) {
1098 case DWC3_DEPEVT_XFERCOMPLETE:
1099 dwc3_ep0_xfer_complete(dwc, event);
1102 case DWC3_DEPEVT_XFERNOTREADY:
1103 dwc3_ep0_xfernotready(dwc, event);
1106 case DWC3_DEPEVT_XFERINPROGRESS:
1107 case DWC3_DEPEVT_RXTXFIFOEVT:
1108 case DWC3_DEPEVT_STREAMEVT:
1109 case DWC3_DEPEVT_EPCMDCMPLT: