2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
12 * commit c00552ebaf : Merge 3.18-rc7 into usb-next
14 * SPDX-License-Identifier: GPL-2.0
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/interrupt.h>
24 #include <linux/list.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/composite.h>
36 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
37 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
38 struct dwc3_ep *dep, struct dwc3_request *req);
40 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
49 case EP0_STATUS_PHASE:
50 return "Status Phase";
56 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
59 struct dwc3_gadget_ep_cmd_params params;
65 dep = dwc->eps[epnum];
66 if (dep->flags & DWC3_EP_BUSY) {
67 dev_vdbg(dwc->dev, "%s still busy", dep->name);
73 trb->bpl = lower_32_bits(buf_dma);
74 trb->bph = upper_32_bits(buf_dma);
78 trb->ctrl |= (DWC3_TRB_CTRL_HWO
81 | DWC3_TRB_CTRL_ISP_IMI);
83 memset(¶ms, 0, sizeof(params));
84 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
85 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
87 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
88 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
90 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
94 dep->flags |= DWC3_EP_BUSY;
95 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
98 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
103 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
104 struct dwc3_request *req)
106 struct dwc3 *dwc = dep->dwc;
108 req->request.actual = 0;
109 req->request.status = -EINPROGRESS;
110 req->epnum = dep->number;
112 list_add_tail(&req->list, &dep->request_list);
115 * Gadget driver might not be quick enough to queue a request
116 * before we get a Transfer Not Ready event on this endpoint.
118 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
119 * flag is set, it's telling us that as soon as Gadget queues the
120 * required request, we should kick the transfer here because the
121 * IRQ we were waiting for is long gone.
123 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
126 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
128 if (dwc->ep0state != EP0_DATA_PHASE) {
129 dev_WARN(dwc->dev, "Unexpected pending request\n");
133 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
135 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
142 * In case gadget driver asked us to delay the STATUS phase,
145 if (dwc->delayed_status) {
148 direction = !dwc->ep0_expect_in;
149 dwc->delayed_status = false;
150 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
152 if (dwc->ep0state == EP0_STATUS_PHASE)
153 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
155 dev_dbg(dwc->dev, "too early for delayed status");
161 * Unfortunately we have uncovered a limitation wrt the Data Phase.
163 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
164 * come before issueing Start Transfer command, but if we do, we will
165 * miss situations where the host starts another SETUP phase instead of
166 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
167 * Layer Compliance Suite.
169 * The problem surfaces due to the fact that in case of back-to-back
170 * SETUP packets there will be no XferNotReady(DATA) generated and we
171 * will be stuck waiting for XferNotReady(DATA) forever.
173 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
174 * it tells us to start Data Phase right away. It also mentions that if
175 * we receive a SETUP phase instead of the DATA phase, core will issue
176 * XferComplete for the DATA phase, before actually initiating it in
177 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
178 * can only be used to print some debugging logs, as the core expects
179 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
180 * just so it completes right away, without transferring anything and,
181 * only then, we can go back to the SETUP phase.
183 * Because of this scenario, SNPS decided to change the programming
184 * model of control transfers and support on-demand transfers only for
185 * the STATUS phase. To fix the issue we have now, we will always wait
186 * for gadget driver to queue the DATA phase's struct usb_request, then
187 * start it right away.
189 * If we're actually in a 2-stage transfer, we will wait for
190 * XferNotReady(STATUS).
192 if (dwc->three_stage_setup) {
195 direction = dwc->ep0_expect_in;
196 dwc->ep0state = EP0_DATA_PHASE;
198 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
200 dep->flags &= ~DWC3_EP0_DIR_IN;
206 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
209 struct dwc3_request *req = to_dwc3_request(request);
210 struct dwc3_ep *dep = to_dwc3_ep(ep);
211 struct dwc3 *dwc = dep->dwc;
217 spin_lock_irqsave(&dwc->lock, flags);
218 if (!dep->endpoint.desc) {
219 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
225 /* we share one TRB for ep0/1 */
226 if (!list_empty(&dep->request_list)) {
231 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
232 request, dep->name, request->length,
233 dwc3_ep0_state_string(dwc->ep0state));
235 ret = __dwc3_gadget_ep0_queue(dep, req);
238 spin_unlock_irqrestore(&dwc->lock, flags);
243 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
247 /* reinitialize physical ep1 */
249 dep->flags = DWC3_EP_ENABLED;
251 /* stall is always issued on EP0 */
253 __dwc3_gadget_ep_set_halt(dep, 1, false);
254 dep->flags = DWC3_EP_ENABLED;
255 dwc->delayed_status = false;
257 if (!list_empty(&dep->request_list)) {
258 struct dwc3_request *req;
260 req = next_request(&dep->request_list);
261 dwc3_gadget_giveback(dep, req, -ECONNRESET);
264 dwc->ep0state = EP0_SETUP_PHASE;
265 dwc3_ep0_out_start(dwc);
268 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
270 struct dwc3_ep *dep = to_dwc3_ep(ep);
271 struct dwc3 *dwc = dep->dwc;
273 dwc3_ep0_stall_and_restart(dwc);
278 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
280 struct dwc3_ep *dep = to_dwc3_ep(ep);
281 struct dwc3 *dwc = dep->dwc;
285 spin_lock_irqsave(&dwc->lock, flags);
286 ret = __dwc3_gadget_ep0_set_halt(ep, value);
287 spin_unlock_irqrestore(&dwc->lock, flags);
292 void dwc3_ep0_out_start(struct dwc3 *dwc)
296 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
297 DWC3_TRBCTL_CONTROL_SETUP);
301 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
304 u32 windex = le16_to_cpu(wIndex_le);
307 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
308 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
311 dep = dwc->eps[epnum];
312 if (dep->flags & DWC3_EP_ENABLED)
318 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
324 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
325 struct usb_ctrlrequest *ctrl)
331 __le16 *response_pkt;
333 recip = ctrl->bRequestType & USB_RECIP_MASK;
335 case USB_RECIP_DEVICE:
337 * LTM will be set once we know how to set this in HW.
339 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
341 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
342 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
343 if (reg & DWC3_DCTL_INITU1ENA)
344 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
345 if (reg & DWC3_DCTL_INITU2ENA)
346 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
351 case USB_RECIP_INTERFACE:
353 * Function Remote Wake Capable D0
354 * Function Remote Wakeup D1
358 case USB_RECIP_ENDPOINT:
359 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
363 if (dep->flags & DWC3_EP_STALL)
364 usb_status = 1 << USB_ENDPOINT_HALT;
370 response_pkt = (__le16 *) dwc->setup_buf;
371 *response_pkt = cpu_to_le16(usb_status);
374 dwc->ep0_usb_req.dep = dep;
375 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
376 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
377 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
379 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
382 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
383 struct usb_ctrlrequest *ctrl, int set)
391 enum usb_device_state state;
393 wValue = le16_to_cpu(ctrl->wValue);
394 wIndex = le16_to_cpu(ctrl->wIndex);
395 recip = ctrl->bRequestType & USB_RECIP_MASK;
396 state = dwc->gadget.state;
399 case USB_RECIP_DEVICE:
402 case USB_DEVICE_REMOTE_WAKEUP:
405 * 9.4.1 says only only for SS, in AddressState only for
406 * default control pipe
408 case USB_DEVICE_U1_ENABLE:
409 if (state != USB_STATE_CONFIGURED)
411 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
414 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
416 reg |= DWC3_DCTL_INITU1ENA;
418 reg &= ~DWC3_DCTL_INITU1ENA;
419 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
422 case USB_DEVICE_U2_ENABLE:
423 if (state != USB_STATE_CONFIGURED)
425 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
428 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
430 reg |= DWC3_DCTL_INITU2ENA;
432 reg &= ~DWC3_DCTL_INITU2ENA;
433 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
436 case USB_DEVICE_LTM_ENABLE:
439 case USB_DEVICE_TEST_MODE:
440 if ((wIndex & 0xff) != 0)
445 dwc->test_mode_nr = wIndex >> 8;
446 dwc->test_mode = true;
453 case USB_RECIP_INTERFACE:
455 case USB_INTRF_FUNC_SUSPEND:
456 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
457 /* XXX enable Low power suspend */
459 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
460 /* XXX enable remote wakeup */
468 case USB_RECIP_ENDPOINT:
470 case USB_ENDPOINT_HALT:
471 dep = dwc3_wIndex_to_dep(dwc, wIndex);
474 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
476 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
492 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
494 enum usb_device_state state = dwc->gadget.state;
498 addr = le16_to_cpu(ctrl->wValue);
500 dev_dbg(dwc->dev, "invalid device address %d", addr);
504 if (state == USB_STATE_CONFIGURED) {
505 dev_dbg(dwc->dev, "trying to set address when configured");
509 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
510 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
511 reg |= DWC3_DCFG_DEVADDR(addr);
512 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
515 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
517 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
522 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
526 spin_unlock(&dwc->lock);
527 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
528 spin_lock(&dwc->lock);
532 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
534 enum usb_device_state state = dwc->gadget.state;
539 dwc->start_config_issued = false;
540 cfg = le16_to_cpu(ctrl->wValue);
543 case USB_STATE_DEFAULT:
546 case USB_STATE_ADDRESS:
547 ret = dwc3_ep0_delegate_req(dwc, ctrl);
548 /* if the cfg matches and the cfg is non zero */
549 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
552 * only change state if set_config has already
553 * been processed. If gadget driver returns
554 * USB_GADGET_DELAYED_STATUS, we will wait
555 * to change the state on the next usb_ep_queue()
558 usb_gadget_set_state(&dwc->gadget,
559 USB_STATE_CONFIGURED);
562 * Enable transition to U1/U2 state when
563 * nothing is pending from application.
565 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
566 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
567 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
569 dwc->resize_fifos = true;
570 dev_dbg(dwc->dev, "resize FIFOs flag SET");
574 case USB_STATE_CONFIGURED:
575 ret = dwc3_ep0_delegate_req(dwc, ctrl);
577 usb_gadget_set_state(&dwc->gadget,
586 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
588 struct dwc3_ep *dep = to_dwc3_ep(ep);
589 struct dwc3 *dwc = dep->dwc;
603 memcpy(&timing, req->buf, sizeof(timing));
605 dwc->u1sel = timing.u1sel;
606 dwc->u1pel = timing.u1pel;
607 dwc->u2sel = le16_to_cpu(timing.u2sel);
608 dwc->u2pel = le16_to_cpu(timing.u2pel);
610 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
611 if (reg & DWC3_DCTL_INITU2ENA)
613 if (reg & DWC3_DCTL_INITU1ENA)
617 * According to Synopsys Databook, if parameter is
618 * greater than 125, a value of zero should be
619 * programmed in the register.
624 /* now that we have the time, issue DGCMD Set Sel */
625 ret = dwc3_send_gadget_generic_command(dwc,
626 DWC3_DGCMD_SET_PERIODIC_PAR, param);
630 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
633 enum usb_device_state state = dwc->gadget.state;
637 if (state == USB_STATE_DEFAULT)
640 wValue = le16_to_cpu(ctrl->wValue);
641 wLength = le16_to_cpu(ctrl->wLength);
644 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
650 * To handle Set SEL we need to receive 6 bytes from Host. So let's
651 * queue a usb_request for 6 bytes.
653 * Remember, though, this controller can't handle non-wMaxPacketSize
654 * aligned transfers on the OUT direction, so we queue a request for
655 * wMaxPacketSize instead.
658 dwc->ep0_usb_req.dep = dep;
659 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
660 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
661 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
663 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
666 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
672 wValue = le16_to_cpu(ctrl->wValue);
673 wLength = le16_to_cpu(ctrl->wLength);
674 wIndex = le16_to_cpu(ctrl->wIndex);
676 if (wIndex || wLength)
680 * REVISIT It's unclear from Databook what to do with this
681 * value. For now, just cache it.
683 dwc->isoch_delay = wValue;
688 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
692 switch (ctrl->bRequest) {
693 case USB_REQ_GET_STATUS:
694 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
695 ret = dwc3_ep0_handle_status(dwc, ctrl);
697 case USB_REQ_CLEAR_FEATURE:
698 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
699 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
701 case USB_REQ_SET_FEATURE:
702 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
703 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
705 case USB_REQ_SET_ADDRESS:
706 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
707 ret = dwc3_ep0_set_address(dwc, ctrl);
709 case USB_REQ_SET_CONFIGURATION:
710 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
711 ret = dwc3_ep0_set_config(dwc, ctrl);
713 case USB_REQ_SET_SEL:
714 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
715 ret = dwc3_ep0_set_sel(dwc, ctrl);
717 case USB_REQ_SET_ISOCH_DELAY:
718 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
719 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
722 dev_vdbg(dwc->dev, "Forwarding to gadget driver");
723 ret = dwc3_ep0_delegate_req(dwc, ctrl);
730 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
731 const struct dwc3_event_depevt *event)
733 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
737 if (!dwc->gadget_driver)
740 len = le16_to_cpu(ctrl->wLength);
742 dwc->three_stage_setup = false;
743 dwc->ep0_expect_in = false;
744 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
746 dwc->three_stage_setup = true;
747 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
748 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
751 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
752 ret = dwc3_ep0_std_request(dwc, ctrl);
754 ret = dwc3_ep0_delegate_req(dwc, ctrl);
756 if (ret == USB_GADGET_DELAYED_STATUS)
757 dwc->delayed_status = true;
761 dwc3_ep0_stall_and_restart(dwc);
764 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
765 const struct dwc3_event_depevt *event)
767 struct dwc3_request *r = NULL;
768 struct usb_request *ur;
769 struct dwc3_trb *trb;
776 epnum = event->endpoint_number;
779 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
783 r = next_request(&ep0->request_list);
787 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
788 if (status == DWC3_TRBSTS_SETUP_PENDING) {
789 dev_dbg(dwc->dev, "Setup Pending received");
792 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
799 length = trb->size & DWC3_TRB_SIZE_MASK;
801 if (dwc->ep0_bounced) {
802 unsigned transfer_size = ur->length;
803 unsigned maxp = ep0->endpoint.maxpacket;
805 transfer_size += (maxp - (transfer_size % maxp));
806 transferred = min_t(u32, ur->length,
807 transfer_size - length);
808 memcpy(ur->buf, dwc->ep0_bounce, transferred);
810 transferred = ur->length - length;
813 ur->actual += transferred;
815 if ((epnum & 1) && ur->actual < ur->length) {
816 /* for some reason we did not get everything out */
818 dwc3_ep0_stall_and_restart(dwc);
820 dwc3_gadget_giveback(ep0, r, 0);
822 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
823 ur->length && ur->zero) {
826 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
828 ret = dwc3_ep0_start_trans(dwc, epnum,
829 dwc->ctrl_req_addr, 0,
830 DWC3_TRBCTL_CONTROL_DATA);
836 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
837 const struct dwc3_event_depevt *event)
839 struct dwc3_request *r;
841 struct dwc3_trb *trb;
847 if (!list_empty(&dep->request_list)) {
848 r = next_request(&dep->request_list);
850 dwc3_gadget_giveback(dep, r, 0);
853 if (dwc->test_mode) {
856 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
858 dev_dbg(dwc->dev, "Invalid Test #%d",
860 dwc3_ep0_stall_and_restart(dwc);
865 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
866 if (status == DWC3_TRBSTS_SETUP_PENDING)
867 dev_dbg(dwc->dev, "Setup Pending received");
869 dwc->ep0state = EP0_SETUP_PHASE;
870 dwc3_ep0_out_start(dwc);
873 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
874 const struct dwc3_event_depevt *event)
876 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
878 dep->flags &= ~DWC3_EP_BUSY;
879 dep->resource_index = 0;
880 dwc->setup_packet_pending = false;
882 switch (dwc->ep0state) {
883 case EP0_SETUP_PHASE:
884 dev_vdbg(dwc->dev, "Setup Phase");
885 dwc3_ep0_inspect_setup(dwc, event);
889 dev_vdbg(dwc->dev, "Data Phase");
890 dwc3_ep0_complete_data(dwc, event);
893 case EP0_STATUS_PHASE:
894 dev_vdbg(dwc->dev, "Status Phase");
895 dwc3_ep0_complete_status(dwc, event);
898 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
902 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
903 struct dwc3_ep *dep, struct dwc3_request *req)
907 req->direction = !!dep->number;
909 if (req->request.length == 0) {
910 ret = dwc3_ep0_start_trans(dwc, dep->number,
911 dwc->ctrl_req_addr, 0,
912 DWC3_TRBCTL_CONTROL_DATA);
913 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
914 && (dep->number == 0)) {
918 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
921 dev_dbg(dwc->dev, "failed to map request\n");
925 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
927 maxpacket = dep->endpoint.maxpacket;
928 transfer_size = roundup(req->request.length, maxpacket);
930 dwc->ep0_bounced = true;
933 * REVISIT in case request length is bigger than
934 * DWC3_EP0_BOUNCE_SIZE we will need two chained
935 * TRBs to handle the transfer.
937 ret = dwc3_ep0_start_trans(dwc, dep->number,
938 dwc->ep0_bounce_addr, transfer_size,
939 DWC3_TRBCTL_CONTROL_DATA);
941 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
944 dev_dbg(dwc->dev, "failed to map request\n");
948 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
949 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
955 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
957 struct dwc3 *dwc = dep->dwc;
960 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
961 : DWC3_TRBCTL_CONTROL_STATUS2;
963 return dwc3_ep0_start_trans(dwc, dep->number,
964 dwc->ctrl_req_addr, 0, type);
967 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
969 if (dwc->resize_fifos) {
970 dev_dbg(dwc->dev, "Resizing FIFOs");
971 dwc3_gadget_resize_tx_fifos(dwc);
972 dwc->resize_fifos = 0;
975 WARN_ON(dwc3_ep0_start_control_status(dep));
978 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
979 const struct dwc3_event_depevt *event)
981 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
983 __dwc3_ep0_do_control_status(dwc, dep);
986 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
988 struct dwc3_gadget_ep_cmd_params params;
992 if (!dep->resource_index)
995 cmd = DWC3_DEPCMD_ENDTRANSFER;
996 cmd |= DWC3_DEPCMD_CMDIOC;
997 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
998 memset(¶ms, 0, sizeof(params));
999 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1001 dep->resource_index = 0;
1004 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1005 const struct dwc3_event_depevt *event)
1007 dwc->setup_packet_pending = true;
1009 switch (event->status) {
1010 case DEPEVT_STATUS_CONTROL_DATA:
1011 dev_vdbg(dwc->dev, "Control Data");
1014 * We already have a DATA transfer in the controller's cache,
1015 * if we receive a XferNotReady(DATA) we will ignore it, unless
1016 * it's for the wrong direction.
1018 * In that case, we must issue END_TRANSFER command to the Data
1019 * Phase we already have started and issue SetStall on the
1022 if (dwc->ep0_expect_in != event->endpoint_number) {
1023 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1025 dev_vdbg(dwc->dev, "Wrong direction for Data phase");
1026 dwc3_ep0_end_control_data(dwc, dep);
1027 dwc3_ep0_stall_and_restart(dwc);
1033 case DEPEVT_STATUS_CONTROL_STATUS:
1034 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1037 dev_vdbg(dwc->dev, "Control Status");
1039 dwc->ep0state = EP0_STATUS_PHASE;
1041 if (dwc->delayed_status) {
1042 WARN_ON_ONCE(event->endpoint_number != 1);
1043 dev_vdbg(dwc->dev, "Delayed Status");
1047 dwc3_ep0_do_control_status(dwc, event);
1051 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1052 const struct dwc3_event_depevt *event)
1054 u8 epnum = event->endpoint_number;
1056 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
1057 dwc3_ep_event_string(event->endpoint_event),
1058 epnum >> 1, (epnum & 1) ? "in" : "out",
1059 dwc3_ep0_state_string(dwc->ep0state));
1061 switch (event->endpoint_event) {
1062 case DWC3_DEPEVT_XFERCOMPLETE:
1063 dwc3_ep0_xfer_complete(dwc, event);
1066 case DWC3_DEPEVT_XFERNOTREADY:
1067 dwc3_ep0_xfernotready(dwc, event);
1070 case DWC3_DEPEVT_XFERINPROGRESS:
1071 case DWC3_DEPEVT_RXTXFIFOEVT:
1072 case DWC3_DEPEVT_STREAMEVT:
1073 case DWC3_DEPEVT_EPCMDCMPLT: