2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
12 * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
14 * SPDX-License-Identifier: GPL-2.0
19 #include <asm/dma-mapping.h>
20 #include <usb/lin_gadget_compat.h>
21 #include <linux/list.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/gadget.h>
25 #include <asm/arch/sys_proto.h>
31 #include "linux-compat.h"
34 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will
39 * return 0 on success or -EINVAL if wrong Test Selector
42 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
46 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
47 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
61 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67 * dwc3_gadget_get_link_state - Gets current state of USB Link
68 * @dwc: pointer to our context structure
70 * Caller should take care of locking. This function will
71 * return the link state on success (>= 0) or -ETIMEDOUT.
73 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
77 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
79 return DWC3_DSTS_USBLNKST(reg);
83 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
84 * @dwc: pointer to our context structure
85 * @state: the state to put link into
87 * Caller should take care of locking. This function will
88 * return 0 on success or -ETIMEDOUT.
90 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96 * Wait until device controller is ready. Only applies to 1.94a and
99 if (dwc->revision >= DWC3_REVISION_194A) {
101 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
102 if (reg & DWC3_DSTS_DCNRD)
112 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
113 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
115 /* set requested state */
116 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
117 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
120 * The following code is racy when called from dwc3_gadget_wakeup,
121 * and is not needed, at least on newer versions
123 if (dwc->revision >= DWC3_REVISION_194A)
126 /* wait for a change in DSTS */
129 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
131 if (DWC3_DSTS_USBLNKST(reg) == state)
137 dev_vdbg(dwc->dev, "link state change request timed out\n");
143 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
144 * @dwc: pointer to our context structure
146 * This function will a best effort FIFO allocation in order
147 * to improve FIFO usage and throughput, while still allowing
148 * us to enable as many endpoints as possible.
150 * Keep in mind that this operation will be highly dependent
151 * on the configured size for RAM1 - which contains TxFifo -,
152 * the amount of endpoints enabled on coreConsultant tool, and
153 * the width of the Master Bus.
155 * In the ideal world, we would always be able to satisfy the
156 * following equation:
158 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
159 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
161 * Unfortunately, due to many variables that's not always the case.
163 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
165 int last_fifo_depth = 0;
170 if (!dwc->needs_fifo_resize)
173 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
175 /* MDWIDTH is represented in bits, we need it in bytes */
179 * FIXME For now we will only allocate 1 wMaxPacketSize space
180 * for each enabled endpoint, later patches will come to
181 * improve this algorithm so that we better use the internal
184 for (num = 0; num < dwc->num_in_eps; num++) {
185 /* bit0 indicates direction; 1 means IN ep */
186 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
190 if (!(dep->flags & DWC3_EP_ENABLED))
193 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
194 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
198 * REVISIT: the following assumes we will always have enough
199 * space available on the FIFO RAM for all possible use cases.
200 * Make sure that's true somehow and change FIFO allocation
203 * If we have Bulk or Isochronous endpoints, we want
204 * them to be able to be very, very fast. So we're giving
205 * those endpoints a fifo_size which is enough for 3 full
208 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
211 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
213 fifo_size |= (last_fifo_depth << 16);
215 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
216 dep->name, last_fifo_depth, fifo_size & 0xffff);
218 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
220 last_fifo_depth += (fifo_size & 0xffff);
226 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
229 struct dwc3 *dwc = dep->dwc;
234 * Skip LINK TRB. We can't use req->trb and check for
235 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
236 * just completed (not the LINK TRB).
238 if (((dep->busy_slot & DWC3_TRB_MASK) ==
240 usb_endpoint_xfer_isoc(dep->endpoint.desc))
245 list_del(&req->list);
248 if (req->request.status == -EINPROGRESS)
249 req->request.status = status;
251 if (dwc->ep0_bounced && dep->number == 0)
252 dwc->ep0_bounced = false;
254 usb_gadget_unmap_request(&dwc->gadget, &req->request,
257 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
258 req, dep->name, req->request.actual,
259 req->request.length, status);
261 spin_unlock(&dwc->lock);
262 usb_gadget_giveback_request(&dep->endpoint, &req->request);
263 spin_lock(&dwc->lock);
266 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
271 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
272 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
275 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
276 if (!(reg & DWC3_DGCMD_CMDACT)) {
277 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
278 DWC3_DGCMD_STATUS(reg));
283 * We can't sleep here, because it's also called from
293 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
294 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
299 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
300 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
301 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
303 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
305 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
306 if (!(reg & DWC3_DEPCMD_CMDACT)) {
307 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
308 DWC3_DEPCMD_STATUS(reg));
313 * We can't sleep here, because it is also called from
324 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
325 struct dwc3_trb *trb)
327 u32 offset = (char *) trb - (char *) dep->trb_pool;
329 return dep->trb_pool_dma + offset;
332 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
337 if (dep->number == 0 || dep->number == 1)
340 dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
342 (unsigned long *)&dep->trb_pool_dma);
343 if (!dep->trb_pool) {
344 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
352 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
354 dma_free_coherent(dep->trb_pool);
356 dep->trb_pool = NULL;
357 dep->trb_pool_dma = 0;
360 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
362 struct dwc3_gadget_ep_cmd_params params;
365 memset(¶ms, 0x00, sizeof(params));
367 if (dep->number != 1) {
368 cmd = DWC3_DEPCMD_DEPSTARTCFG;
369 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
370 if (dep->number > 1) {
371 if (dwc->start_config_issued)
373 dwc->start_config_issued = true;
374 cmd |= DWC3_DEPCMD_PARAM(2);
377 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
383 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
384 const struct usb_endpoint_descriptor *desc,
385 const struct usb_ss_ep_comp_descriptor *comp_desc,
386 bool ignore, bool restore)
388 struct dwc3_gadget_ep_cmd_params params;
390 memset(¶ms, 0x00, sizeof(params));
392 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
393 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
395 /* Burst size is only needed in SuperSpeed mode */
396 if (dwc->gadget.speed == USB_SPEED_SUPER) {
397 u32 burst = dep->endpoint.maxburst - 1;
399 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
403 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
406 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
407 params.param2 |= dep->saved_state;
410 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
411 | DWC3_DEPCFG_XFER_NOT_READY_EN;
413 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
414 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
415 | DWC3_DEPCFG_STREAM_EVENT_EN;
416 dep->stream_capable = true;
419 if (!usb_endpoint_xfer_control(desc))
420 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
423 * We are doing 1:1 mapping for endpoints, meaning
424 * Physical Endpoints 2 maps to Logical Endpoint 2 and
425 * so on. We consider the direction bit as part of the physical
426 * endpoint number. So USB endpoint 0x81 is 0x03.
428 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
431 * We must use the lower 16 TX FIFOs even though
435 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
437 if (desc->bInterval) {
438 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
439 dep->interval = 1 << (desc->bInterval - 1);
442 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
443 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
446 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
448 struct dwc3_gadget_ep_cmd_params params;
450 memset(¶ms, 0x00, sizeof(params));
452 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
454 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
455 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
459 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
460 * @dep: endpoint to be initialized
461 * @desc: USB Endpoint Descriptor
463 * Caller should take care of locking
465 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
466 const struct usb_endpoint_descriptor *desc,
467 const struct usb_ss_ep_comp_descriptor *comp_desc,
468 bool ignore, bool restore)
470 struct dwc3 *dwc = dep->dwc;
474 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
476 if (!(dep->flags & DWC3_EP_ENABLED)) {
477 ret = dwc3_gadget_start_config(dwc, dep);
482 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
487 if (!(dep->flags & DWC3_EP_ENABLED)) {
488 struct dwc3_trb *trb_st_hw;
489 struct dwc3_trb *trb_link;
491 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
495 dep->endpoint.desc = desc;
496 dep->comp_desc = comp_desc;
497 dep->type = usb_endpoint_type(desc);
498 dep->flags |= DWC3_EP_ENABLED;
500 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
501 reg |= DWC3_DALEPENA_EP(dep->number);
502 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
504 if (!usb_endpoint_xfer_isoc(desc))
507 /* Link TRB for ISOC. The HWO bit is never reset */
508 trb_st_hw = &dep->trb_pool[0];
510 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
511 memset(trb_link, 0, sizeof(*trb_link));
513 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
514 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
515 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
516 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
522 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
523 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
525 struct dwc3_request *req;
527 if (!list_empty(&dep->req_queued)) {
528 dwc3_stop_active_transfer(dwc, dep->number, true);
530 /* - giveback all requests to gadget driver */
531 while (!list_empty(&dep->req_queued)) {
532 req = next_request(&dep->req_queued);
534 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
538 while (!list_empty(&dep->request_list)) {
539 req = next_request(&dep->request_list);
541 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
546 * __dwc3_gadget_ep_disable - Disables a HW endpoint
547 * @dep: the endpoint to disable
549 * This function also removes requests which are currently processed ny the
550 * hardware and those which are not yet scheduled.
551 * Caller should take care of locking.
553 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
555 struct dwc3 *dwc = dep->dwc;
558 dwc3_remove_requests(dwc, dep);
560 /* make sure HW endpoint isn't stalled */
561 if (dep->flags & DWC3_EP_STALL)
562 __dwc3_gadget_ep_set_halt(dep, 0, false);
564 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
565 reg &= ~DWC3_DALEPENA_EP(dep->number);
566 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
568 dep->stream_capable = false;
569 dep->endpoint.desc = NULL;
570 dep->comp_desc = NULL;
577 /* -------------------------------------------------------------------------- */
579 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
580 const struct usb_endpoint_descriptor *desc)
585 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
590 /* -------------------------------------------------------------------------- */
592 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
593 const struct usb_endpoint_descriptor *desc)
599 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
600 pr_debug("dwc3: invalid parameters\n");
604 if (!desc->wMaxPacketSize) {
605 pr_debug("dwc3: missing wMaxPacketSize\n");
609 dep = to_dwc3_ep(ep);
611 if (dep->flags & DWC3_EP_ENABLED) {
612 WARN(true, "%s is already enabled\n",
617 switch (usb_endpoint_type(desc)) {
618 case USB_ENDPOINT_XFER_CONTROL:
619 strlcat(dep->name, "-control", sizeof(dep->name));
621 case USB_ENDPOINT_XFER_ISOC:
622 strlcat(dep->name, "-isoc", sizeof(dep->name));
624 case USB_ENDPOINT_XFER_BULK:
625 strlcat(dep->name, "-bulk", sizeof(dep->name));
627 case USB_ENDPOINT_XFER_INT:
628 strlcat(dep->name, "-int", sizeof(dep->name));
631 dev_err(dwc->dev, "invalid endpoint transfer type\n");
634 spin_lock_irqsave(&dwc->lock, flags);
635 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
636 spin_unlock_irqrestore(&dwc->lock, flags);
641 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
648 pr_debug("dwc3: invalid parameters\n");
652 dep = to_dwc3_ep(ep);
654 if (!(dep->flags & DWC3_EP_ENABLED)) {
655 WARN(true, "%s is already disabled\n",
660 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
662 (dep->number & 1) ? "in" : "out");
664 spin_lock_irqsave(&dwc->lock, flags);
665 ret = __dwc3_gadget_ep_disable(dep);
666 spin_unlock_irqrestore(&dwc->lock, flags);
671 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
674 struct dwc3_request *req;
675 struct dwc3_ep *dep = to_dwc3_ep(ep);
677 req = kzalloc(sizeof(*req), gfp_flags);
681 req->epnum = dep->number;
684 return &req->request;
687 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
688 struct usb_request *request)
690 struct dwc3_request *req = to_dwc3_request(request);
696 * dwc3_prepare_one_trb - setup one TRB from one request
697 * @dep: endpoint for which this request is prepared
698 * @req: dwc3_request pointer
700 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
701 struct dwc3_request *req, dma_addr_t dma,
702 unsigned length, unsigned last, unsigned chain, unsigned node)
704 struct dwc3_trb *trb;
706 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
707 dep->name, req, (unsigned long long) dma,
708 length, last ? " last" : "",
709 chain ? " chain" : "");
712 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
715 dwc3_gadget_move_request_queued(req);
717 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
718 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
722 /* Skip the LINK-TRB on ISOC */
723 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
724 usb_endpoint_xfer_isoc(dep->endpoint.desc))
727 trb->size = DWC3_TRB_SIZE_LENGTH(length);
728 trb->bpl = lower_32_bits(dma);
729 trb->bph = upper_32_bits(dma);
731 switch (usb_endpoint_type(dep->endpoint.desc)) {
732 case USB_ENDPOINT_XFER_CONTROL:
733 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
736 case USB_ENDPOINT_XFER_ISOC:
738 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
740 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
743 case USB_ENDPOINT_XFER_BULK:
744 case USB_ENDPOINT_XFER_INT:
745 trb->ctrl = DWC3_TRBCTL_NORMAL;
749 * This is only possible with faulty memory because we
750 * checked it already :)
755 if (!req->request.no_interrupt && !chain)
756 trb->ctrl |= DWC3_TRB_CTRL_IOC;
758 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
759 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
760 trb->ctrl |= DWC3_TRB_CTRL_CSP;
762 trb->ctrl |= DWC3_TRB_CTRL_LST;
766 trb->ctrl |= DWC3_TRB_CTRL_CHN;
768 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
769 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
771 trb->ctrl |= DWC3_TRB_CTRL_HWO;
775 * dwc3_prepare_trbs - setup TRBs from requests
776 * @dep: endpoint for which requests are being prepared
777 * @starting: true if the endpoint is idle and no requests are queued.
779 * The function goes through the requests list and sets up TRBs for the
780 * transfers. The function returns once there are no more TRBs available or
781 * it runs out of requests.
783 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
785 struct dwc3_request *req, *n;
788 unsigned int last_one = 0;
790 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
792 /* the first request must not be queued */
793 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
795 /* Can't wrap around on a non-isoc EP since there's no link TRB */
796 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
797 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
803 * If busy & slot are equal than it is either full or empty. If we are
804 * starting to process requests then we are empty. Otherwise we are
805 * full and don't do anything
810 trbs_left = DWC3_TRB_NUM;
812 * In case we start from scratch, we queue the ISOC requests
813 * starting from slot 1. This is done because we use ring
814 * buffer and have no LST bit to stop us. Instead, we place
815 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
816 * after the first request so we start at slot 1 and have
817 * 7 requests proceed before we hit the first IOC.
818 * Other transfer types don't use the ring buffer and are
819 * processed from the first TRB until the last one. Since we
820 * don't wrap around we have to start at the beginning.
822 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
831 /* The last TRB is a link TRB, not used for xfer */
832 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
835 list_for_each_entry_safe(req, n, &dep->request_list, list) {
840 dma = req->request.dma;
841 length = req->request.length;
847 /* Is this the last request? */
848 if (list_is_last(&req->list, &dep->request_list))
851 dwc3_prepare_one_trb(dep, req, dma, length,
859 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
862 struct dwc3_gadget_ep_cmd_params params;
863 struct dwc3_request *req;
864 struct dwc3 *dwc = dep->dwc;
868 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
869 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
872 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
875 * If we are getting here after a short-out-packet we don't enqueue any
876 * new requests as we try to set the IOC bit only on the last request.
879 if (list_empty(&dep->req_queued))
880 dwc3_prepare_trbs(dep, start_new);
882 /* req points to the first request which will be sent */
883 req = next_request(&dep->req_queued);
885 dwc3_prepare_trbs(dep, start_new);
888 * req points to the first request where HWO changed from 0 to 1
890 req = next_request(&dep->req_queued);
893 dep->flags |= DWC3_EP_PENDING_REQUEST;
897 memset(¶ms, 0, sizeof(params));
900 params.param0 = upper_32_bits(req->trb_dma);
901 params.param1 = lower_32_bits(req->trb_dma);
902 cmd = DWC3_DEPCMD_STARTTRANSFER;
904 cmd = DWC3_DEPCMD_UPDATETRANSFER;
907 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
908 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
910 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
913 * FIXME we need to iterate over the list of requests
914 * here and stop, unmap, free and del each of the linked
915 * requests instead of what we do now.
917 usb_gadget_unmap_request(&dwc->gadget, &req->request,
919 list_del(&req->list);
923 dep->flags |= DWC3_EP_BUSY;
926 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
928 WARN_ON_ONCE(!dep->resource_index);
934 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
935 struct dwc3_ep *dep, u32 cur_uf)
939 if (list_empty(&dep->request_list)) {
940 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
942 dep->flags |= DWC3_EP_PENDING_REQUEST;
946 /* 4 micro frames in the future */
947 uf = cur_uf + dep->interval * 4;
949 __dwc3_gadget_kick_transfer(dep, uf, 1);
952 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
953 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
957 mask = ~(dep->interval - 1);
958 cur_uf = event->parameters & mask;
960 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
963 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
965 struct dwc3 *dwc = dep->dwc;
968 req->request.actual = 0;
969 req->request.status = -EINPROGRESS;
970 req->direction = dep->direction;
971 req->epnum = dep->number;
974 * We only add to our list of requests now and
975 * start consuming the list once we get XferNotReady
978 * That way, we avoid doing anything that we don't need
979 * to do now and defer it until the point we receive a
980 * particular token from the Host side.
982 * This will also avoid Host cancelling URBs due to too
985 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
990 list_add_tail(&req->list, &dep->request_list);
993 * There are a few special cases:
995 * 1. XferNotReady with empty list of requests. We need to kick the
996 * transfer here in that situation, otherwise we will be NAKing
997 * forever. If we get XferNotReady before gadget driver has a
998 * chance to queue a request, we will ACK the IRQ but won't be
999 * able to receive the data until the next request is queued.
1000 * The following code is handling exactly that.
1003 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1005 * If xfernotready is already elapsed and it is a case
1006 * of isoc transfer, then issue END TRANSFER, so that
1007 * you can receive xfernotready again and can have
1008 * notion of current microframe.
1010 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1011 if (list_empty(&dep->req_queued)) {
1012 dwc3_stop_active_transfer(dwc, dep->number, true);
1013 dep->flags = DWC3_EP_ENABLED;
1018 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1019 if (ret && ret != -EBUSY)
1020 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1026 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1027 * kick the transfer here after queuing a request, otherwise the
1028 * core may not see the modified TRB(s).
1030 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1031 (dep->flags & DWC3_EP_BUSY) &&
1032 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1033 WARN_ON_ONCE(!dep->resource_index);
1034 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1036 if (ret && ret != -EBUSY)
1037 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1043 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1044 * right away, otherwise host will not know we have streams to be
1047 if (dep->stream_capable) {
1050 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1051 if (ret && ret != -EBUSY) {
1052 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1060 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1063 struct dwc3_request *req = to_dwc3_request(request);
1064 struct dwc3_ep *dep = to_dwc3_ep(ep);
1066 unsigned long flags;
1070 spin_lock_irqsave(&dwc->lock, flags);
1071 if (!dep->endpoint.desc) {
1072 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1078 if (req->dep != dep) {
1079 WARN(true, "request %p belongs to '%s'\n",
1080 request, req->dep->name);
1085 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1086 request, ep->name, request->length);
1088 ret = __dwc3_gadget_ep_queue(dep, req);
1091 spin_unlock_irqrestore(&dwc->lock, flags);
1096 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1097 struct usb_request *request)
1099 struct dwc3_request *req = to_dwc3_request(request);
1100 struct dwc3_request *r = NULL;
1102 struct dwc3_ep *dep = to_dwc3_ep(ep);
1103 struct dwc3 *dwc = dep->dwc;
1105 unsigned long flags;
1108 spin_lock_irqsave(&dwc->lock, flags);
1110 list_for_each_entry(r, &dep->request_list, list) {
1116 list_for_each_entry(r, &dep->req_queued, list) {
1121 /* wait until it is processed */
1122 dwc3_stop_active_transfer(dwc, dep->number, true);
1125 dev_err(dwc->dev, "request %p was not queued to %s\n",
1132 /* giveback the request */
1133 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1136 spin_unlock_irqrestore(&dwc->lock, flags);
1141 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1143 struct dwc3_gadget_ep_cmd_params params;
1144 struct dwc3 *dwc = dep->dwc;
1147 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1148 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1152 memset(¶ms, 0x00, sizeof(params));
1155 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1156 (!list_empty(&dep->req_queued) ||
1157 !list_empty(&dep->request_list)))) {
1158 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1163 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1164 DWC3_DEPCMD_SETSTALL, ¶ms);
1166 dev_err(dwc->dev, "failed to set STALL on %s\n",
1169 dep->flags |= DWC3_EP_STALL;
1171 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1172 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1174 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1177 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1183 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1185 struct dwc3_ep *dep = to_dwc3_ep(ep);
1187 unsigned long flags;
1191 spin_lock_irqsave(&dwc->lock, flags);
1192 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1193 spin_unlock_irqrestore(&dwc->lock, flags);
1198 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1200 struct dwc3_ep *dep = to_dwc3_ep(ep);
1201 unsigned long flags;
1204 spin_lock_irqsave(&dwc->lock, flags);
1205 dep->flags |= DWC3_EP_WEDGE;
1207 if (dep->number == 0 || dep->number == 1)
1208 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1210 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1211 spin_unlock_irqrestore(&dwc->lock, flags);
1216 /* -------------------------------------------------------------------------- */
1218 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1219 .bLength = USB_DT_ENDPOINT_SIZE,
1220 .bDescriptorType = USB_DT_ENDPOINT,
1221 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1224 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1225 .enable = dwc3_gadget_ep0_enable,
1226 .disable = dwc3_gadget_ep0_disable,
1227 .alloc_request = dwc3_gadget_ep_alloc_request,
1228 .free_request = dwc3_gadget_ep_free_request,
1229 .queue = dwc3_gadget_ep0_queue,
1230 .dequeue = dwc3_gadget_ep_dequeue,
1231 .set_halt = dwc3_gadget_ep0_set_halt,
1232 .set_wedge = dwc3_gadget_ep_set_wedge,
1235 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1236 .enable = dwc3_gadget_ep_enable,
1237 .disable = dwc3_gadget_ep_disable,
1238 .alloc_request = dwc3_gadget_ep_alloc_request,
1239 .free_request = dwc3_gadget_ep_free_request,
1240 .queue = dwc3_gadget_ep_queue,
1241 .dequeue = dwc3_gadget_ep_dequeue,
1242 .set_halt = dwc3_gadget_ep_set_halt,
1243 .set_wedge = dwc3_gadget_ep_set_wedge,
1246 /* -------------------------------------------------------------------------- */
1248 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1250 struct dwc3 *dwc = gadget_to_dwc(g);
1253 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1254 return DWC3_DSTS_SOFFN(reg);
1257 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1259 struct dwc3 *dwc = gadget_to_dwc(g);
1261 unsigned long timeout;
1262 unsigned long flags;
1271 spin_lock_irqsave(&dwc->lock, flags);
1274 * According to the Databook Remote wakeup request should
1275 * be issued only when the device is in early suspend state.
1277 * We can check that via USB Link State bits in DSTS register.
1279 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1281 speed = reg & DWC3_DSTS_CONNECTSPD;
1282 if (speed == DWC3_DSTS_SUPERSPEED) {
1283 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1288 link_state = DWC3_DSTS_USBLNKST(reg);
1290 switch (link_state) {
1291 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1292 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1295 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1301 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1303 dev_err(dwc->dev, "failed to put link in Recovery\n");
1307 /* Recent versions do this automatically */
1308 if (dwc->revision < DWC3_REVISION_194A) {
1309 /* write zeroes to Link Change Request */
1310 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1311 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1312 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1315 /* poll until Link State changes to ON */
1319 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1321 /* in HS, means ON */
1322 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1326 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1327 dev_err(dwc->dev, "failed to send remote wakeup\n");
1332 spin_unlock_irqrestore(&dwc->lock, flags);
1337 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1340 struct dwc3 *dwc = gadget_to_dwc(g);
1341 unsigned long flags;
1343 spin_lock_irqsave(&dwc->lock, flags);
1344 dwc->is_selfpowered = !!is_selfpowered;
1345 spin_unlock_irqrestore(&dwc->lock, flags);
1350 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1355 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1357 if (dwc->revision <= DWC3_REVISION_187A) {
1358 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1359 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1362 if (dwc->revision >= DWC3_REVISION_194A)
1363 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1364 reg |= DWC3_DCTL_RUN_STOP;
1366 if (dwc->has_hibernation)
1367 reg |= DWC3_DCTL_KEEP_CONNECT;
1369 dwc->pullups_connected = true;
1371 reg &= ~DWC3_DCTL_RUN_STOP;
1373 if (dwc->has_hibernation && !suspend)
1374 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1376 dwc->pullups_connected = false;
1379 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1382 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1384 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1387 if (reg & DWC3_DSTS_DEVCTRLHLT)
1396 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1398 ? dwc->gadget_driver->function : "no-function",
1399 is_on ? "connect" : "disconnect");
1404 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1406 struct dwc3 *dwc = gadget_to_dwc(g);
1407 unsigned long flags;
1412 spin_lock_irqsave(&dwc->lock, flags);
1413 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1414 spin_unlock_irqrestore(&dwc->lock, flags);
1419 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1423 /* Enable all but Start and End of Frame IRQs */
1424 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1425 DWC3_DEVTEN_EVNTOVERFLOWEN |
1426 DWC3_DEVTEN_CMDCMPLTEN |
1427 DWC3_DEVTEN_ERRTICERREN |
1428 DWC3_DEVTEN_WKUPEVTEN |
1429 DWC3_DEVTEN_ULSTCNGEN |
1430 DWC3_DEVTEN_CONNECTDONEEN |
1431 DWC3_DEVTEN_USBRSTEN |
1432 DWC3_DEVTEN_DISCONNEVTEN);
1434 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1437 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1439 /* mask all interrupts */
1440 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1443 static int dwc3_gadget_start(struct usb_gadget *g,
1444 struct usb_gadget_driver *driver)
1446 struct dwc3 *dwc = gadget_to_dwc(g);
1447 struct dwc3_ep *dep;
1448 unsigned long flags;
1452 spin_lock_irqsave(&dwc->lock, flags);
1454 if (dwc->gadget_driver) {
1455 dev_err(dwc->dev, "%s is already bound to %s\n",
1457 dwc->gadget_driver->function);
1462 dwc->gadget_driver = driver;
1464 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1465 reg &= ~(DWC3_DCFG_SPEED_MASK);
1468 * WORKAROUND: DWC3 revision < 2.20a have an issue
1469 * which would cause metastability state on Run/Stop
1470 * bit if we try to force the IP to USB2-only mode.
1472 * Because of that, we cannot configure the IP to any
1473 * speed other than the SuperSpeed
1477 * STAR#9000525659: Clock Domain Crossing on DCTL in
1480 if (dwc->revision < DWC3_REVISION_220A) {
1481 reg |= DWC3_DCFG_SUPERSPEED;
1483 switch (dwc->maximum_speed) {
1485 reg |= DWC3_DSTS_LOWSPEED;
1487 case USB_SPEED_FULL:
1488 reg |= DWC3_DSTS_FULLSPEED1;
1490 case USB_SPEED_HIGH:
1491 reg |= DWC3_DSTS_HIGHSPEED;
1493 case USB_SPEED_SUPER: /* FALLTHROUGH */
1494 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1496 reg |= DWC3_DSTS_SUPERSPEED;
1499 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1501 dwc->start_config_issued = false;
1503 /* Start with SuperSpeed Default */
1504 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1507 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1510 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1515 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1518 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1522 /* begin to receive SETUP packets */
1523 dwc->ep0state = EP0_SETUP_PHASE;
1524 dwc3_ep0_out_start(dwc);
1526 dwc3_gadget_enable_irq(dwc);
1528 spin_unlock_irqrestore(&dwc->lock, flags);
1533 __dwc3_gadget_ep_disable(dwc->eps[0]);
1536 dwc->gadget_driver = NULL;
1539 spin_unlock_irqrestore(&dwc->lock, flags);
1544 static int dwc3_gadget_stop(struct usb_gadget *g)
1546 struct dwc3 *dwc = gadget_to_dwc(g);
1547 unsigned long flags;
1549 spin_lock_irqsave(&dwc->lock, flags);
1551 dwc3_gadget_disable_irq(dwc);
1552 __dwc3_gadget_ep_disable(dwc->eps[0]);
1553 __dwc3_gadget_ep_disable(dwc->eps[1]);
1555 dwc->gadget_driver = NULL;
1557 spin_unlock_irqrestore(&dwc->lock, flags);
1562 static const struct usb_gadget_ops dwc3_gadget_ops = {
1563 .get_frame = dwc3_gadget_get_frame,
1564 .wakeup = dwc3_gadget_wakeup,
1565 .set_selfpowered = dwc3_gadget_set_selfpowered,
1566 .pullup = dwc3_gadget_pullup,
1567 .udc_start = dwc3_gadget_start,
1568 .udc_stop = dwc3_gadget_stop,
1571 /* -------------------------------------------------------------------------- */
1573 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1574 u8 num, u32 direction)
1576 struct dwc3_ep *dep;
1579 for (i = 0; i < num; i++) {
1580 u8 epnum = (i << 1) | (!!direction);
1582 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1587 dep->number = epnum;
1588 dep->direction = !!direction;
1589 dwc->eps[epnum] = dep;
1591 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1592 (epnum & 1) ? "in" : "out");
1594 dep->endpoint.name = dep->name;
1596 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1598 if (epnum == 0 || epnum == 1) {
1599 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1600 dep->endpoint.maxburst = 1;
1601 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1603 dwc->gadget.ep0 = &dep->endpoint;
1607 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1608 dep->endpoint.max_streams = 15;
1609 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1610 list_add_tail(&dep->endpoint.ep_list,
1611 &dwc->gadget.ep_list);
1613 ret = dwc3_alloc_trb_pool(dep);
1618 INIT_LIST_HEAD(&dep->request_list);
1619 INIT_LIST_HEAD(&dep->req_queued);
1625 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1629 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1631 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1633 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1637 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1639 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1646 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1648 struct dwc3_ep *dep;
1651 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1652 dep = dwc->eps[epnum];
1656 * Physical endpoints 0 and 1 are special; they form the
1657 * bi-directional USB endpoint 0.
1659 * For those two physical endpoints, we don't allocate a TRB
1660 * pool nor do we add them the endpoints list. Due to that, we
1661 * shouldn't do these two operations otherwise we would end up
1662 * with all sorts of bugs when removing dwc3.ko.
1664 if (epnum != 0 && epnum != 1) {
1665 dwc3_free_trb_pool(dep);
1666 list_del(&dep->endpoint.ep_list);
1673 /* -------------------------------------------------------------------------- */
1675 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1676 struct dwc3_request *req, struct dwc3_trb *trb,
1677 const struct dwc3_event_depevt *event, int status)
1680 unsigned int s_pkt = 0;
1681 unsigned int trb_status;
1683 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1685 * We continue despite the error. There is not much we
1686 * can do. If we don't clean it up we loop forever. If
1687 * we skip the TRB then it gets overwritten after a
1688 * while since we use them in a ring buffer. A BUG()
1689 * would help. Lets hope that if this occurs, someone
1690 * fixes the root cause instead of looking away :)
1692 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1694 count = trb->size & DWC3_TRB_SIZE_MASK;
1696 if (dep->direction) {
1698 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1699 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1700 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1703 * If missed isoc occurred and there is
1704 * no request queued then issue END
1705 * TRANSFER, so that core generates
1706 * next xfernotready and we will issue
1707 * a fresh START TRANSFER.
1708 * If there are still queued request
1709 * then wait, do not issue either END
1710 * or UPDATE TRANSFER, just attach next
1711 * request in request_list during
1712 * giveback.If any future queued request
1713 * is successfully transferred then we
1714 * will issue UPDATE TRANSFER for all
1715 * request in the request_list.
1717 dep->flags |= DWC3_EP_MISSED_ISOC;
1719 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1721 status = -ECONNRESET;
1724 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1727 if (count && (event->status & DEPEVT_STATUS_SHORT))
1732 * We assume here we will always receive the entire data block
1733 * which we should receive. Meaning, if we program RX to
1734 * receive 4K but we receive only 2K, we assume that's all we
1735 * should receive and we simply bounce the request back to the
1736 * gadget driver for further processing.
1738 req->request.actual += req->request.length - count;
1741 if ((event->status & DEPEVT_STATUS_LST) &&
1742 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1743 DWC3_TRB_CTRL_HWO)))
1745 if ((event->status & DEPEVT_STATUS_IOC) &&
1746 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1751 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1752 const struct dwc3_event_depevt *event, int status)
1754 struct dwc3_request *req;
1755 struct dwc3_trb *trb;
1760 req = next_request(&dep->req_queued);
1766 slot = req->start_slot;
1767 if ((slot == DWC3_TRB_NUM - 1) &&
1768 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1770 slot %= DWC3_TRB_NUM;
1771 trb = &dep->trb_pool[slot];
1773 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1778 dwc3_gadget_giveback(dep, req, status);
1784 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1785 list_empty(&dep->req_queued)) {
1786 if (list_empty(&dep->request_list)) {
1788 * If there is no entry in request list then do
1789 * not issue END TRANSFER now. Just set PENDING
1790 * flag, so that END TRANSFER is issued when an
1791 * entry is added into request list.
1793 dep->flags = DWC3_EP_PENDING_REQUEST;
1795 dwc3_stop_active_transfer(dwc, dep->number, true);
1796 dep->flags = DWC3_EP_ENABLED;
1804 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1805 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1807 unsigned status = 0;
1810 if (event->status & DEPEVT_STATUS_BUSERR)
1811 status = -ECONNRESET;
1813 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1815 dep->flags &= ~DWC3_EP_BUSY;
1818 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1819 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1821 if (dwc->revision < DWC3_REVISION_183A) {
1825 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1828 if (!(dep->flags & DWC3_EP_ENABLED))
1831 if (!list_empty(&dep->req_queued))
1835 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1837 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1843 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1844 const struct dwc3_event_depevt *event)
1846 struct dwc3_ep *dep;
1847 u8 epnum = event->endpoint_number;
1849 dep = dwc->eps[epnum];
1851 if (!(dep->flags & DWC3_EP_ENABLED))
1854 if (epnum == 0 || epnum == 1) {
1855 dwc3_ep0_interrupt(dwc, event);
1859 switch (event->endpoint_event) {
1860 case DWC3_DEPEVT_XFERCOMPLETE:
1861 dep->resource_index = 0;
1863 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1864 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1869 dwc3_endpoint_transfer_complete(dwc, dep, event);
1871 case DWC3_DEPEVT_XFERINPROGRESS:
1872 dwc3_endpoint_transfer_complete(dwc, dep, event);
1874 case DWC3_DEPEVT_XFERNOTREADY:
1875 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1876 dwc3_gadget_start_isoc(dwc, dep, event);
1880 dev_vdbg(dwc->dev, "%s: reason %s\n",
1881 dep->name, event->status &
1882 DEPEVT_STATUS_TRANSFER_ACTIVE
1884 : "Transfer Not Active");
1886 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1887 if (!ret || ret == -EBUSY)
1890 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1895 case DWC3_DEPEVT_STREAMEVT:
1896 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1897 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1902 switch (event->status) {
1903 case DEPEVT_STREAMEVT_FOUND:
1904 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1908 case DEPEVT_STREAMEVT_NOTFOUND:
1911 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1914 case DWC3_DEPEVT_RXTXFIFOEVT:
1915 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1917 case DWC3_DEPEVT_EPCMDCMPLT:
1918 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1923 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1925 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1926 spin_unlock(&dwc->lock);
1927 dwc->gadget_driver->disconnect(&dwc->gadget);
1928 spin_lock(&dwc->lock);
1932 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1934 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1935 spin_unlock(&dwc->lock);
1936 dwc->gadget_driver->suspend(&dwc->gadget);
1937 spin_lock(&dwc->lock);
1941 static void dwc3_resume_gadget(struct dwc3 *dwc)
1943 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1944 spin_unlock(&dwc->lock);
1945 dwc->gadget_driver->resume(&dwc->gadget);
1949 static void dwc3_reset_gadget(struct dwc3 *dwc)
1951 if (!dwc->gadget_driver)
1954 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1955 spin_unlock(&dwc->lock);
1956 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1957 spin_lock(&dwc->lock);
1961 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1963 struct dwc3_ep *dep;
1964 struct dwc3_gadget_ep_cmd_params params;
1968 dep = dwc->eps[epnum];
1970 if (!dep->resource_index)
1974 * NOTICE: We are violating what the Databook says about the
1975 * EndTransfer command. Ideally we would _always_ wait for the
1976 * EndTransfer Command Completion IRQ, but that's causing too
1977 * much trouble synchronizing between us and gadget driver.
1979 * We have discussed this with the IP Provider and it was
1980 * suggested to giveback all requests here, but give HW some
1981 * extra time to synchronize with the interconnect. We're using
1982 * an arbitraty 100us delay for that.
1984 * Note also that a similar handling was tested by Synopsys
1985 * (thanks a lot Paul) and nothing bad has come out of it.
1986 * In short, what we're doing is:
1988 * - Issue EndTransfer WITH CMDIOC bit set
1992 cmd = DWC3_DEPCMD_ENDTRANSFER;
1993 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1994 cmd |= DWC3_DEPCMD_CMDIOC;
1995 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1996 memset(¶ms, 0, sizeof(params));
1997 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1999 dep->resource_index = 0;
2000 dep->flags &= ~DWC3_EP_BUSY;
2004 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2008 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2009 struct dwc3_ep *dep;
2011 dep = dwc->eps[epnum];
2015 if (!(dep->flags & DWC3_EP_ENABLED))
2018 dwc3_remove_requests(dwc, dep);
2022 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2026 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2027 struct dwc3_ep *dep;
2028 struct dwc3_gadget_ep_cmd_params params;
2031 dep = dwc->eps[epnum];
2035 if (!(dep->flags & DWC3_EP_STALL))
2038 dep->flags &= ~DWC3_EP_STALL;
2040 memset(¶ms, 0, sizeof(params));
2041 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2042 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2047 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2051 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2052 reg &= ~DWC3_DCTL_INITU1ENA;
2053 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2055 reg &= ~DWC3_DCTL_INITU2ENA;
2056 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2058 dwc3_disconnect_gadget(dwc);
2059 dwc->start_config_issued = false;
2061 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2062 dwc->setup_packet_pending = false;
2063 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2066 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2071 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2072 * would cause a missing Disconnect Event if there's a
2073 * pending Setup Packet in the FIFO.
2075 * There's no suggested workaround on the official Bug
2076 * report, which states that "unless the driver/application
2077 * is doing any special handling of a disconnect event,
2078 * there is no functional issue".
2080 * Unfortunately, it turns out that we _do_ some special
2081 * handling of a disconnect event, namely complete all
2082 * pending transfers, notify gadget driver of the
2083 * disconnection, and so on.
2085 * Our suggested workaround is to follow the Disconnect
2086 * Event steps here, instead, based on a setup_packet_pending
2087 * flag. Such flag gets set whenever we have a XferNotReady
2088 * event on EP0 and gets cleared on XferComplete for the
2093 * STAR#9000466709: RTL: Device : Disconnect event not
2094 * generated if setup packet pending in FIFO
2096 if (dwc->revision < DWC3_REVISION_188A) {
2097 if (dwc->setup_packet_pending)
2098 dwc3_gadget_disconnect_interrupt(dwc);
2101 dwc3_reset_gadget(dwc);
2103 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2104 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2105 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2106 dwc->test_mode = false;
2108 dwc3_stop_active_transfers(dwc);
2109 dwc3_clear_stall_all_ep(dwc);
2110 dwc->start_config_issued = false;
2112 /* Reset device address to zero */
2113 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2114 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2115 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2118 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2121 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2124 * We change the clock only at SS but I dunno why I would want to do
2125 * this. Maybe it becomes part of the power saving plan.
2128 if (speed != DWC3_DSTS_SUPERSPEED)
2132 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2133 * each time on Connect Done.
2138 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2139 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2140 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2143 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2145 struct dwc3_ep *dep;
2150 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2151 speed = reg & DWC3_DSTS_CONNECTSPD;
2154 dwc3_update_ram_clk_sel(dwc, speed);
2157 case DWC3_DCFG_SUPERSPEED:
2159 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2160 * would cause a missing USB3 Reset event.
2162 * In such situations, we should force a USB3 Reset
2163 * event by calling our dwc3_gadget_reset_interrupt()
2168 * STAR#9000483510: RTL: SS : USB3 reset event may
2169 * not be generated always when the link enters poll
2171 if (dwc->revision < DWC3_REVISION_190A)
2172 dwc3_gadget_reset_interrupt(dwc);
2174 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2175 dwc->gadget.ep0->maxpacket = 512;
2176 dwc->gadget.speed = USB_SPEED_SUPER;
2178 case DWC3_DCFG_HIGHSPEED:
2179 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2180 dwc->gadget.ep0->maxpacket = 64;
2181 dwc->gadget.speed = USB_SPEED_HIGH;
2183 case DWC3_DCFG_FULLSPEED2:
2184 case DWC3_DCFG_FULLSPEED1:
2185 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2186 dwc->gadget.ep0->maxpacket = 64;
2187 dwc->gadget.speed = USB_SPEED_FULL;
2189 case DWC3_DCFG_LOWSPEED:
2190 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2191 dwc->gadget.ep0->maxpacket = 8;
2192 dwc->gadget.speed = USB_SPEED_LOW;
2196 /* Enable USB2 LPM Capability */
2198 if ((dwc->revision > DWC3_REVISION_194A)
2199 && (speed != DWC3_DCFG_SUPERSPEED)) {
2200 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2201 reg |= DWC3_DCFG_LPM_CAP;
2202 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2204 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2205 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2207 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2210 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2211 * DCFG.LPMCap is set, core responses with an ACK and the
2212 * BESL value in the LPM token is less than or equal to LPM
2215 if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum)
2216 WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2218 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2219 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2221 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2223 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2224 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2225 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2229 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2232 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2237 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2240 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2245 * Configure PHY via GUSB3PIPECTLn if required.
2247 * Update GTXFIFOSIZn
2249 * In both cases reset values should be sufficient.
2253 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2256 * TODO take core out of low power mode when that's
2260 dwc->gadget_driver->resume(&dwc->gadget);
2263 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2264 unsigned int evtinfo)
2266 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2267 unsigned int pwropt;
2270 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2271 * Hibernation mode enabled which would show up when device detects
2272 * host-initiated U3 exit.
2274 * In that case, device will generate a Link State Change Interrupt
2275 * from U3 to RESUME which is only necessary if Hibernation is
2278 * There are no functional changes due to such spurious event and we
2279 * just need to ignore it.
2283 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2286 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2287 if ((dwc->revision < DWC3_REVISION_250A) &&
2288 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2289 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2290 (next == DWC3_LINK_STATE_RESUME)) {
2291 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2297 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2298 * on the link partner, the USB session might do multiple entry/exit
2299 * of low power states before a transfer takes place.
2301 * Due to this problem, we might experience lower throughput. The
2302 * suggested workaround is to disable DCTL[12:9] bits if we're
2303 * transitioning from U1/U2 to U0 and enable those bits again
2304 * after a transfer completes and there are no pending transfers
2305 * on any of the enabled endpoints.
2307 * This is the first half of that workaround.
2311 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2312 * core send LGO_Ux entering U0
2314 if (dwc->revision < DWC3_REVISION_183A) {
2315 if (next == DWC3_LINK_STATE_U0) {
2319 switch (dwc->link_state) {
2320 case DWC3_LINK_STATE_U1:
2321 case DWC3_LINK_STATE_U2:
2322 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2323 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2324 | DWC3_DCTL_ACCEPTU2ENA
2325 | DWC3_DCTL_INITU1ENA
2326 | DWC3_DCTL_ACCEPTU1ENA);
2329 dwc->u1u2 = reg & u1u2;
2333 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2343 case DWC3_LINK_STATE_U1:
2344 if (dwc->speed == USB_SPEED_SUPER)
2345 dwc3_suspend_gadget(dwc);
2347 case DWC3_LINK_STATE_U2:
2348 case DWC3_LINK_STATE_U3:
2349 dwc3_suspend_gadget(dwc);
2351 case DWC3_LINK_STATE_RESUME:
2352 dwc3_resume_gadget(dwc);
2359 dwc->link_state = next;
2362 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2363 unsigned int evtinfo)
2365 unsigned int is_ss = evtinfo & BIT(4);
2368 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2369 * have a known issue which can cause USB CV TD.9.23 to fail
2372 * Because of this issue, core could generate bogus hibernation
2373 * events which SW needs to ignore.
2377 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2378 * Device Fallback from SuperSpeed
2380 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2383 /* enter hibernation here */
2386 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2387 const struct dwc3_event_devt *event)
2389 switch (event->type) {
2390 case DWC3_DEVICE_EVENT_DISCONNECT:
2391 dwc3_gadget_disconnect_interrupt(dwc);
2393 case DWC3_DEVICE_EVENT_RESET:
2394 dwc3_gadget_reset_interrupt(dwc);
2396 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2397 dwc3_gadget_conndone_interrupt(dwc);
2399 case DWC3_DEVICE_EVENT_WAKEUP:
2400 dwc3_gadget_wakeup_interrupt(dwc);
2402 case DWC3_DEVICE_EVENT_HIBER_REQ:
2403 if (!dwc->has_hibernation) {
2404 WARN(1 ,"unexpected hibernation event\n");
2407 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2409 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2410 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2412 case DWC3_DEVICE_EVENT_EOPF:
2413 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2415 case DWC3_DEVICE_EVENT_SOF:
2416 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2418 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2419 dev_vdbg(dwc->dev, "Erratic Error\n");
2421 case DWC3_DEVICE_EVENT_CMD_CMPL:
2422 dev_vdbg(dwc->dev, "Command Complete\n");
2424 case DWC3_DEVICE_EVENT_OVERFLOW:
2425 dev_vdbg(dwc->dev, "Overflow\n");
2428 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2432 static void dwc3_process_event_entry(struct dwc3 *dwc,
2433 const union dwc3_event *event)
2435 /* Endpoint IRQ, handle it and return early */
2436 if (event->type.is_devspec == 0) {
2438 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2441 switch (event->type.type) {
2442 case DWC3_EVENT_TYPE_DEV:
2443 dwc3_gadget_interrupt(dwc, &event->devt);
2445 /* REVISIT what to do with Carkit and I2C events ? */
2447 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2451 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2453 struct dwc3_event_buffer *evt;
2454 irqreturn_t ret = IRQ_NONE;
2458 evt = dwc->ev_buffs[buf];
2461 if (!(evt->flags & DWC3_EVENT_PENDING))
2465 union dwc3_event event;
2467 event.raw = *(u32 *) (evt->buf + evt->lpos);
2469 dwc3_process_event_entry(dwc, &event);
2472 * FIXME we wrap around correctly to the next entry as
2473 * almost all entries are 4 bytes in size. There is one
2474 * entry which has 12 bytes which is a regular entry
2475 * followed by 8 bytes data. ATM I don't know how
2476 * things are organized if we get next to the a
2477 * boundary so I worry about that once we try to handle
2480 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2483 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2487 evt->flags &= ~DWC3_EVENT_PENDING;
2490 /* Unmask interrupt */
2491 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2492 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2493 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2498 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2500 struct dwc3 *dwc = _dwc;
2501 unsigned long flags;
2502 irqreturn_t ret = IRQ_NONE;
2505 spin_lock_irqsave(&dwc->lock, flags);
2507 for (i = 0; i < dwc->num_event_buffers; i++)
2508 ret |= dwc3_process_event_buf(dwc, i);
2510 spin_unlock_irqrestore(&dwc->lock, flags);
2515 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2517 struct dwc3_event_buffer *evt;
2521 evt = dwc->ev_buffs[buf];
2523 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2524 count &= DWC3_GEVNTCOUNT_MASK;
2529 evt->flags |= DWC3_EVENT_PENDING;
2531 /* Mask interrupt */
2532 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2533 reg |= DWC3_GEVNTSIZ_INTMASK;
2534 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2536 return IRQ_WAKE_THREAD;
2539 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2541 struct dwc3 *dwc = _dwc;
2543 irqreturn_t ret = IRQ_NONE;
2545 spin_lock(&dwc->lock);
2547 for (i = 0; i < dwc->num_event_buffers; i++) {
2550 status = dwc3_check_event_buf(dwc, i);
2551 if (status == IRQ_WAKE_THREAD)
2555 spin_unlock(&dwc->lock);
2561 * dwc3_gadget_init - Initializes gadget related registers
2562 * @dwc: pointer to our controller context structure
2564 * Returns 0 on success otherwise negative errno.
2566 int dwc3_gadget_init(struct dwc3 *dwc)
2570 dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2571 (unsigned long *)&dwc->ctrl_req_addr);
2572 if (!dwc->ctrl_req) {
2573 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2578 dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb),
2579 (unsigned long *)&dwc->ep0_trb_addr);
2580 if (!dwc->ep0_trb) {
2581 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2586 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2587 if (!dwc->setup_buf) {
2592 dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2593 (unsigned long *)&dwc->ep0_bounce_addr);
2594 if (!dwc->ep0_bounce) {
2595 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2600 dwc->gadget.ops = &dwc3_gadget_ops;
2601 dwc->gadget.max_speed = USB_SPEED_SUPER;
2602 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2603 dwc->gadget.name = "dwc3-gadget";
2606 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2609 dwc->gadget.quirk_ep_out_aligned_size = true;
2612 * REVISIT: Here we should clear all pending IRQs to be
2613 * sure we're starting from a well known location.
2616 ret = dwc3_gadget_init_endpoints(dwc);
2620 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2622 dev_err(dwc->dev, "failed to register udc\n");
2629 dwc3_gadget_free_endpoints(dwc);
2630 dma_free_coherent(dwc->ep0_bounce);
2633 kfree(dwc->setup_buf);
2636 dma_free_coherent(dwc->ep0_trb);
2639 dma_free_coherent(dwc->ctrl_req);
2645 /* -------------------------------------------------------------------------- */
2647 void dwc3_gadget_exit(struct dwc3 *dwc)
2649 usb_del_gadget_udc(&dwc->gadget);
2651 dwc3_gadget_free_endpoints(dwc);
2653 dma_free_coherent(dwc->ep0_bounce);
2655 kfree(dwc->setup_buf);
2657 dma_free_coherent(dwc->ep0_trb);
2659 dma_free_coherent(dwc->ctrl_req);
2663 * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2664 * @dwc: struct dwce *
2666 * Handles ep0 and gadget interrupt
2668 * Should be called from dwc3 core.
2670 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2672 dwc3_interrupt(0, dwc);
2673 dwc3_thread_interrupt(0, dwc);