2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
12 * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
14 * SPDX-License-Identifier: GPL-2.0
19 #include <asm/dma-mapping.h>
20 #include <usb/lin_gadget_compat.h>
21 #include <linux/list.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/gadget.h>
25 #include <asm/arch/sys_proto.h>
31 #include "linux-compat.h"
34 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will
39 * return 0 on success or -EINVAL if wrong Test Selector
42 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
46 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
47 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
61 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67 * dwc3_gadget_get_link_state - Gets current state of USB Link
68 * @dwc: pointer to our context structure
70 * Caller should take care of locking. This function will
71 * return the link state on success (>= 0) or -ETIMEDOUT.
73 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
77 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
79 return DWC3_DSTS_USBLNKST(reg);
83 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
84 * @dwc: pointer to our context structure
85 * @state: the state to put link into
87 * Caller should take care of locking. This function will
88 * return 0 on success or -ETIMEDOUT.
90 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96 * Wait until device controller is ready. Only applies to 1.94a and
99 if (dwc->revision >= DWC3_REVISION_194A) {
101 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
102 if (reg & DWC3_DSTS_DCNRD)
112 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
113 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
115 /* set requested state */
116 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
117 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
120 * The following code is racy when called from dwc3_gadget_wakeup,
121 * and is not needed, at least on newer versions
123 if (dwc->revision >= DWC3_REVISION_194A)
126 /* wait for a change in DSTS */
129 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
131 if (DWC3_DSTS_USBLNKST(reg) == state)
137 dev_vdbg(dwc->dev, "link state change request timed out\n");
143 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
144 * @dwc: pointer to our context structure
146 * This function will a best effort FIFO allocation in order
147 * to improve FIFO usage and throughput, while still allowing
148 * us to enable as many endpoints as possible.
150 * Keep in mind that this operation will be highly dependent
151 * on the configured size for RAM1 - which contains TxFifo -,
152 * the amount of endpoints enabled on coreConsultant tool, and
153 * the width of the Master Bus.
155 * In the ideal world, we would always be able to satisfy the
156 * following equation:
158 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
159 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
161 * Unfortunately, due to many variables that's not always the case.
163 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
165 int last_fifo_depth = 0;
170 if (!dwc->needs_fifo_resize)
173 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
175 /* MDWIDTH is represented in bits, we need it in bytes */
179 * FIXME For now we will only allocate 1 wMaxPacketSize space
180 * for each enabled endpoint, later patches will come to
181 * improve this algorithm so that we better use the internal
184 for (num = 0; num < dwc->num_in_eps; num++) {
185 /* bit0 indicates direction; 1 means IN ep */
186 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
190 if (!(dep->flags & DWC3_EP_ENABLED))
193 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
194 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
198 * REVISIT: the following assumes we will always have enough
199 * space available on the FIFO RAM for all possible use cases.
200 * Make sure that's true somehow and change FIFO allocation
203 * If we have Bulk or Isochronous endpoints, we want
204 * them to be able to be very, very fast. So we're giving
205 * those endpoints a fifo_size which is enough for 3 full
208 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
211 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
213 fifo_size |= (last_fifo_depth << 16);
215 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
216 dep->name, last_fifo_depth, fifo_size & 0xffff);
218 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
220 last_fifo_depth += (fifo_size & 0xffff);
226 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
229 struct dwc3 *dwc = dep->dwc;
234 * Skip LINK TRB. We can't use req->trb and check for
235 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
236 * just completed (not the LINK TRB).
238 if (((dep->busy_slot & DWC3_TRB_MASK) ==
240 usb_endpoint_xfer_isoc(dep->endpoint.desc))
245 list_del(&req->list);
247 dwc3_flush_cache((int)req->request.dma, req->request.length);
249 if (req->request.status == -EINPROGRESS)
250 req->request.status = status;
252 if (dwc->ep0_bounced && dep->number == 0)
253 dwc->ep0_bounced = false;
255 usb_gadget_unmap_request(&dwc->gadget, &req->request,
258 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
259 req, dep->name, req->request.actual,
260 req->request.length, status);
262 spin_unlock(&dwc->lock);
263 usb_gadget_giveback_request(&dep->endpoint, &req->request);
264 spin_lock(&dwc->lock);
267 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
272 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
273 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
276 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
277 if (!(reg & DWC3_DGCMD_CMDACT)) {
278 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
279 DWC3_DGCMD_STATUS(reg));
284 * We can't sleep here, because it's also called from
294 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
295 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
300 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
301 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
302 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
304 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
306 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
307 if (!(reg & DWC3_DEPCMD_CMDACT)) {
308 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
309 DWC3_DEPCMD_STATUS(reg));
314 * We can't sleep here, because it is also called from
325 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
326 struct dwc3_trb *trb)
328 u32 offset = (char *) trb - (char *) dep->trb_pool;
330 return dep->trb_pool_dma + offset;
333 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
338 if (dep->number == 0 || dep->number == 1)
341 dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
343 (unsigned long *)&dep->trb_pool_dma);
344 if (!dep->trb_pool) {
345 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
353 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
355 dma_free_coherent(dep->trb_pool);
357 dep->trb_pool = NULL;
358 dep->trb_pool_dma = 0;
361 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
363 struct dwc3_gadget_ep_cmd_params params;
366 memset(¶ms, 0x00, sizeof(params));
368 if (dep->number != 1) {
369 cmd = DWC3_DEPCMD_DEPSTARTCFG;
370 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
371 if (dep->number > 1) {
372 if (dwc->start_config_issued)
374 dwc->start_config_issued = true;
375 cmd |= DWC3_DEPCMD_PARAM(2);
378 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
384 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
385 const struct usb_endpoint_descriptor *desc,
386 const struct usb_ss_ep_comp_descriptor *comp_desc,
387 bool ignore, bool restore)
389 struct dwc3_gadget_ep_cmd_params params;
391 memset(¶ms, 0x00, sizeof(params));
393 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
394 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
396 /* Burst size is only needed in SuperSpeed mode */
397 if (dwc->gadget.speed == USB_SPEED_SUPER) {
398 u32 burst = dep->endpoint.maxburst - 1;
400 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
404 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
407 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
408 params.param2 |= dep->saved_state;
411 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
412 | DWC3_DEPCFG_XFER_NOT_READY_EN;
414 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
415 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
416 | DWC3_DEPCFG_STREAM_EVENT_EN;
417 dep->stream_capable = true;
420 if (!usb_endpoint_xfer_control(desc))
421 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
424 * We are doing 1:1 mapping for endpoints, meaning
425 * Physical Endpoints 2 maps to Logical Endpoint 2 and
426 * so on. We consider the direction bit as part of the physical
427 * endpoint number. So USB endpoint 0x81 is 0x03.
429 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
432 * We must use the lower 16 TX FIFOs even though
436 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
438 if (desc->bInterval) {
439 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
440 dep->interval = 1 << (desc->bInterval - 1);
443 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
444 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
447 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
449 struct dwc3_gadget_ep_cmd_params params;
451 memset(¶ms, 0x00, sizeof(params));
453 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
455 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
456 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
460 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
461 * @dep: endpoint to be initialized
462 * @desc: USB Endpoint Descriptor
464 * Caller should take care of locking
466 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
467 const struct usb_endpoint_descriptor *desc,
468 const struct usb_ss_ep_comp_descriptor *comp_desc,
469 bool ignore, bool restore)
471 struct dwc3 *dwc = dep->dwc;
475 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
477 if (!(dep->flags & DWC3_EP_ENABLED)) {
478 ret = dwc3_gadget_start_config(dwc, dep);
483 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
488 if (!(dep->flags & DWC3_EP_ENABLED)) {
489 struct dwc3_trb *trb_st_hw;
490 struct dwc3_trb *trb_link;
492 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
496 dep->endpoint.desc = desc;
497 dep->comp_desc = comp_desc;
498 dep->type = usb_endpoint_type(desc);
499 dep->flags |= DWC3_EP_ENABLED;
501 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
502 reg |= DWC3_DALEPENA_EP(dep->number);
503 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
505 if (!usb_endpoint_xfer_isoc(desc))
508 /* Link TRB for ISOC. The HWO bit is never reset */
509 trb_st_hw = &dep->trb_pool[0];
511 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
512 memset(trb_link, 0, sizeof(*trb_link));
514 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
515 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
516 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
517 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
523 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
524 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
526 struct dwc3_request *req;
528 if (!list_empty(&dep->req_queued)) {
529 dwc3_stop_active_transfer(dwc, dep->number, true);
531 /* - giveback all requests to gadget driver */
532 while (!list_empty(&dep->req_queued)) {
533 req = next_request(&dep->req_queued);
535 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
539 while (!list_empty(&dep->request_list)) {
540 req = next_request(&dep->request_list);
542 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
547 * __dwc3_gadget_ep_disable - Disables a HW endpoint
548 * @dep: the endpoint to disable
550 * This function also removes requests which are currently processed ny the
551 * hardware and those which are not yet scheduled.
552 * Caller should take care of locking.
554 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
556 struct dwc3 *dwc = dep->dwc;
559 dwc3_remove_requests(dwc, dep);
561 /* make sure HW endpoint isn't stalled */
562 if (dep->flags & DWC3_EP_STALL)
563 __dwc3_gadget_ep_set_halt(dep, 0, false);
565 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
566 reg &= ~DWC3_DALEPENA_EP(dep->number);
567 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
569 dep->stream_capable = false;
570 dep->endpoint.desc = NULL;
571 dep->comp_desc = NULL;
578 /* -------------------------------------------------------------------------- */
580 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
581 const struct usb_endpoint_descriptor *desc)
586 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
591 /* -------------------------------------------------------------------------- */
593 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
594 const struct usb_endpoint_descriptor *desc)
600 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
601 pr_debug("dwc3: invalid parameters\n");
605 if (!desc->wMaxPacketSize) {
606 pr_debug("dwc3: missing wMaxPacketSize\n");
610 dep = to_dwc3_ep(ep);
612 if (dep->flags & DWC3_EP_ENABLED) {
613 WARN(true, "%s is already enabled\n",
618 switch (usb_endpoint_type(desc)) {
619 case USB_ENDPOINT_XFER_CONTROL:
620 strlcat(dep->name, "-control", sizeof(dep->name));
622 case USB_ENDPOINT_XFER_ISOC:
623 strlcat(dep->name, "-isoc", sizeof(dep->name));
625 case USB_ENDPOINT_XFER_BULK:
626 strlcat(dep->name, "-bulk", sizeof(dep->name));
628 case USB_ENDPOINT_XFER_INT:
629 strlcat(dep->name, "-int", sizeof(dep->name));
632 dev_err(dwc->dev, "invalid endpoint transfer type\n");
635 spin_lock_irqsave(&dwc->lock, flags);
636 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
637 spin_unlock_irqrestore(&dwc->lock, flags);
642 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
649 pr_debug("dwc3: invalid parameters\n");
653 dep = to_dwc3_ep(ep);
655 if (!(dep->flags & DWC3_EP_ENABLED)) {
656 WARN(true, "%s is already disabled\n",
661 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
663 (dep->number & 1) ? "in" : "out");
665 spin_lock_irqsave(&dwc->lock, flags);
666 ret = __dwc3_gadget_ep_disable(dep);
667 spin_unlock_irqrestore(&dwc->lock, flags);
672 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
675 struct dwc3_request *req;
676 struct dwc3_ep *dep = to_dwc3_ep(ep);
678 req = kzalloc(sizeof(*req), gfp_flags);
682 req->epnum = dep->number;
685 return &req->request;
688 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
689 struct usb_request *request)
691 struct dwc3_request *req = to_dwc3_request(request);
697 * dwc3_prepare_one_trb - setup one TRB from one request
698 * @dep: endpoint for which this request is prepared
699 * @req: dwc3_request pointer
701 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
702 struct dwc3_request *req, dma_addr_t dma,
703 unsigned length, unsigned last, unsigned chain, unsigned node)
705 struct dwc3_trb *trb;
707 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
708 dep->name, req, (unsigned long long) dma,
709 length, last ? " last" : "",
710 chain ? " chain" : "");
713 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
716 dwc3_gadget_move_request_queued(req);
718 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
719 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
723 /* Skip the LINK-TRB on ISOC */
724 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
725 usb_endpoint_xfer_isoc(dep->endpoint.desc))
728 trb->size = DWC3_TRB_SIZE_LENGTH(length);
729 trb->bpl = lower_32_bits(dma);
730 trb->bph = upper_32_bits(dma);
732 switch (usb_endpoint_type(dep->endpoint.desc)) {
733 case USB_ENDPOINT_XFER_CONTROL:
734 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
737 case USB_ENDPOINT_XFER_ISOC:
739 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
741 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
744 case USB_ENDPOINT_XFER_BULK:
745 case USB_ENDPOINT_XFER_INT:
746 trb->ctrl = DWC3_TRBCTL_NORMAL;
750 * This is only possible with faulty memory because we
751 * checked it already :)
756 if (!req->request.no_interrupt && !chain)
757 trb->ctrl |= DWC3_TRB_CTRL_IOC;
759 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
760 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
761 trb->ctrl |= DWC3_TRB_CTRL_CSP;
763 trb->ctrl |= DWC3_TRB_CTRL_LST;
767 trb->ctrl |= DWC3_TRB_CTRL_CHN;
769 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
770 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
772 trb->ctrl |= DWC3_TRB_CTRL_HWO;
774 dwc3_flush_cache((int)dma, length);
775 dwc3_flush_cache((int)trb, sizeof(*trb));
779 * dwc3_prepare_trbs - setup TRBs from requests
780 * @dep: endpoint for which requests are being prepared
781 * @starting: true if the endpoint is idle and no requests are queued.
783 * The function goes through the requests list and sets up TRBs for the
784 * transfers. The function returns once there are no more TRBs available or
785 * it runs out of requests.
787 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
789 struct dwc3_request *req, *n;
792 unsigned int last_one = 0;
794 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
796 /* the first request must not be queued */
797 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
799 /* Can't wrap around on a non-isoc EP since there's no link TRB */
800 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
801 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
807 * If busy & slot are equal than it is either full or empty. If we are
808 * starting to process requests then we are empty. Otherwise we are
809 * full and don't do anything
814 trbs_left = DWC3_TRB_NUM;
816 * In case we start from scratch, we queue the ISOC requests
817 * starting from slot 1. This is done because we use ring
818 * buffer and have no LST bit to stop us. Instead, we place
819 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
820 * after the first request so we start at slot 1 and have
821 * 7 requests proceed before we hit the first IOC.
822 * Other transfer types don't use the ring buffer and are
823 * processed from the first TRB until the last one. Since we
824 * don't wrap around we have to start at the beginning.
826 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
835 /* The last TRB is a link TRB, not used for xfer */
836 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
839 list_for_each_entry_safe(req, n, &dep->request_list, list) {
844 dma = req->request.dma;
845 length = req->request.length;
851 /* Is this the last request? */
852 if (list_is_last(&req->list, &dep->request_list))
855 dwc3_prepare_one_trb(dep, req, dma, length,
863 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
866 struct dwc3_gadget_ep_cmd_params params;
867 struct dwc3_request *req;
868 struct dwc3 *dwc = dep->dwc;
872 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
873 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
876 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
879 * If we are getting here after a short-out-packet we don't enqueue any
880 * new requests as we try to set the IOC bit only on the last request.
883 if (list_empty(&dep->req_queued))
884 dwc3_prepare_trbs(dep, start_new);
886 /* req points to the first request which will be sent */
887 req = next_request(&dep->req_queued);
889 dwc3_prepare_trbs(dep, start_new);
892 * req points to the first request where HWO changed from 0 to 1
894 req = next_request(&dep->req_queued);
897 dep->flags |= DWC3_EP_PENDING_REQUEST;
901 memset(¶ms, 0, sizeof(params));
904 params.param0 = upper_32_bits(req->trb_dma);
905 params.param1 = lower_32_bits(req->trb_dma);
906 cmd = DWC3_DEPCMD_STARTTRANSFER;
908 cmd = DWC3_DEPCMD_UPDATETRANSFER;
911 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
912 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
914 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
917 * FIXME we need to iterate over the list of requests
918 * here and stop, unmap, free and del each of the linked
919 * requests instead of what we do now.
921 usb_gadget_unmap_request(&dwc->gadget, &req->request,
923 list_del(&req->list);
927 dep->flags |= DWC3_EP_BUSY;
930 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
932 WARN_ON_ONCE(!dep->resource_index);
938 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
939 struct dwc3_ep *dep, u32 cur_uf)
943 if (list_empty(&dep->request_list)) {
944 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
946 dep->flags |= DWC3_EP_PENDING_REQUEST;
950 /* 4 micro frames in the future */
951 uf = cur_uf + dep->interval * 4;
953 __dwc3_gadget_kick_transfer(dep, uf, 1);
956 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
957 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
961 mask = ~(dep->interval - 1);
962 cur_uf = event->parameters & mask;
964 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
967 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
969 struct dwc3 *dwc = dep->dwc;
972 req->request.actual = 0;
973 req->request.status = -EINPROGRESS;
974 req->direction = dep->direction;
975 req->epnum = dep->number;
978 * We only add to our list of requests now and
979 * start consuming the list once we get XferNotReady
982 * That way, we avoid doing anything that we don't need
983 * to do now and defer it until the point we receive a
984 * particular token from the Host side.
986 * This will also avoid Host cancelling URBs due to too
989 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
994 list_add_tail(&req->list, &dep->request_list);
997 * There are a few special cases:
999 * 1. XferNotReady with empty list of requests. We need to kick the
1000 * transfer here in that situation, otherwise we will be NAKing
1001 * forever. If we get XferNotReady before gadget driver has a
1002 * chance to queue a request, we will ACK the IRQ but won't be
1003 * able to receive the data until the next request is queued.
1004 * The following code is handling exactly that.
1007 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1009 * If xfernotready is already elapsed and it is a case
1010 * of isoc transfer, then issue END TRANSFER, so that
1011 * you can receive xfernotready again and can have
1012 * notion of current microframe.
1014 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1015 if (list_empty(&dep->req_queued)) {
1016 dwc3_stop_active_transfer(dwc, dep->number, true);
1017 dep->flags = DWC3_EP_ENABLED;
1022 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1023 if (ret && ret != -EBUSY)
1024 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1030 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1031 * kick the transfer here after queuing a request, otherwise the
1032 * core may not see the modified TRB(s).
1034 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1035 (dep->flags & DWC3_EP_BUSY) &&
1036 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1037 WARN_ON_ONCE(!dep->resource_index);
1038 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1040 if (ret && ret != -EBUSY)
1041 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1047 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1048 * right away, otherwise host will not know we have streams to be
1051 if (dep->stream_capable) {
1054 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1055 if (ret && ret != -EBUSY) {
1056 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1064 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1067 struct dwc3_request *req = to_dwc3_request(request);
1068 struct dwc3_ep *dep = to_dwc3_ep(ep);
1070 unsigned long flags;
1074 spin_lock_irqsave(&dwc->lock, flags);
1075 if (!dep->endpoint.desc) {
1076 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1082 if (req->dep != dep) {
1083 WARN(true, "request %p belongs to '%s'\n",
1084 request, req->dep->name);
1089 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1090 request, ep->name, request->length);
1092 ret = __dwc3_gadget_ep_queue(dep, req);
1095 spin_unlock_irqrestore(&dwc->lock, flags);
1100 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1101 struct usb_request *request)
1103 struct dwc3_request *req = to_dwc3_request(request);
1104 struct dwc3_request *r = NULL;
1106 struct dwc3_ep *dep = to_dwc3_ep(ep);
1107 struct dwc3 *dwc = dep->dwc;
1109 unsigned long flags;
1112 spin_lock_irqsave(&dwc->lock, flags);
1114 list_for_each_entry(r, &dep->request_list, list) {
1120 list_for_each_entry(r, &dep->req_queued, list) {
1125 /* wait until it is processed */
1126 dwc3_stop_active_transfer(dwc, dep->number, true);
1129 dev_err(dwc->dev, "request %p was not queued to %s\n",
1136 /* giveback the request */
1137 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1140 spin_unlock_irqrestore(&dwc->lock, flags);
1145 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1147 struct dwc3_gadget_ep_cmd_params params;
1148 struct dwc3 *dwc = dep->dwc;
1151 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1152 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1156 memset(¶ms, 0x00, sizeof(params));
1159 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1160 (!list_empty(&dep->req_queued) ||
1161 !list_empty(&dep->request_list)))) {
1162 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1167 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1168 DWC3_DEPCMD_SETSTALL, ¶ms);
1170 dev_err(dwc->dev, "failed to set STALL on %s\n",
1173 dep->flags |= DWC3_EP_STALL;
1175 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1176 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1178 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1181 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1187 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1189 struct dwc3_ep *dep = to_dwc3_ep(ep);
1191 unsigned long flags;
1195 spin_lock_irqsave(&dwc->lock, flags);
1196 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1197 spin_unlock_irqrestore(&dwc->lock, flags);
1202 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1204 struct dwc3_ep *dep = to_dwc3_ep(ep);
1205 unsigned long flags;
1208 spin_lock_irqsave(&dwc->lock, flags);
1209 dep->flags |= DWC3_EP_WEDGE;
1211 if (dep->number == 0 || dep->number == 1)
1212 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1214 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1215 spin_unlock_irqrestore(&dwc->lock, flags);
1220 /* -------------------------------------------------------------------------- */
1222 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1223 .bLength = USB_DT_ENDPOINT_SIZE,
1224 .bDescriptorType = USB_DT_ENDPOINT,
1225 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1228 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1229 .enable = dwc3_gadget_ep0_enable,
1230 .disable = dwc3_gadget_ep0_disable,
1231 .alloc_request = dwc3_gadget_ep_alloc_request,
1232 .free_request = dwc3_gadget_ep_free_request,
1233 .queue = dwc3_gadget_ep0_queue,
1234 .dequeue = dwc3_gadget_ep_dequeue,
1235 .set_halt = dwc3_gadget_ep0_set_halt,
1236 .set_wedge = dwc3_gadget_ep_set_wedge,
1239 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1240 .enable = dwc3_gadget_ep_enable,
1241 .disable = dwc3_gadget_ep_disable,
1242 .alloc_request = dwc3_gadget_ep_alloc_request,
1243 .free_request = dwc3_gadget_ep_free_request,
1244 .queue = dwc3_gadget_ep_queue,
1245 .dequeue = dwc3_gadget_ep_dequeue,
1246 .set_halt = dwc3_gadget_ep_set_halt,
1247 .set_wedge = dwc3_gadget_ep_set_wedge,
1250 /* -------------------------------------------------------------------------- */
1252 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1254 struct dwc3 *dwc = gadget_to_dwc(g);
1257 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1258 return DWC3_DSTS_SOFFN(reg);
1261 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1263 struct dwc3 *dwc = gadget_to_dwc(g);
1265 unsigned long timeout;
1266 unsigned long flags;
1275 spin_lock_irqsave(&dwc->lock, flags);
1278 * According to the Databook Remote wakeup request should
1279 * be issued only when the device is in early suspend state.
1281 * We can check that via USB Link State bits in DSTS register.
1283 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1285 speed = reg & DWC3_DSTS_CONNECTSPD;
1286 if (speed == DWC3_DSTS_SUPERSPEED) {
1287 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1292 link_state = DWC3_DSTS_USBLNKST(reg);
1294 switch (link_state) {
1295 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1296 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1299 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1305 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1307 dev_err(dwc->dev, "failed to put link in Recovery\n");
1311 /* Recent versions do this automatically */
1312 if (dwc->revision < DWC3_REVISION_194A) {
1313 /* write zeroes to Link Change Request */
1314 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1315 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1316 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1319 /* poll until Link State changes to ON */
1323 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1325 /* in HS, means ON */
1326 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1330 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1331 dev_err(dwc->dev, "failed to send remote wakeup\n");
1336 spin_unlock_irqrestore(&dwc->lock, flags);
1341 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1344 struct dwc3 *dwc = gadget_to_dwc(g);
1345 unsigned long flags;
1347 spin_lock_irqsave(&dwc->lock, flags);
1348 dwc->is_selfpowered = !!is_selfpowered;
1349 spin_unlock_irqrestore(&dwc->lock, flags);
1354 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1359 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1361 if (dwc->revision <= DWC3_REVISION_187A) {
1362 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1363 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1366 if (dwc->revision >= DWC3_REVISION_194A)
1367 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1368 reg |= DWC3_DCTL_RUN_STOP;
1370 if (dwc->has_hibernation)
1371 reg |= DWC3_DCTL_KEEP_CONNECT;
1373 dwc->pullups_connected = true;
1375 reg &= ~DWC3_DCTL_RUN_STOP;
1377 if (dwc->has_hibernation && !suspend)
1378 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1380 dwc->pullups_connected = false;
1383 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1386 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1388 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1391 if (reg & DWC3_DSTS_DEVCTRLHLT)
1400 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1402 ? dwc->gadget_driver->function : "no-function",
1403 is_on ? "connect" : "disconnect");
1408 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1410 struct dwc3 *dwc = gadget_to_dwc(g);
1411 unsigned long flags;
1416 spin_lock_irqsave(&dwc->lock, flags);
1417 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1418 spin_unlock_irqrestore(&dwc->lock, flags);
1423 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1427 /* Enable all but Start and End of Frame IRQs */
1428 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1429 DWC3_DEVTEN_EVNTOVERFLOWEN |
1430 DWC3_DEVTEN_CMDCMPLTEN |
1431 DWC3_DEVTEN_ERRTICERREN |
1432 DWC3_DEVTEN_WKUPEVTEN |
1433 DWC3_DEVTEN_ULSTCNGEN |
1434 DWC3_DEVTEN_CONNECTDONEEN |
1435 DWC3_DEVTEN_USBRSTEN |
1436 DWC3_DEVTEN_DISCONNEVTEN);
1438 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1441 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1443 /* mask all interrupts */
1444 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1447 static int dwc3_gadget_start(struct usb_gadget *g,
1448 struct usb_gadget_driver *driver)
1450 struct dwc3 *dwc = gadget_to_dwc(g);
1451 struct dwc3_ep *dep;
1452 unsigned long flags;
1456 spin_lock_irqsave(&dwc->lock, flags);
1458 if (dwc->gadget_driver) {
1459 dev_err(dwc->dev, "%s is already bound to %s\n",
1461 dwc->gadget_driver->function);
1466 dwc->gadget_driver = driver;
1468 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1469 reg &= ~(DWC3_DCFG_SPEED_MASK);
1472 * WORKAROUND: DWC3 revision < 2.20a have an issue
1473 * which would cause metastability state on Run/Stop
1474 * bit if we try to force the IP to USB2-only mode.
1476 * Because of that, we cannot configure the IP to any
1477 * speed other than the SuperSpeed
1481 * STAR#9000525659: Clock Domain Crossing on DCTL in
1484 if (dwc->revision < DWC3_REVISION_220A) {
1485 reg |= DWC3_DCFG_SUPERSPEED;
1487 switch (dwc->maximum_speed) {
1489 reg |= DWC3_DSTS_LOWSPEED;
1491 case USB_SPEED_FULL:
1492 reg |= DWC3_DSTS_FULLSPEED1;
1494 case USB_SPEED_HIGH:
1495 reg |= DWC3_DSTS_HIGHSPEED;
1497 case USB_SPEED_SUPER: /* FALLTHROUGH */
1498 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1500 reg |= DWC3_DSTS_SUPERSPEED;
1503 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1505 dwc->start_config_issued = false;
1507 /* Start with SuperSpeed Default */
1508 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1511 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1514 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1519 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1522 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1526 /* begin to receive SETUP packets */
1527 dwc->ep0state = EP0_SETUP_PHASE;
1528 dwc3_ep0_out_start(dwc);
1530 dwc3_gadget_enable_irq(dwc);
1532 spin_unlock_irqrestore(&dwc->lock, flags);
1537 __dwc3_gadget_ep_disable(dwc->eps[0]);
1540 dwc->gadget_driver = NULL;
1543 spin_unlock_irqrestore(&dwc->lock, flags);
1548 static int dwc3_gadget_stop(struct usb_gadget *g)
1550 struct dwc3 *dwc = gadget_to_dwc(g);
1551 unsigned long flags;
1553 spin_lock_irqsave(&dwc->lock, flags);
1555 dwc3_gadget_disable_irq(dwc);
1556 __dwc3_gadget_ep_disable(dwc->eps[0]);
1557 __dwc3_gadget_ep_disable(dwc->eps[1]);
1559 dwc->gadget_driver = NULL;
1561 spin_unlock_irqrestore(&dwc->lock, flags);
1566 static const struct usb_gadget_ops dwc3_gadget_ops = {
1567 .get_frame = dwc3_gadget_get_frame,
1568 .wakeup = dwc3_gadget_wakeup,
1569 .set_selfpowered = dwc3_gadget_set_selfpowered,
1570 .pullup = dwc3_gadget_pullup,
1571 .udc_start = dwc3_gadget_start,
1572 .udc_stop = dwc3_gadget_stop,
1575 /* -------------------------------------------------------------------------- */
1577 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1578 u8 num, u32 direction)
1580 struct dwc3_ep *dep;
1583 for (i = 0; i < num; i++) {
1584 u8 epnum = (i << 1) | (!!direction);
1586 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1591 dep->number = epnum;
1592 dep->direction = !!direction;
1593 dwc->eps[epnum] = dep;
1595 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1596 (epnum & 1) ? "in" : "out");
1598 dep->endpoint.name = dep->name;
1600 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1602 if (epnum == 0 || epnum == 1) {
1603 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1604 dep->endpoint.maxburst = 1;
1605 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1607 dwc->gadget.ep0 = &dep->endpoint;
1611 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1612 dep->endpoint.max_streams = 15;
1613 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1614 list_add_tail(&dep->endpoint.ep_list,
1615 &dwc->gadget.ep_list);
1617 ret = dwc3_alloc_trb_pool(dep);
1622 INIT_LIST_HEAD(&dep->request_list);
1623 INIT_LIST_HEAD(&dep->req_queued);
1629 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1633 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1635 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1637 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1641 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1643 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1650 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1652 struct dwc3_ep *dep;
1655 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1656 dep = dwc->eps[epnum];
1660 * Physical endpoints 0 and 1 are special; they form the
1661 * bi-directional USB endpoint 0.
1663 * For those two physical endpoints, we don't allocate a TRB
1664 * pool nor do we add them the endpoints list. Due to that, we
1665 * shouldn't do these two operations otherwise we would end up
1666 * with all sorts of bugs when removing dwc3.ko.
1668 if (epnum != 0 && epnum != 1) {
1669 dwc3_free_trb_pool(dep);
1670 list_del(&dep->endpoint.ep_list);
1677 /* -------------------------------------------------------------------------- */
1679 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1680 struct dwc3_request *req, struct dwc3_trb *trb,
1681 const struct dwc3_event_depevt *event, int status)
1684 unsigned int s_pkt = 0;
1685 unsigned int trb_status;
1687 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1689 * We continue despite the error. There is not much we
1690 * can do. If we don't clean it up we loop forever. If
1691 * we skip the TRB then it gets overwritten after a
1692 * while since we use them in a ring buffer. A BUG()
1693 * would help. Lets hope that if this occurs, someone
1694 * fixes the root cause instead of looking away :)
1696 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1698 count = trb->size & DWC3_TRB_SIZE_MASK;
1700 if (dep->direction) {
1702 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1703 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1704 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1707 * If missed isoc occurred and there is
1708 * no request queued then issue END
1709 * TRANSFER, so that core generates
1710 * next xfernotready and we will issue
1711 * a fresh START TRANSFER.
1712 * If there are still queued request
1713 * then wait, do not issue either END
1714 * or UPDATE TRANSFER, just attach next
1715 * request in request_list during
1716 * giveback.If any future queued request
1717 * is successfully transferred then we
1718 * will issue UPDATE TRANSFER for all
1719 * request in the request_list.
1721 dep->flags |= DWC3_EP_MISSED_ISOC;
1723 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1725 status = -ECONNRESET;
1728 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1731 if (count && (event->status & DEPEVT_STATUS_SHORT))
1736 * We assume here we will always receive the entire data block
1737 * which we should receive. Meaning, if we program RX to
1738 * receive 4K but we receive only 2K, we assume that's all we
1739 * should receive and we simply bounce the request back to the
1740 * gadget driver for further processing.
1742 req->request.actual += req->request.length - count;
1745 if ((event->status & DEPEVT_STATUS_LST) &&
1746 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1747 DWC3_TRB_CTRL_HWO)))
1749 if ((event->status & DEPEVT_STATUS_IOC) &&
1750 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1755 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1756 const struct dwc3_event_depevt *event, int status)
1758 struct dwc3_request *req;
1759 struct dwc3_trb *trb;
1764 req = next_request(&dep->req_queued);
1770 slot = req->start_slot;
1771 if ((slot == DWC3_TRB_NUM - 1) &&
1772 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1774 slot %= DWC3_TRB_NUM;
1775 trb = &dep->trb_pool[slot];
1777 dwc3_flush_cache((int)trb, sizeof(*trb));
1778 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1783 dwc3_gadget_giveback(dep, req, status);
1789 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1790 list_empty(&dep->req_queued)) {
1791 if (list_empty(&dep->request_list)) {
1793 * If there is no entry in request list then do
1794 * not issue END TRANSFER now. Just set PENDING
1795 * flag, so that END TRANSFER is issued when an
1796 * entry is added into request list.
1798 dep->flags = DWC3_EP_PENDING_REQUEST;
1800 dwc3_stop_active_transfer(dwc, dep->number, true);
1801 dep->flags = DWC3_EP_ENABLED;
1809 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1810 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1812 unsigned status = 0;
1815 if (event->status & DEPEVT_STATUS_BUSERR)
1816 status = -ECONNRESET;
1818 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1820 dep->flags &= ~DWC3_EP_BUSY;
1823 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1824 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1826 if (dwc->revision < DWC3_REVISION_183A) {
1830 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1833 if (!(dep->flags & DWC3_EP_ENABLED))
1836 if (!list_empty(&dep->req_queued))
1840 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1842 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1848 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1849 const struct dwc3_event_depevt *event)
1851 struct dwc3_ep *dep;
1852 u8 epnum = event->endpoint_number;
1854 dep = dwc->eps[epnum];
1856 if (!(dep->flags & DWC3_EP_ENABLED))
1859 if (epnum == 0 || epnum == 1) {
1860 dwc3_ep0_interrupt(dwc, event);
1864 switch (event->endpoint_event) {
1865 case DWC3_DEPEVT_XFERCOMPLETE:
1866 dep->resource_index = 0;
1868 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1869 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1874 dwc3_endpoint_transfer_complete(dwc, dep, event);
1876 case DWC3_DEPEVT_XFERINPROGRESS:
1877 dwc3_endpoint_transfer_complete(dwc, dep, event);
1879 case DWC3_DEPEVT_XFERNOTREADY:
1880 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1881 dwc3_gadget_start_isoc(dwc, dep, event);
1885 dev_vdbg(dwc->dev, "%s: reason %s\n",
1886 dep->name, event->status &
1887 DEPEVT_STATUS_TRANSFER_ACTIVE
1889 : "Transfer Not Active");
1891 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1892 if (!ret || ret == -EBUSY)
1895 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1900 case DWC3_DEPEVT_STREAMEVT:
1901 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1902 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1907 switch (event->status) {
1908 case DEPEVT_STREAMEVT_FOUND:
1909 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1913 case DEPEVT_STREAMEVT_NOTFOUND:
1916 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1919 case DWC3_DEPEVT_RXTXFIFOEVT:
1920 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1922 case DWC3_DEPEVT_EPCMDCMPLT:
1923 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1928 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1930 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1931 spin_unlock(&dwc->lock);
1932 dwc->gadget_driver->disconnect(&dwc->gadget);
1933 spin_lock(&dwc->lock);
1937 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1939 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1940 spin_unlock(&dwc->lock);
1941 dwc->gadget_driver->suspend(&dwc->gadget);
1942 spin_lock(&dwc->lock);
1946 static void dwc3_resume_gadget(struct dwc3 *dwc)
1948 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1949 spin_unlock(&dwc->lock);
1950 dwc->gadget_driver->resume(&dwc->gadget);
1954 static void dwc3_reset_gadget(struct dwc3 *dwc)
1956 if (!dwc->gadget_driver)
1959 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1960 spin_unlock(&dwc->lock);
1961 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1962 spin_lock(&dwc->lock);
1966 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1968 struct dwc3_ep *dep;
1969 struct dwc3_gadget_ep_cmd_params params;
1973 dep = dwc->eps[epnum];
1975 if (!dep->resource_index)
1979 * NOTICE: We are violating what the Databook says about the
1980 * EndTransfer command. Ideally we would _always_ wait for the
1981 * EndTransfer Command Completion IRQ, but that's causing too
1982 * much trouble synchronizing between us and gadget driver.
1984 * We have discussed this with the IP Provider and it was
1985 * suggested to giveback all requests here, but give HW some
1986 * extra time to synchronize with the interconnect. We're using
1987 * an arbitraty 100us delay for that.
1989 * Note also that a similar handling was tested by Synopsys
1990 * (thanks a lot Paul) and nothing bad has come out of it.
1991 * In short, what we're doing is:
1993 * - Issue EndTransfer WITH CMDIOC bit set
1997 cmd = DWC3_DEPCMD_ENDTRANSFER;
1998 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1999 cmd |= DWC3_DEPCMD_CMDIOC;
2000 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2001 memset(¶ms, 0, sizeof(params));
2002 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2004 dep->resource_index = 0;
2005 dep->flags &= ~DWC3_EP_BUSY;
2009 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2013 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2014 struct dwc3_ep *dep;
2016 dep = dwc->eps[epnum];
2020 if (!(dep->flags & DWC3_EP_ENABLED))
2023 dwc3_remove_requests(dwc, dep);
2027 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2031 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2032 struct dwc3_ep *dep;
2033 struct dwc3_gadget_ep_cmd_params params;
2036 dep = dwc->eps[epnum];
2040 if (!(dep->flags & DWC3_EP_STALL))
2043 dep->flags &= ~DWC3_EP_STALL;
2045 memset(¶ms, 0, sizeof(params));
2046 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2047 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2052 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2056 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2057 reg &= ~DWC3_DCTL_INITU1ENA;
2058 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2060 reg &= ~DWC3_DCTL_INITU2ENA;
2061 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2063 dwc3_disconnect_gadget(dwc);
2064 dwc->start_config_issued = false;
2066 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2067 dwc->setup_packet_pending = false;
2068 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2071 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2076 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2077 * would cause a missing Disconnect Event if there's a
2078 * pending Setup Packet in the FIFO.
2080 * There's no suggested workaround on the official Bug
2081 * report, which states that "unless the driver/application
2082 * is doing any special handling of a disconnect event,
2083 * there is no functional issue".
2085 * Unfortunately, it turns out that we _do_ some special
2086 * handling of a disconnect event, namely complete all
2087 * pending transfers, notify gadget driver of the
2088 * disconnection, and so on.
2090 * Our suggested workaround is to follow the Disconnect
2091 * Event steps here, instead, based on a setup_packet_pending
2092 * flag. Such flag gets set whenever we have a XferNotReady
2093 * event on EP0 and gets cleared on XferComplete for the
2098 * STAR#9000466709: RTL: Device : Disconnect event not
2099 * generated if setup packet pending in FIFO
2101 if (dwc->revision < DWC3_REVISION_188A) {
2102 if (dwc->setup_packet_pending)
2103 dwc3_gadget_disconnect_interrupt(dwc);
2106 dwc3_reset_gadget(dwc);
2108 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2109 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2110 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2111 dwc->test_mode = false;
2113 dwc3_stop_active_transfers(dwc);
2114 dwc3_clear_stall_all_ep(dwc);
2115 dwc->start_config_issued = false;
2117 /* Reset device address to zero */
2118 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2119 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2120 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2123 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2126 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2129 * We change the clock only at SS but I dunno why I would want to do
2130 * this. Maybe it becomes part of the power saving plan.
2133 if (speed != DWC3_DSTS_SUPERSPEED)
2137 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2138 * each time on Connect Done.
2143 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2144 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2145 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2148 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2150 struct dwc3_ep *dep;
2155 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2156 speed = reg & DWC3_DSTS_CONNECTSPD;
2159 dwc3_update_ram_clk_sel(dwc, speed);
2162 case DWC3_DCFG_SUPERSPEED:
2164 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2165 * would cause a missing USB3 Reset event.
2167 * In such situations, we should force a USB3 Reset
2168 * event by calling our dwc3_gadget_reset_interrupt()
2173 * STAR#9000483510: RTL: SS : USB3 reset event may
2174 * not be generated always when the link enters poll
2176 if (dwc->revision < DWC3_REVISION_190A)
2177 dwc3_gadget_reset_interrupt(dwc);
2179 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2180 dwc->gadget.ep0->maxpacket = 512;
2181 dwc->gadget.speed = USB_SPEED_SUPER;
2183 case DWC3_DCFG_HIGHSPEED:
2184 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2185 dwc->gadget.ep0->maxpacket = 64;
2186 dwc->gadget.speed = USB_SPEED_HIGH;
2188 case DWC3_DCFG_FULLSPEED2:
2189 case DWC3_DCFG_FULLSPEED1:
2190 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2191 dwc->gadget.ep0->maxpacket = 64;
2192 dwc->gadget.speed = USB_SPEED_FULL;
2194 case DWC3_DCFG_LOWSPEED:
2195 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2196 dwc->gadget.ep0->maxpacket = 8;
2197 dwc->gadget.speed = USB_SPEED_LOW;
2201 /* Enable USB2 LPM Capability */
2203 if ((dwc->revision > DWC3_REVISION_194A)
2204 && (speed != DWC3_DCFG_SUPERSPEED)) {
2205 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2206 reg |= DWC3_DCFG_LPM_CAP;
2207 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2209 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2210 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2212 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2215 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2216 * DCFG.LPMCap is set, core responses with an ACK and the
2217 * BESL value in the LPM token is less than or equal to LPM
2220 if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum)
2221 WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2223 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2224 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2226 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2228 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2229 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2230 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2234 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2237 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2242 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2245 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2250 * Configure PHY via GUSB3PIPECTLn if required.
2252 * Update GTXFIFOSIZn
2254 * In both cases reset values should be sufficient.
2258 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2261 * TODO take core out of low power mode when that's
2265 dwc->gadget_driver->resume(&dwc->gadget);
2268 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2269 unsigned int evtinfo)
2271 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2272 unsigned int pwropt;
2275 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2276 * Hibernation mode enabled which would show up when device detects
2277 * host-initiated U3 exit.
2279 * In that case, device will generate a Link State Change Interrupt
2280 * from U3 to RESUME which is only necessary if Hibernation is
2283 * There are no functional changes due to such spurious event and we
2284 * just need to ignore it.
2288 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2291 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2292 if ((dwc->revision < DWC3_REVISION_250A) &&
2293 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2294 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2295 (next == DWC3_LINK_STATE_RESUME)) {
2296 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2302 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2303 * on the link partner, the USB session might do multiple entry/exit
2304 * of low power states before a transfer takes place.
2306 * Due to this problem, we might experience lower throughput. The
2307 * suggested workaround is to disable DCTL[12:9] bits if we're
2308 * transitioning from U1/U2 to U0 and enable those bits again
2309 * after a transfer completes and there are no pending transfers
2310 * on any of the enabled endpoints.
2312 * This is the first half of that workaround.
2316 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2317 * core send LGO_Ux entering U0
2319 if (dwc->revision < DWC3_REVISION_183A) {
2320 if (next == DWC3_LINK_STATE_U0) {
2324 switch (dwc->link_state) {
2325 case DWC3_LINK_STATE_U1:
2326 case DWC3_LINK_STATE_U2:
2327 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2328 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2329 | DWC3_DCTL_ACCEPTU2ENA
2330 | DWC3_DCTL_INITU1ENA
2331 | DWC3_DCTL_ACCEPTU1ENA);
2334 dwc->u1u2 = reg & u1u2;
2338 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2348 case DWC3_LINK_STATE_U1:
2349 if (dwc->speed == USB_SPEED_SUPER)
2350 dwc3_suspend_gadget(dwc);
2352 case DWC3_LINK_STATE_U2:
2353 case DWC3_LINK_STATE_U3:
2354 dwc3_suspend_gadget(dwc);
2356 case DWC3_LINK_STATE_RESUME:
2357 dwc3_resume_gadget(dwc);
2364 dwc->link_state = next;
2367 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2368 unsigned int evtinfo)
2370 unsigned int is_ss = evtinfo & BIT(4);
2373 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2374 * have a known issue which can cause USB CV TD.9.23 to fail
2377 * Because of this issue, core could generate bogus hibernation
2378 * events which SW needs to ignore.
2382 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2383 * Device Fallback from SuperSpeed
2385 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2388 /* enter hibernation here */
2391 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2392 const struct dwc3_event_devt *event)
2394 switch (event->type) {
2395 case DWC3_DEVICE_EVENT_DISCONNECT:
2396 dwc3_gadget_disconnect_interrupt(dwc);
2398 case DWC3_DEVICE_EVENT_RESET:
2399 dwc3_gadget_reset_interrupt(dwc);
2401 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2402 dwc3_gadget_conndone_interrupt(dwc);
2404 case DWC3_DEVICE_EVENT_WAKEUP:
2405 dwc3_gadget_wakeup_interrupt(dwc);
2407 case DWC3_DEVICE_EVENT_HIBER_REQ:
2408 if (!dwc->has_hibernation) {
2409 WARN(1 ,"unexpected hibernation event\n");
2412 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2414 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2415 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2417 case DWC3_DEVICE_EVENT_EOPF:
2418 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2420 case DWC3_DEVICE_EVENT_SOF:
2421 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2423 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2424 dev_vdbg(dwc->dev, "Erratic Error\n");
2426 case DWC3_DEVICE_EVENT_CMD_CMPL:
2427 dev_vdbg(dwc->dev, "Command Complete\n");
2429 case DWC3_DEVICE_EVENT_OVERFLOW:
2430 dev_vdbg(dwc->dev, "Overflow\n");
2433 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2437 static void dwc3_process_event_entry(struct dwc3 *dwc,
2438 const union dwc3_event *event)
2440 /* Endpoint IRQ, handle it and return early */
2441 if (event->type.is_devspec == 0) {
2443 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2446 switch (event->type.type) {
2447 case DWC3_EVENT_TYPE_DEV:
2448 dwc3_gadget_interrupt(dwc, &event->devt);
2450 /* REVISIT what to do with Carkit and I2C events ? */
2452 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2456 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2458 struct dwc3_event_buffer *evt;
2459 irqreturn_t ret = IRQ_NONE;
2463 evt = dwc->ev_buffs[buf];
2466 if (!(evt->flags & DWC3_EVENT_PENDING))
2470 union dwc3_event event;
2472 event.raw = *(u32 *) (evt->buf + evt->lpos);
2474 dwc3_process_event_entry(dwc, &event);
2477 * FIXME we wrap around correctly to the next entry as
2478 * almost all entries are 4 bytes in size. There is one
2479 * entry which has 12 bytes which is a regular entry
2480 * followed by 8 bytes data. ATM I don't know how
2481 * things are organized if we get next to the a
2482 * boundary so I worry about that once we try to handle
2485 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2488 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2492 evt->flags &= ~DWC3_EVENT_PENDING;
2495 /* Unmask interrupt */
2496 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2497 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2498 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2503 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2505 struct dwc3 *dwc = _dwc;
2506 unsigned long flags;
2507 irqreturn_t ret = IRQ_NONE;
2510 spin_lock_irqsave(&dwc->lock, flags);
2512 for (i = 0; i < dwc->num_event_buffers; i++)
2513 ret |= dwc3_process_event_buf(dwc, i);
2515 spin_unlock_irqrestore(&dwc->lock, flags);
2520 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2522 struct dwc3_event_buffer *evt;
2526 evt = dwc->ev_buffs[buf];
2528 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2529 count &= DWC3_GEVNTCOUNT_MASK;
2534 evt->flags |= DWC3_EVENT_PENDING;
2536 /* Mask interrupt */
2537 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2538 reg |= DWC3_GEVNTSIZ_INTMASK;
2539 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2541 return IRQ_WAKE_THREAD;
2544 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2546 struct dwc3 *dwc = _dwc;
2548 irqreturn_t ret = IRQ_NONE;
2550 spin_lock(&dwc->lock);
2552 for (i = 0; i < dwc->num_event_buffers; i++) {
2555 status = dwc3_check_event_buf(dwc, i);
2556 if (status == IRQ_WAKE_THREAD)
2560 spin_unlock(&dwc->lock);
2566 * dwc3_gadget_init - Initializes gadget related registers
2567 * @dwc: pointer to our controller context structure
2569 * Returns 0 on success otherwise negative errno.
2571 int dwc3_gadget_init(struct dwc3 *dwc)
2575 dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2576 (unsigned long *)&dwc->ctrl_req_addr);
2577 if (!dwc->ctrl_req) {
2578 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2583 dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb),
2584 (unsigned long *)&dwc->ep0_trb_addr);
2585 if (!dwc->ep0_trb) {
2586 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2591 dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2592 DWC3_EP0_BOUNCE_SIZE);
2593 if (!dwc->setup_buf) {
2598 dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2599 (unsigned long *)&dwc->ep0_bounce_addr);
2600 if (!dwc->ep0_bounce) {
2601 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2606 dwc->gadget.ops = &dwc3_gadget_ops;
2607 dwc->gadget.max_speed = USB_SPEED_SUPER;
2608 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2609 dwc->gadget.name = "dwc3-gadget";
2612 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2615 dwc->gadget.quirk_ep_out_aligned_size = true;
2618 * REVISIT: Here we should clear all pending IRQs to be
2619 * sure we're starting from a well known location.
2622 ret = dwc3_gadget_init_endpoints(dwc);
2626 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2628 dev_err(dwc->dev, "failed to register udc\n");
2635 dwc3_gadget_free_endpoints(dwc);
2636 dma_free_coherent(dwc->ep0_bounce);
2639 kfree(dwc->setup_buf);
2642 dma_free_coherent(dwc->ep0_trb);
2645 dma_free_coherent(dwc->ctrl_req);
2651 /* -------------------------------------------------------------------------- */
2653 void dwc3_gadget_exit(struct dwc3 *dwc)
2655 usb_del_gadget_udc(&dwc->gadget);
2657 dwc3_gadget_free_endpoints(dwc);
2659 dma_free_coherent(dwc->ep0_bounce);
2661 kfree(dwc->setup_buf);
2663 dma_free_coherent(dwc->ep0_trb);
2665 dma_free_coherent(dwc->ctrl_req);
2669 * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2670 * @dwc: struct dwce *
2672 * Handles ep0 and gadget interrupt
2674 * Should be called from dwc3 core.
2676 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2678 dwc3_interrupt(0, dwc);
2679 dwc3_thread_interrupt(0, dwc);