2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
12 * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
14 * SPDX-License-Identifier: GPL-2.0
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/interrupt.h>
25 #include <linux/list.h>
26 #include <linux/dma-mapping.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
37 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
38 * @dwc: pointer to our context structure
39 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
41 * Caller should take care of locking. This function will
42 * return 0 on success or -EINVAL if wrong Test Selector
45 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
49 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
50 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
64 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
70 * dwc3_gadget_get_link_state - Gets current state of USB Link
71 * @dwc: pointer to our context structure
73 * Caller should take care of locking. This function will
74 * return the link state on success (>= 0) or -ETIMEDOUT.
76 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
80 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
82 return DWC3_DSTS_USBLNKST(reg);
86 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
87 * @dwc: pointer to our context structure
88 * @state: the state to put link into
90 * Caller should take care of locking. This function will
91 * return 0 on success or -ETIMEDOUT.
93 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99 * Wait until device controller is ready. Only applies to 1.94a and
102 if (dwc->revision >= DWC3_REVISION_194A) {
104 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
105 if (reg & DWC3_DSTS_DCNRD)
115 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
116 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
118 /* set requested state */
119 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
120 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123 * The following code is racy when called from dwc3_gadget_wakeup,
124 * and is not needed, at least on newer versions
126 if (dwc->revision >= DWC3_REVISION_194A)
129 /* wait for a change in DSTS */
132 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
134 if (DWC3_DSTS_USBLNKST(reg) == state)
140 dev_vdbg(dwc->dev, "link state change request timed out\n");
146 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
147 * @dwc: pointer to our context structure
149 * This function will a best effort FIFO allocation in order
150 * to improve FIFO usage and throughput, while still allowing
151 * us to enable as many endpoints as possible.
153 * Keep in mind that this operation will be highly dependent
154 * on the configured size for RAM1 - which contains TxFifo -,
155 * the amount of endpoints enabled on coreConsultant tool, and
156 * the width of the Master Bus.
158 * In the ideal world, we would always be able to satisfy the
159 * following equation:
161 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
162 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
164 * Unfortunately, due to many variables that's not always the case.
166 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
168 int last_fifo_depth = 0;
174 if (!dwc->needs_fifo_resize)
177 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
178 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
180 /* MDWIDTH is represented in bits, we need it in bytes */
184 * FIXME For now we will only allocate 1 wMaxPacketSize space
185 * for each enabled endpoint, later patches will come to
186 * improve this algorithm so that we better use the internal
189 for (num = 0; num < dwc->num_in_eps; num++) {
190 /* bit0 indicates direction; 1 means IN ep */
191 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
195 if (!(dep->flags & DWC3_EP_ENABLED))
198 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
199 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
203 * REVISIT: the following assumes we will always have enough
204 * space available on the FIFO RAM for all possible use cases.
205 * Make sure that's true somehow and change FIFO allocation
208 * If we have Bulk or Isochronous endpoints, we want
209 * them to be able to be very, very fast. So we're giving
210 * those endpoints a fifo_size which is enough for 3 full
213 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
216 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
218 fifo_size |= (last_fifo_depth << 16);
220 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
221 dep->name, last_fifo_depth, fifo_size & 0xffff);
223 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
225 last_fifo_depth += (fifo_size & 0xffff);
231 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
234 struct dwc3 *dwc = dep->dwc;
242 * Skip LINK TRB. We can't use req->trb and check for
243 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
244 * just completed (not the LINK TRB).
246 if (((dep->busy_slot & DWC3_TRB_MASK) ==
248 usb_endpoint_xfer_isoc(dep->endpoint.desc))
250 } while(++i < req->request.num_mapped_sgs);
253 list_del(&req->list);
256 if (req->request.status == -EINPROGRESS)
257 req->request.status = status;
259 if (dwc->ep0_bounced && dep->number == 0)
260 dwc->ep0_bounced = false;
262 usb_gadget_unmap_request(&dwc->gadget, &req->request,
265 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
266 req, dep->name, req->request.actual,
267 req->request.length, status);
269 spin_unlock(&dwc->lock);
270 usb_gadget_giveback_request(&dep->endpoint, &req->request);
271 spin_lock(&dwc->lock);
274 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
279 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
280 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
283 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
284 if (!(reg & DWC3_DGCMD_CMDACT)) {
285 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
286 DWC3_DGCMD_STATUS(reg));
291 * We can't sleep here, because it's also called from
301 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
302 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
304 struct dwc3_ep *dep = dwc->eps[ep];
308 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
309 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
310 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
312 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
314 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
315 if (!(reg & DWC3_DEPCMD_CMDACT)) {
316 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
317 DWC3_DEPCMD_STATUS(reg));
322 * We can't sleep here, because it is also called from
333 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
334 struct dwc3_trb *trb)
336 u32 offset = (char *) trb - (char *) dep->trb_pool;
338 return dep->trb_pool_dma + offset;
341 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
343 struct dwc3 *dwc = dep->dwc;
348 if (dep->number == 0 || dep->number == 1)
351 dep->trb_pool = dma_alloc_coherent(dwc->dev,
352 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
353 &dep->trb_pool_dma, GFP_KERNEL);
354 if (!dep->trb_pool) {
355 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
363 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
365 struct dwc3 *dwc = dep->dwc;
367 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
368 dep->trb_pool, dep->trb_pool_dma);
370 dep->trb_pool = NULL;
371 dep->trb_pool_dma = 0;
374 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
376 struct dwc3_gadget_ep_cmd_params params;
379 memset(¶ms, 0x00, sizeof(params));
381 if (dep->number != 1) {
382 cmd = DWC3_DEPCMD_DEPSTARTCFG;
383 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
384 if (dep->number > 1) {
385 if (dwc->start_config_issued)
387 dwc->start_config_issued = true;
388 cmd |= DWC3_DEPCMD_PARAM(2);
391 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
397 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
398 const struct usb_endpoint_descriptor *desc,
399 const struct usb_ss_ep_comp_descriptor *comp_desc,
400 bool ignore, bool restore)
402 struct dwc3_gadget_ep_cmd_params params;
404 memset(¶ms, 0x00, sizeof(params));
406 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
407 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
409 /* Burst size is only needed in SuperSpeed mode */
410 if (dwc->gadget.speed == USB_SPEED_SUPER) {
411 u32 burst = dep->endpoint.maxburst - 1;
413 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
417 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
420 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
421 params.param2 |= dep->saved_state;
424 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
425 | DWC3_DEPCFG_XFER_NOT_READY_EN;
427 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
428 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
429 | DWC3_DEPCFG_STREAM_EVENT_EN;
430 dep->stream_capable = true;
433 if (!usb_endpoint_xfer_control(desc))
434 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
437 * We are doing 1:1 mapping for endpoints, meaning
438 * Physical Endpoints 2 maps to Logical Endpoint 2 and
439 * so on. We consider the direction bit as part of the physical
440 * endpoint number. So USB endpoint 0x81 is 0x03.
442 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
445 * We must use the lower 16 TX FIFOs even though
449 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
451 if (desc->bInterval) {
452 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
453 dep->interval = 1 << (desc->bInterval - 1);
456 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
457 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
460 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
462 struct dwc3_gadget_ep_cmd_params params;
464 memset(¶ms, 0x00, sizeof(params));
466 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
468 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
469 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
473 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
474 * @dep: endpoint to be initialized
475 * @desc: USB Endpoint Descriptor
477 * Caller should take care of locking
479 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
480 const struct usb_endpoint_descriptor *desc,
481 const struct usb_ss_ep_comp_descriptor *comp_desc,
482 bool ignore, bool restore)
484 struct dwc3 *dwc = dep->dwc;
488 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
490 if (!(dep->flags & DWC3_EP_ENABLED)) {
491 ret = dwc3_gadget_start_config(dwc, dep);
496 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
501 if (!(dep->flags & DWC3_EP_ENABLED)) {
502 struct dwc3_trb *trb_st_hw;
503 struct dwc3_trb *trb_link;
505 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
509 dep->endpoint.desc = desc;
510 dep->comp_desc = comp_desc;
511 dep->type = usb_endpoint_type(desc);
512 dep->flags |= DWC3_EP_ENABLED;
514 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
515 reg |= DWC3_DALEPENA_EP(dep->number);
516 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
518 if (!usb_endpoint_xfer_isoc(desc))
521 /* Link TRB for ISOC. The HWO bit is never reset */
522 trb_st_hw = &dep->trb_pool[0];
524 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
525 memset(trb_link, 0, sizeof(*trb_link));
527 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
528 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
529 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
530 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
536 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
537 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
539 struct dwc3_request *req;
541 if (!list_empty(&dep->req_queued)) {
542 dwc3_stop_active_transfer(dwc, dep->number, true);
544 /* - giveback all requests to gadget driver */
545 while (!list_empty(&dep->req_queued)) {
546 req = next_request(&dep->req_queued);
548 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
552 while (!list_empty(&dep->request_list)) {
553 req = next_request(&dep->request_list);
555 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
560 * __dwc3_gadget_ep_disable - Disables a HW endpoint
561 * @dep: the endpoint to disable
563 * This function also removes requests which are currently processed ny the
564 * hardware and those which are not yet scheduled.
565 * Caller should take care of locking.
567 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
569 struct dwc3 *dwc = dep->dwc;
572 dwc3_remove_requests(dwc, dep);
574 /* make sure HW endpoint isn't stalled */
575 if (dep->flags & DWC3_EP_STALL)
576 __dwc3_gadget_ep_set_halt(dep, 0, false);
578 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
579 reg &= ~DWC3_DALEPENA_EP(dep->number);
580 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
582 dep->stream_capable = false;
583 dep->endpoint.desc = NULL;
584 dep->comp_desc = NULL;
591 /* -------------------------------------------------------------------------- */
593 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
594 const struct usb_endpoint_descriptor *desc)
599 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
604 /* -------------------------------------------------------------------------- */
606 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
607 const struct usb_endpoint_descriptor *desc)
614 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
615 pr_debug("dwc3: invalid parameters\n");
619 if (!desc->wMaxPacketSize) {
620 pr_debug("dwc3: missing wMaxPacketSize\n");
624 dep = to_dwc3_ep(ep);
627 if (dep->flags & DWC3_EP_ENABLED) {
628 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
633 switch (usb_endpoint_type(desc)) {
634 case USB_ENDPOINT_XFER_CONTROL:
635 strlcat(dep->name, "-control", sizeof(dep->name));
637 case USB_ENDPOINT_XFER_ISOC:
638 strlcat(dep->name, "-isoc", sizeof(dep->name));
640 case USB_ENDPOINT_XFER_BULK:
641 strlcat(dep->name, "-bulk", sizeof(dep->name));
643 case USB_ENDPOINT_XFER_INT:
644 strlcat(dep->name, "-int", sizeof(dep->name));
647 dev_err(dwc->dev, "invalid endpoint transfer type\n");
650 spin_lock_irqsave(&dwc->lock, flags);
651 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
652 spin_unlock_irqrestore(&dwc->lock, flags);
657 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
665 pr_debug("dwc3: invalid parameters\n");
669 dep = to_dwc3_ep(ep);
672 if (!(dep->flags & DWC3_EP_ENABLED)) {
673 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
678 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
680 (dep->number & 1) ? "in" : "out");
682 spin_lock_irqsave(&dwc->lock, flags);
683 ret = __dwc3_gadget_ep_disable(dep);
684 spin_unlock_irqrestore(&dwc->lock, flags);
689 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
692 struct dwc3_request *req;
693 struct dwc3_ep *dep = to_dwc3_ep(ep);
695 req = kzalloc(sizeof(*req), gfp_flags);
699 req->epnum = dep->number;
702 return &req->request;
705 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
706 struct usb_request *request)
708 struct dwc3_request *req = to_dwc3_request(request);
714 * dwc3_prepare_one_trb - setup one TRB from one request
715 * @dep: endpoint for which this request is prepared
716 * @req: dwc3_request pointer
718 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
719 struct dwc3_request *req, dma_addr_t dma,
720 unsigned length, unsigned last, unsigned chain, unsigned node)
722 struct dwc3 *dwc = dep->dwc;
723 struct dwc3_trb *trb;
725 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
726 dep->name, req, (unsigned long long) dma,
727 length, last ? " last" : "",
728 chain ? " chain" : "");
731 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
734 dwc3_gadget_move_request_queued(req);
736 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
737 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
741 /* Skip the LINK-TRB on ISOC */
742 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
743 usb_endpoint_xfer_isoc(dep->endpoint.desc))
746 trb->size = DWC3_TRB_SIZE_LENGTH(length);
747 trb->bpl = lower_32_bits(dma);
748 trb->bph = upper_32_bits(dma);
750 switch (usb_endpoint_type(dep->endpoint.desc)) {
751 case USB_ENDPOINT_XFER_CONTROL:
752 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
755 case USB_ENDPOINT_XFER_ISOC:
757 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
759 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
762 case USB_ENDPOINT_XFER_BULK:
763 case USB_ENDPOINT_XFER_INT:
764 trb->ctrl = DWC3_TRBCTL_NORMAL;
768 * This is only possible with faulty memory because we
769 * checked it already :)
774 if (!req->request.no_interrupt && !chain)
775 trb->ctrl |= DWC3_TRB_CTRL_IOC;
777 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
778 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
779 trb->ctrl |= DWC3_TRB_CTRL_CSP;
781 trb->ctrl |= DWC3_TRB_CTRL_LST;
785 trb->ctrl |= DWC3_TRB_CTRL_CHN;
787 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
788 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
790 trb->ctrl |= DWC3_TRB_CTRL_HWO;
794 * dwc3_prepare_trbs - setup TRBs from requests
795 * @dep: endpoint for which requests are being prepared
796 * @starting: true if the endpoint is idle and no requests are queued.
798 * The function goes through the requests list and sets up TRBs for the
799 * transfers. The function returns once there are no more TRBs available or
800 * it runs out of requests.
802 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
804 struct dwc3_request *req, *n;
807 unsigned int last_one = 0;
809 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
811 /* the first request must not be queued */
812 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
814 /* Can't wrap around on a non-isoc EP since there's no link TRB */
815 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
816 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
822 * If busy & slot are equal than it is either full or empty. If we are
823 * starting to process requests then we are empty. Otherwise we are
824 * full and don't do anything
829 trbs_left = DWC3_TRB_NUM;
831 * In case we start from scratch, we queue the ISOC requests
832 * starting from slot 1. This is done because we use ring
833 * buffer and have no LST bit to stop us. Instead, we place
834 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
835 * after the first request so we start at slot 1 and have
836 * 7 requests proceed before we hit the first IOC.
837 * Other transfer types don't use the ring buffer and are
838 * processed from the first TRB until the last one. Since we
839 * don't wrap around we have to start at the beginning.
841 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
850 /* The last TRB is a link TRB, not used for xfer */
851 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
854 list_for_each_entry_safe(req, n, &dep->request_list, list) {
859 if (req->request.num_mapped_sgs > 0) {
860 struct usb_request *request = &req->request;
861 struct scatterlist *sg = request->sg;
862 struct scatterlist *s;
865 for_each_sg(sg, s, request->num_mapped_sgs, i) {
866 unsigned chain = true;
868 length = sg_dma_len(s);
869 dma = sg_dma_address(s);
871 if (i == (request->num_mapped_sgs - 1) ||
873 if (list_is_last(&req->list,
886 dwc3_prepare_one_trb(dep, req, dma, length,
893 dma = req->request.dma;
894 length = req->request.length;
900 /* Is this the last request? */
901 if (list_is_last(&req->list, &dep->request_list))
904 dwc3_prepare_one_trb(dep, req, dma, length,
913 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
916 struct dwc3_gadget_ep_cmd_params params;
917 struct dwc3_request *req;
918 struct dwc3 *dwc = dep->dwc;
922 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
923 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
926 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
929 * If we are getting here after a short-out-packet we don't enqueue any
930 * new requests as we try to set the IOC bit only on the last request.
933 if (list_empty(&dep->req_queued))
934 dwc3_prepare_trbs(dep, start_new);
936 /* req points to the first request which will be sent */
937 req = next_request(&dep->req_queued);
939 dwc3_prepare_trbs(dep, start_new);
942 * req points to the first request where HWO changed from 0 to 1
944 req = next_request(&dep->req_queued);
947 dep->flags |= DWC3_EP_PENDING_REQUEST;
951 memset(¶ms, 0, sizeof(params));
954 params.param0 = upper_32_bits(req->trb_dma);
955 params.param1 = lower_32_bits(req->trb_dma);
956 cmd = DWC3_DEPCMD_STARTTRANSFER;
958 cmd = DWC3_DEPCMD_UPDATETRANSFER;
961 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
962 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
964 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
967 * FIXME we need to iterate over the list of requests
968 * here and stop, unmap, free and del each of the linked
969 * requests instead of what we do now.
971 usb_gadget_unmap_request(&dwc->gadget, &req->request,
973 list_del(&req->list);
977 dep->flags |= DWC3_EP_BUSY;
980 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
982 WARN_ON_ONCE(!dep->resource_index);
988 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
989 struct dwc3_ep *dep, u32 cur_uf)
993 if (list_empty(&dep->request_list)) {
994 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
996 dep->flags |= DWC3_EP_PENDING_REQUEST;
1000 /* 4 micro frames in the future */
1001 uf = cur_uf + dep->interval * 4;
1003 __dwc3_gadget_kick_transfer(dep, uf, 1);
1006 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1007 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1011 mask = ~(dep->interval - 1);
1012 cur_uf = event->parameters & mask;
1014 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1017 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1019 struct dwc3 *dwc = dep->dwc;
1022 req->request.actual = 0;
1023 req->request.status = -EINPROGRESS;
1024 req->direction = dep->direction;
1025 req->epnum = dep->number;
1028 * We only add to our list of requests now and
1029 * start consuming the list once we get XferNotReady
1032 * That way, we avoid doing anything that we don't need
1033 * to do now and defer it until the point we receive a
1034 * particular token from the Host side.
1036 * This will also avoid Host cancelling URBs due to too
1039 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1044 list_add_tail(&req->list, &dep->request_list);
1047 * There are a few special cases:
1049 * 1. XferNotReady with empty list of requests. We need to kick the
1050 * transfer here in that situation, otherwise we will be NAKing
1051 * forever. If we get XferNotReady before gadget driver has a
1052 * chance to queue a request, we will ACK the IRQ but won't be
1053 * able to receive the data until the next request is queued.
1054 * The following code is handling exactly that.
1057 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1059 * If xfernotready is already elapsed and it is a case
1060 * of isoc transfer, then issue END TRANSFER, so that
1061 * you can receive xfernotready again and can have
1062 * notion of current microframe.
1064 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1065 if (list_empty(&dep->req_queued)) {
1066 dwc3_stop_active_transfer(dwc, dep->number, true);
1067 dep->flags = DWC3_EP_ENABLED;
1072 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1073 if (ret && ret != -EBUSY)
1074 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1080 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1081 * kick the transfer here after queuing a request, otherwise the
1082 * core may not see the modified TRB(s).
1084 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1085 (dep->flags & DWC3_EP_BUSY) &&
1086 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1087 WARN_ON_ONCE(!dep->resource_index);
1088 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1090 if (ret && ret != -EBUSY)
1091 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1097 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1098 * right away, otherwise host will not know we have streams to be
1101 if (dep->stream_capable) {
1104 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1105 if (ret && ret != -EBUSY) {
1106 struct dwc3 *dwc = dep->dwc;
1108 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1116 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1119 struct dwc3_request *req = to_dwc3_request(request);
1120 struct dwc3_ep *dep = to_dwc3_ep(ep);
1121 struct dwc3 *dwc = dep->dwc;
1123 unsigned long flags;
1127 spin_lock_irqsave(&dwc->lock, flags);
1128 if (!dep->endpoint.desc) {
1129 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1135 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1136 request, req->dep->name)) {
1141 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1142 request, ep->name, request->length);
1144 ret = __dwc3_gadget_ep_queue(dep, req);
1147 spin_unlock_irqrestore(&dwc->lock, flags);
1152 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1153 struct usb_request *request)
1155 struct dwc3_request *req = to_dwc3_request(request);
1156 struct dwc3_request *r = NULL;
1158 struct dwc3_ep *dep = to_dwc3_ep(ep);
1159 struct dwc3 *dwc = dep->dwc;
1161 unsigned long flags;
1164 spin_lock_irqsave(&dwc->lock, flags);
1166 list_for_each_entry(r, &dep->request_list, list) {
1172 list_for_each_entry(r, &dep->req_queued, list) {
1177 /* wait until it is processed */
1178 dwc3_stop_active_transfer(dwc, dep->number, true);
1181 dev_err(dwc->dev, "request %p was not queued to %s\n",
1188 /* giveback the request */
1189 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1192 spin_unlock_irqrestore(&dwc->lock, flags);
1197 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1199 struct dwc3_gadget_ep_cmd_params params;
1200 struct dwc3 *dwc = dep->dwc;
1203 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1204 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1208 memset(¶ms, 0x00, sizeof(params));
1211 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1212 (!list_empty(&dep->req_queued) ||
1213 !list_empty(&dep->request_list)))) {
1214 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1219 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1220 DWC3_DEPCMD_SETSTALL, ¶ms);
1222 dev_err(dwc->dev, "failed to set STALL on %s\n",
1225 dep->flags |= DWC3_EP_STALL;
1227 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1228 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1230 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1233 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1239 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1241 struct dwc3_ep *dep = to_dwc3_ep(ep);
1242 struct dwc3 *dwc = dep->dwc;
1244 unsigned long flags;
1248 spin_lock_irqsave(&dwc->lock, flags);
1249 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1250 spin_unlock_irqrestore(&dwc->lock, flags);
1255 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1257 struct dwc3_ep *dep = to_dwc3_ep(ep);
1258 struct dwc3 *dwc = dep->dwc;
1259 unsigned long flags;
1262 spin_lock_irqsave(&dwc->lock, flags);
1263 dep->flags |= DWC3_EP_WEDGE;
1265 if (dep->number == 0 || dep->number == 1)
1266 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1268 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1269 spin_unlock_irqrestore(&dwc->lock, flags);
1274 /* -------------------------------------------------------------------------- */
1276 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1277 .bLength = USB_DT_ENDPOINT_SIZE,
1278 .bDescriptorType = USB_DT_ENDPOINT,
1279 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1282 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1283 .enable = dwc3_gadget_ep0_enable,
1284 .disable = dwc3_gadget_ep0_disable,
1285 .alloc_request = dwc3_gadget_ep_alloc_request,
1286 .free_request = dwc3_gadget_ep_free_request,
1287 .queue = dwc3_gadget_ep0_queue,
1288 .dequeue = dwc3_gadget_ep_dequeue,
1289 .set_halt = dwc3_gadget_ep0_set_halt,
1290 .set_wedge = dwc3_gadget_ep_set_wedge,
1293 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1294 .enable = dwc3_gadget_ep_enable,
1295 .disable = dwc3_gadget_ep_disable,
1296 .alloc_request = dwc3_gadget_ep_alloc_request,
1297 .free_request = dwc3_gadget_ep_free_request,
1298 .queue = dwc3_gadget_ep_queue,
1299 .dequeue = dwc3_gadget_ep_dequeue,
1300 .set_halt = dwc3_gadget_ep_set_halt,
1301 .set_wedge = dwc3_gadget_ep_set_wedge,
1304 /* -------------------------------------------------------------------------- */
1306 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1308 struct dwc3 *dwc = gadget_to_dwc(g);
1311 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1312 return DWC3_DSTS_SOFFN(reg);
1315 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1317 struct dwc3 *dwc = gadget_to_dwc(g);
1319 unsigned long timeout;
1320 unsigned long flags;
1329 spin_lock_irqsave(&dwc->lock, flags);
1332 * According to the Databook Remote wakeup request should
1333 * be issued only when the device is in early suspend state.
1335 * We can check that via USB Link State bits in DSTS register.
1337 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1339 speed = reg & DWC3_DSTS_CONNECTSPD;
1340 if (speed == DWC3_DSTS_SUPERSPEED) {
1341 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1346 link_state = DWC3_DSTS_USBLNKST(reg);
1348 switch (link_state) {
1349 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1350 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1353 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1359 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1361 dev_err(dwc->dev, "failed to put link in Recovery\n");
1365 /* Recent versions do this automatically */
1366 if (dwc->revision < DWC3_REVISION_194A) {
1367 /* write zeroes to Link Change Request */
1368 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1369 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1370 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1373 /* poll until Link State changes to ON */
1374 timeout = jiffies + msecs_to_jiffies(100);
1376 while (!time_after(jiffies, timeout)) {
1377 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1379 /* in HS, means ON */
1380 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1384 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1385 dev_err(dwc->dev, "failed to send remote wakeup\n");
1390 spin_unlock_irqrestore(&dwc->lock, flags);
1395 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1398 struct dwc3 *dwc = gadget_to_dwc(g);
1399 unsigned long flags;
1401 spin_lock_irqsave(&dwc->lock, flags);
1402 dwc->is_selfpowered = !!is_selfpowered;
1403 spin_unlock_irqrestore(&dwc->lock, flags);
1408 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1413 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1415 if (dwc->revision <= DWC3_REVISION_187A) {
1416 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1417 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1420 if (dwc->revision >= DWC3_REVISION_194A)
1421 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1422 reg |= DWC3_DCTL_RUN_STOP;
1424 if (dwc->has_hibernation)
1425 reg |= DWC3_DCTL_KEEP_CONNECT;
1427 dwc->pullups_connected = true;
1429 reg &= ~DWC3_DCTL_RUN_STOP;
1431 if (dwc->has_hibernation && !suspend)
1432 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1434 dwc->pullups_connected = false;
1437 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1440 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1442 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1445 if (reg & DWC3_DSTS_DEVCTRLHLT)
1454 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1456 ? dwc->gadget_driver->function : "no-function",
1457 is_on ? "connect" : "disconnect");
1462 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1464 struct dwc3 *dwc = gadget_to_dwc(g);
1465 unsigned long flags;
1470 spin_lock_irqsave(&dwc->lock, flags);
1471 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1472 spin_unlock_irqrestore(&dwc->lock, flags);
1477 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1481 /* Enable all but Start and End of Frame IRQs */
1482 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1483 DWC3_DEVTEN_EVNTOVERFLOWEN |
1484 DWC3_DEVTEN_CMDCMPLTEN |
1485 DWC3_DEVTEN_ERRTICERREN |
1486 DWC3_DEVTEN_WKUPEVTEN |
1487 DWC3_DEVTEN_ULSTCNGEN |
1488 DWC3_DEVTEN_CONNECTDONEEN |
1489 DWC3_DEVTEN_USBRSTEN |
1490 DWC3_DEVTEN_DISCONNEVTEN);
1492 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1495 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1497 /* mask all interrupts */
1498 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1501 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1502 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1504 static int dwc3_gadget_start(struct usb_gadget *g,
1505 struct usb_gadget_driver *driver)
1507 struct dwc3 *dwc = gadget_to_dwc(g);
1508 struct dwc3_ep *dep;
1509 unsigned long flags;
1514 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1515 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1516 IRQF_SHARED, "dwc3", dwc);
1518 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1523 spin_lock_irqsave(&dwc->lock, flags);
1525 if (dwc->gadget_driver) {
1526 dev_err(dwc->dev, "%s is already bound to %s\n",
1528 dwc->gadget_driver->driver.name);
1533 dwc->gadget_driver = driver;
1535 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1536 reg &= ~(DWC3_DCFG_SPEED_MASK);
1539 * WORKAROUND: DWC3 revision < 2.20a have an issue
1540 * which would cause metastability state on Run/Stop
1541 * bit if we try to force the IP to USB2-only mode.
1543 * Because of that, we cannot configure the IP to any
1544 * speed other than the SuperSpeed
1548 * STAR#9000525659: Clock Domain Crossing on DCTL in
1551 if (dwc->revision < DWC3_REVISION_220A) {
1552 reg |= DWC3_DCFG_SUPERSPEED;
1554 switch (dwc->maximum_speed) {
1556 reg |= DWC3_DSTS_LOWSPEED;
1558 case USB_SPEED_FULL:
1559 reg |= DWC3_DSTS_FULLSPEED1;
1561 case USB_SPEED_HIGH:
1562 reg |= DWC3_DSTS_HIGHSPEED;
1564 case USB_SPEED_SUPER: /* FALLTHROUGH */
1565 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1567 reg |= DWC3_DSTS_SUPERSPEED;
1570 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1572 dwc->start_config_issued = false;
1574 /* Start with SuperSpeed Default */
1575 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1578 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1581 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1586 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1589 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1593 /* begin to receive SETUP packets */
1594 dwc->ep0state = EP0_SETUP_PHASE;
1595 dwc3_ep0_out_start(dwc);
1597 dwc3_gadget_enable_irq(dwc);
1599 spin_unlock_irqrestore(&dwc->lock, flags);
1604 __dwc3_gadget_ep_disable(dwc->eps[0]);
1607 dwc->gadget_driver = NULL;
1610 spin_unlock_irqrestore(&dwc->lock, flags);
1618 static int dwc3_gadget_stop(struct usb_gadget *g)
1620 struct dwc3 *dwc = gadget_to_dwc(g);
1621 unsigned long flags;
1624 spin_lock_irqsave(&dwc->lock, flags);
1626 dwc3_gadget_disable_irq(dwc);
1627 __dwc3_gadget_ep_disable(dwc->eps[0]);
1628 __dwc3_gadget_ep_disable(dwc->eps[1]);
1630 dwc->gadget_driver = NULL;
1632 spin_unlock_irqrestore(&dwc->lock, flags);
1634 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1640 static const struct usb_gadget_ops dwc3_gadget_ops = {
1641 .get_frame = dwc3_gadget_get_frame,
1642 .wakeup = dwc3_gadget_wakeup,
1643 .set_selfpowered = dwc3_gadget_set_selfpowered,
1644 .pullup = dwc3_gadget_pullup,
1645 .udc_start = dwc3_gadget_start,
1646 .udc_stop = dwc3_gadget_stop,
1649 /* -------------------------------------------------------------------------- */
1651 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1652 u8 num, u32 direction)
1654 struct dwc3_ep *dep;
1657 for (i = 0; i < num; i++) {
1658 u8 epnum = (i << 1) | (!!direction);
1660 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1665 dep->number = epnum;
1666 dep->direction = !!direction;
1667 dwc->eps[epnum] = dep;
1669 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1670 (epnum & 1) ? "in" : "out");
1672 dep->endpoint.name = dep->name;
1674 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1676 if (epnum == 0 || epnum == 1) {
1677 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1678 dep->endpoint.maxburst = 1;
1679 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1681 dwc->gadget.ep0 = &dep->endpoint;
1685 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1686 dep->endpoint.max_streams = 15;
1687 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1688 list_add_tail(&dep->endpoint.ep_list,
1689 &dwc->gadget.ep_list);
1691 ret = dwc3_alloc_trb_pool(dep);
1696 INIT_LIST_HEAD(&dep->request_list);
1697 INIT_LIST_HEAD(&dep->req_queued);
1703 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1707 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1709 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1711 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1715 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1717 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1724 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1726 struct dwc3_ep *dep;
1729 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1730 dep = dwc->eps[epnum];
1734 * Physical endpoints 0 and 1 are special; they form the
1735 * bi-directional USB endpoint 0.
1737 * For those two physical endpoints, we don't allocate a TRB
1738 * pool nor do we add them the endpoints list. Due to that, we
1739 * shouldn't do these two operations otherwise we would end up
1740 * with all sorts of bugs when removing dwc3.ko.
1742 if (epnum != 0 && epnum != 1) {
1743 dwc3_free_trb_pool(dep);
1744 list_del(&dep->endpoint.ep_list);
1751 /* -------------------------------------------------------------------------- */
1753 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1754 struct dwc3_request *req, struct dwc3_trb *trb,
1755 const struct dwc3_event_depevt *event, int status)
1758 unsigned int s_pkt = 0;
1759 unsigned int trb_status;
1761 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1763 * We continue despite the error. There is not much we
1764 * can do. If we don't clean it up we loop forever. If
1765 * we skip the TRB then it gets overwritten after a
1766 * while since we use them in a ring buffer. A BUG()
1767 * would help. Lets hope that if this occurs, someone
1768 * fixes the root cause instead of looking away :)
1770 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1772 count = trb->size & DWC3_TRB_SIZE_MASK;
1774 if (dep->direction) {
1776 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1777 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1778 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1781 * If missed isoc occurred and there is
1782 * no request queued then issue END
1783 * TRANSFER, so that core generates
1784 * next xfernotready and we will issue
1785 * a fresh START TRANSFER.
1786 * If there are still queued request
1787 * then wait, do not issue either END
1788 * or UPDATE TRANSFER, just attach next
1789 * request in request_list during
1790 * giveback.If any future queued request
1791 * is successfully transferred then we
1792 * will issue UPDATE TRANSFER for all
1793 * request in the request_list.
1795 dep->flags |= DWC3_EP_MISSED_ISOC;
1797 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1799 status = -ECONNRESET;
1802 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1805 if (count && (event->status & DEPEVT_STATUS_SHORT))
1810 * We assume here we will always receive the entire data block
1811 * which we should receive. Meaning, if we program RX to
1812 * receive 4K but we receive only 2K, we assume that's all we
1813 * should receive and we simply bounce the request back to the
1814 * gadget driver for further processing.
1816 req->request.actual += req->request.length - count;
1819 if ((event->status & DEPEVT_STATUS_LST) &&
1820 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1821 DWC3_TRB_CTRL_HWO)))
1823 if ((event->status & DEPEVT_STATUS_IOC) &&
1824 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1829 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1830 const struct dwc3_event_depevt *event, int status)
1832 struct dwc3_request *req;
1833 struct dwc3_trb *trb;
1839 req = next_request(&dep->req_queued);
1846 slot = req->start_slot + i;
1847 if ((slot == DWC3_TRB_NUM - 1) &&
1848 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1850 slot %= DWC3_TRB_NUM;
1851 trb = &dep->trb_pool[slot];
1853 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1857 }while (++i < req->request.num_mapped_sgs);
1859 dwc3_gadget_giveback(dep, req, status);
1865 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1866 list_empty(&dep->req_queued)) {
1867 if (list_empty(&dep->request_list)) {
1869 * If there is no entry in request list then do
1870 * not issue END TRANSFER now. Just set PENDING
1871 * flag, so that END TRANSFER is issued when an
1872 * entry is added into request list.
1874 dep->flags = DWC3_EP_PENDING_REQUEST;
1876 dwc3_stop_active_transfer(dwc, dep->number, true);
1877 dep->flags = DWC3_EP_ENABLED;
1885 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1886 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1888 unsigned status = 0;
1891 if (event->status & DEPEVT_STATUS_BUSERR)
1892 status = -ECONNRESET;
1894 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1896 dep->flags &= ~DWC3_EP_BUSY;
1899 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1900 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1902 if (dwc->revision < DWC3_REVISION_183A) {
1906 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1909 if (!(dep->flags & DWC3_EP_ENABLED))
1912 if (!list_empty(&dep->req_queued))
1916 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1918 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1924 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1925 const struct dwc3_event_depevt *event)
1927 struct dwc3_ep *dep;
1928 u8 epnum = event->endpoint_number;
1930 dep = dwc->eps[epnum];
1932 if (!(dep->flags & DWC3_EP_ENABLED))
1935 if (epnum == 0 || epnum == 1) {
1936 dwc3_ep0_interrupt(dwc, event);
1940 switch (event->endpoint_event) {
1941 case DWC3_DEPEVT_XFERCOMPLETE:
1942 dep->resource_index = 0;
1944 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1945 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1950 dwc3_endpoint_transfer_complete(dwc, dep, event);
1952 case DWC3_DEPEVT_XFERINPROGRESS:
1953 dwc3_endpoint_transfer_complete(dwc, dep, event);
1955 case DWC3_DEPEVT_XFERNOTREADY:
1956 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1957 dwc3_gadget_start_isoc(dwc, dep, event);
1961 dev_vdbg(dwc->dev, "%s: reason %s\n",
1962 dep->name, event->status &
1963 DEPEVT_STATUS_TRANSFER_ACTIVE
1965 : "Transfer Not Active");
1967 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1968 if (!ret || ret == -EBUSY)
1971 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1976 case DWC3_DEPEVT_STREAMEVT:
1977 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1978 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1983 switch (event->status) {
1984 case DEPEVT_STREAMEVT_FOUND:
1985 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1989 case DEPEVT_STREAMEVT_NOTFOUND:
1992 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1995 case DWC3_DEPEVT_RXTXFIFOEVT:
1996 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1998 case DWC3_DEPEVT_EPCMDCMPLT:
1999 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
2004 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2006 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2007 spin_unlock(&dwc->lock);
2008 dwc->gadget_driver->disconnect(&dwc->gadget);
2009 spin_lock(&dwc->lock);
2013 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2015 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2016 spin_unlock(&dwc->lock);
2017 dwc->gadget_driver->suspend(&dwc->gadget);
2018 spin_lock(&dwc->lock);
2022 static void dwc3_resume_gadget(struct dwc3 *dwc)
2024 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2025 spin_unlock(&dwc->lock);
2026 dwc->gadget_driver->resume(&dwc->gadget);
2030 static void dwc3_reset_gadget(struct dwc3 *dwc)
2032 if (!dwc->gadget_driver)
2035 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2036 spin_unlock(&dwc->lock);
2037 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2038 spin_lock(&dwc->lock);
2042 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2044 struct dwc3_ep *dep;
2045 struct dwc3_gadget_ep_cmd_params params;
2049 dep = dwc->eps[epnum];
2051 if (!dep->resource_index)
2055 * NOTICE: We are violating what the Databook says about the
2056 * EndTransfer command. Ideally we would _always_ wait for the
2057 * EndTransfer Command Completion IRQ, but that's causing too
2058 * much trouble synchronizing between us and gadget driver.
2060 * We have discussed this with the IP Provider and it was
2061 * suggested to giveback all requests here, but give HW some
2062 * extra time to synchronize with the interconnect. We're using
2063 * an arbitraty 100us delay for that.
2065 * Note also that a similar handling was tested by Synopsys
2066 * (thanks a lot Paul) and nothing bad has come out of it.
2067 * In short, what we're doing is:
2069 * - Issue EndTransfer WITH CMDIOC bit set
2073 cmd = DWC3_DEPCMD_ENDTRANSFER;
2074 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2075 cmd |= DWC3_DEPCMD_CMDIOC;
2076 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2077 memset(¶ms, 0, sizeof(params));
2078 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2080 dep->resource_index = 0;
2081 dep->flags &= ~DWC3_EP_BUSY;
2085 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2089 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2090 struct dwc3_ep *dep;
2092 dep = dwc->eps[epnum];
2096 if (!(dep->flags & DWC3_EP_ENABLED))
2099 dwc3_remove_requests(dwc, dep);
2103 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2107 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2108 struct dwc3_ep *dep;
2109 struct dwc3_gadget_ep_cmd_params params;
2112 dep = dwc->eps[epnum];
2116 if (!(dep->flags & DWC3_EP_STALL))
2119 dep->flags &= ~DWC3_EP_STALL;
2121 memset(¶ms, 0, sizeof(params));
2122 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2123 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2128 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2132 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2133 reg &= ~DWC3_DCTL_INITU1ENA;
2134 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2136 reg &= ~DWC3_DCTL_INITU2ENA;
2137 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2139 dwc3_disconnect_gadget(dwc);
2140 dwc->start_config_issued = false;
2142 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2143 dwc->setup_packet_pending = false;
2144 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2147 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2152 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2153 * would cause a missing Disconnect Event if there's a
2154 * pending Setup Packet in the FIFO.
2156 * There's no suggested workaround on the official Bug
2157 * report, which states that "unless the driver/application
2158 * is doing any special handling of a disconnect event,
2159 * there is no functional issue".
2161 * Unfortunately, it turns out that we _do_ some special
2162 * handling of a disconnect event, namely complete all
2163 * pending transfers, notify gadget driver of the
2164 * disconnection, and so on.
2166 * Our suggested workaround is to follow the Disconnect
2167 * Event steps here, instead, based on a setup_packet_pending
2168 * flag. Such flag gets set whenever we have a XferNotReady
2169 * event on EP0 and gets cleared on XferComplete for the
2174 * STAR#9000466709: RTL: Device : Disconnect event not
2175 * generated if setup packet pending in FIFO
2177 if (dwc->revision < DWC3_REVISION_188A) {
2178 if (dwc->setup_packet_pending)
2179 dwc3_gadget_disconnect_interrupt(dwc);
2182 dwc3_reset_gadget(dwc);
2184 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2185 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2186 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2187 dwc->test_mode = false;
2189 dwc3_stop_active_transfers(dwc);
2190 dwc3_clear_stall_all_ep(dwc);
2191 dwc->start_config_issued = false;
2193 /* Reset device address to zero */
2194 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2195 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2196 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2199 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2202 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2205 * We change the clock only at SS but I dunno why I would want to do
2206 * this. Maybe it becomes part of the power saving plan.
2209 if (speed != DWC3_DSTS_SUPERSPEED)
2213 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2214 * each time on Connect Done.
2219 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2220 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2221 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2224 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2226 struct dwc3_ep *dep;
2231 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2232 speed = reg & DWC3_DSTS_CONNECTSPD;
2235 dwc3_update_ram_clk_sel(dwc, speed);
2238 case DWC3_DCFG_SUPERSPEED:
2240 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2241 * would cause a missing USB3 Reset event.
2243 * In such situations, we should force a USB3 Reset
2244 * event by calling our dwc3_gadget_reset_interrupt()
2249 * STAR#9000483510: RTL: SS : USB3 reset event may
2250 * not be generated always when the link enters poll
2252 if (dwc->revision < DWC3_REVISION_190A)
2253 dwc3_gadget_reset_interrupt(dwc);
2255 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2256 dwc->gadget.ep0->maxpacket = 512;
2257 dwc->gadget.speed = USB_SPEED_SUPER;
2259 case DWC3_DCFG_HIGHSPEED:
2260 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2261 dwc->gadget.ep0->maxpacket = 64;
2262 dwc->gadget.speed = USB_SPEED_HIGH;
2264 case DWC3_DCFG_FULLSPEED2:
2265 case DWC3_DCFG_FULLSPEED1:
2266 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2267 dwc->gadget.ep0->maxpacket = 64;
2268 dwc->gadget.speed = USB_SPEED_FULL;
2270 case DWC3_DCFG_LOWSPEED:
2271 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2272 dwc->gadget.ep0->maxpacket = 8;
2273 dwc->gadget.speed = USB_SPEED_LOW;
2277 /* Enable USB2 LPM Capability */
2279 if ((dwc->revision > DWC3_REVISION_194A)
2280 && (speed != DWC3_DCFG_SUPERSPEED)) {
2281 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2282 reg |= DWC3_DCFG_LPM_CAP;
2283 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2285 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2286 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2288 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2291 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2292 * DCFG.LPMCap is set, core responses with an ACK and the
2293 * BESL value in the LPM token is less than or equal to LPM
2296 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2297 && dwc->has_lpm_erratum,
2298 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2300 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2301 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2303 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2305 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2306 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2307 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2311 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2314 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2319 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2322 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2327 * Configure PHY via GUSB3PIPECTLn if required.
2329 * Update GTXFIFOSIZn
2331 * In both cases reset values should be sufficient.
2335 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2338 * TODO take core out of low power mode when that's
2342 dwc->gadget_driver->resume(&dwc->gadget);
2345 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2346 unsigned int evtinfo)
2348 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2349 unsigned int pwropt;
2352 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2353 * Hibernation mode enabled which would show up when device detects
2354 * host-initiated U3 exit.
2356 * In that case, device will generate a Link State Change Interrupt
2357 * from U3 to RESUME which is only necessary if Hibernation is
2360 * There are no functional changes due to such spurious event and we
2361 * just need to ignore it.
2365 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2368 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2369 if ((dwc->revision < DWC3_REVISION_250A) &&
2370 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2371 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2372 (next == DWC3_LINK_STATE_RESUME)) {
2373 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2379 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2380 * on the link partner, the USB session might do multiple entry/exit
2381 * of low power states before a transfer takes place.
2383 * Due to this problem, we might experience lower throughput. The
2384 * suggested workaround is to disable DCTL[12:9] bits if we're
2385 * transitioning from U1/U2 to U0 and enable those bits again
2386 * after a transfer completes and there are no pending transfers
2387 * on any of the enabled endpoints.
2389 * This is the first half of that workaround.
2393 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2394 * core send LGO_Ux entering U0
2396 if (dwc->revision < DWC3_REVISION_183A) {
2397 if (next == DWC3_LINK_STATE_U0) {
2401 switch (dwc->link_state) {
2402 case DWC3_LINK_STATE_U1:
2403 case DWC3_LINK_STATE_U2:
2404 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2405 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2406 | DWC3_DCTL_ACCEPTU2ENA
2407 | DWC3_DCTL_INITU1ENA
2408 | DWC3_DCTL_ACCEPTU1ENA);
2411 dwc->u1u2 = reg & u1u2;
2415 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2425 case DWC3_LINK_STATE_U1:
2426 if (dwc->speed == USB_SPEED_SUPER)
2427 dwc3_suspend_gadget(dwc);
2429 case DWC3_LINK_STATE_U2:
2430 case DWC3_LINK_STATE_U3:
2431 dwc3_suspend_gadget(dwc);
2433 case DWC3_LINK_STATE_RESUME:
2434 dwc3_resume_gadget(dwc);
2441 dwc->link_state = next;
2444 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2445 unsigned int evtinfo)
2447 unsigned int is_ss = evtinfo & BIT(4);
2450 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2451 * have a known issue which can cause USB CV TD.9.23 to fail
2454 * Because of this issue, core could generate bogus hibernation
2455 * events which SW needs to ignore.
2459 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2460 * Device Fallback from SuperSpeed
2462 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2465 /* enter hibernation here */
2468 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2469 const struct dwc3_event_devt *event)
2471 switch (event->type) {
2472 case DWC3_DEVICE_EVENT_DISCONNECT:
2473 dwc3_gadget_disconnect_interrupt(dwc);
2475 case DWC3_DEVICE_EVENT_RESET:
2476 dwc3_gadget_reset_interrupt(dwc);
2478 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2479 dwc3_gadget_conndone_interrupt(dwc);
2481 case DWC3_DEVICE_EVENT_WAKEUP:
2482 dwc3_gadget_wakeup_interrupt(dwc);
2484 case DWC3_DEVICE_EVENT_HIBER_REQ:
2485 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2486 "unexpected hibernation event\n"))
2489 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2491 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2492 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2494 case DWC3_DEVICE_EVENT_EOPF:
2495 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2497 case DWC3_DEVICE_EVENT_SOF:
2498 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2500 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2501 dev_vdbg(dwc->dev, "Erratic Error\n");
2503 case DWC3_DEVICE_EVENT_CMD_CMPL:
2504 dev_vdbg(dwc->dev, "Command Complete\n");
2506 case DWC3_DEVICE_EVENT_OVERFLOW:
2507 dev_vdbg(dwc->dev, "Overflow\n");
2510 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2514 static void dwc3_process_event_entry(struct dwc3 *dwc,
2515 const union dwc3_event *event)
2517 /* Endpoint IRQ, handle it and return early */
2518 if (event->type.is_devspec == 0) {
2520 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2523 switch (event->type.type) {
2524 case DWC3_EVENT_TYPE_DEV:
2525 dwc3_gadget_interrupt(dwc, &event->devt);
2527 /* REVISIT what to do with Carkit and I2C events ? */
2529 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2533 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2535 struct dwc3_event_buffer *evt;
2536 irqreturn_t ret = IRQ_NONE;
2540 evt = dwc->ev_buffs[buf];
2543 if (!(evt->flags & DWC3_EVENT_PENDING))
2547 union dwc3_event event;
2549 event.raw = *(u32 *) (evt->buf + evt->lpos);
2551 dwc3_process_event_entry(dwc, &event);
2554 * FIXME we wrap around correctly to the next entry as
2555 * almost all entries are 4 bytes in size. There is one
2556 * entry which has 12 bytes which is a regular entry
2557 * followed by 8 bytes data. ATM I don't know how
2558 * things are organized if we get next to the a
2559 * boundary so I worry about that once we try to handle
2562 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2565 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2569 evt->flags &= ~DWC3_EVENT_PENDING;
2572 /* Unmask interrupt */
2573 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2574 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2575 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2580 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2582 struct dwc3 *dwc = _dwc;
2583 unsigned long flags;
2584 irqreturn_t ret = IRQ_NONE;
2587 spin_lock_irqsave(&dwc->lock, flags);
2589 for (i = 0; i < dwc->num_event_buffers; i++)
2590 ret |= dwc3_process_event_buf(dwc, i);
2592 spin_unlock_irqrestore(&dwc->lock, flags);
2597 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2599 struct dwc3_event_buffer *evt;
2603 evt = dwc->ev_buffs[buf];
2605 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2606 count &= DWC3_GEVNTCOUNT_MASK;
2611 evt->flags |= DWC3_EVENT_PENDING;
2613 /* Mask interrupt */
2614 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2615 reg |= DWC3_GEVNTSIZ_INTMASK;
2616 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2618 return IRQ_WAKE_THREAD;
2621 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2623 struct dwc3 *dwc = _dwc;
2625 irqreturn_t ret = IRQ_NONE;
2627 spin_lock(&dwc->lock);
2629 for (i = 0; i < dwc->num_event_buffers; i++) {
2632 status = dwc3_check_event_buf(dwc, i);
2633 if (status == IRQ_WAKE_THREAD)
2637 spin_unlock(&dwc->lock);
2643 * dwc3_gadget_init - Initializes gadget related registers
2644 * @dwc: pointer to our controller context structure
2646 * Returns 0 on success otherwise negative errno.
2648 int dwc3_gadget_init(struct dwc3 *dwc)
2652 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2653 &dwc->ctrl_req_addr, GFP_KERNEL);
2654 if (!dwc->ctrl_req) {
2655 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2660 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2661 &dwc->ep0_trb_addr, GFP_KERNEL);
2662 if (!dwc->ep0_trb) {
2663 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2668 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2669 if (!dwc->setup_buf) {
2674 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2675 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2677 if (!dwc->ep0_bounce) {
2678 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2683 dwc->gadget.ops = &dwc3_gadget_ops;
2684 dwc->gadget.max_speed = USB_SPEED_SUPER;
2685 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2686 dwc->gadget.sg_supported = true;
2687 dwc->gadget.name = "dwc3-gadget";
2690 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2693 dwc->gadget.quirk_ep_out_aligned_size = true;
2696 * REVISIT: Here we should clear all pending IRQs to be
2697 * sure we're starting from a well known location.
2700 ret = dwc3_gadget_init_endpoints(dwc);
2704 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2706 dev_err(dwc->dev, "failed to register udc\n");
2713 dwc3_gadget_free_endpoints(dwc);
2714 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2715 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2718 kfree(dwc->setup_buf);
2721 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2722 dwc->ep0_trb, dwc->ep0_trb_addr);
2725 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2726 dwc->ctrl_req, dwc->ctrl_req_addr);
2732 /* -------------------------------------------------------------------------- */
2734 void dwc3_gadget_exit(struct dwc3 *dwc)
2736 usb_del_gadget_udc(&dwc->gadget);
2738 dwc3_gadget_free_endpoints(dwc);
2740 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2741 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2743 kfree(dwc->setup_buf);
2745 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2746 dwc->ep0_trb, dwc->ep0_trb_addr);
2748 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2749 dwc->ctrl_req, dwc->ctrl_req_addr);
2752 int dwc3_gadget_suspend(struct dwc3 *dwc)
2754 if (dwc->pullups_connected) {
2755 dwc3_gadget_disable_irq(dwc);
2756 dwc3_gadget_run_stop(dwc, true, true);
2759 __dwc3_gadget_ep_disable(dwc->eps[0]);
2760 __dwc3_gadget_ep_disable(dwc->eps[1]);
2762 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2767 int dwc3_gadget_resume(struct dwc3 *dwc)
2769 struct dwc3_ep *dep;
2772 /* Start with SuperSpeed Default */
2773 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2776 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2782 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2787 /* begin to receive SETUP packets */
2788 dwc->ep0state = EP0_SETUP_PHASE;
2789 dwc3_ep0_out_start(dwc);
2791 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2793 if (dwc->pullups_connected) {
2794 dwc3_gadget_enable_irq(dwc);
2795 dwc3_gadget_run_stop(dwc, true, false);
2801 __dwc3_gadget_ep_disable(dwc->eps[0]);