2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <linux/mii.h>
25 #include "usb_ether.h"
29 /* ASIX AX8817X based USB 2.0 Ethernet Devices */
31 #define AX_CMD_SET_SW_MII 0x06
32 #define AX_CMD_READ_MII_REG 0x07
33 #define AX_CMD_WRITE_MII_REG 0x08
34 #define AX_CMD_SET_HW_MII 0x0a
35 #define AX_CMD_READ_EEPROM 0x0b
36 #define AX_CMD_READ_RX_CTL 0x0f
37 #define AX_CMD_WRITE_RX_CTL 0x10
38 #define AX_CMD_WRITE_IPG0 0x12
39 #define AX_CMD_READ_NODE_ID 0x13
40 #define AX_CMD_WRITE_NODE_ID 0x14
41 #define AX_CMD_READ_PHY_ID 0x19
42 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
43 #define AX_CMD_WRITE_GPIOS 0x1f
44 #define AX_CMD_SW_RESET 0x20
45 #define AX_CMD_SW_PHY_SELECT 0x22
47 #define AX_SWRESET_CLEAR 0x00
48 #define AX_SWRESET_PRTE 0x04
49 #define AX_SWRESET_PRL 0x08
50 #define AX_SWRESET_IPRL 0x20
51 #define AX_SWRESET_IPPD 0x40
53 #define AX88772_IPG0_DEFAULT 0x15
54 #define AX88772_IPG1_DEFAULT 0x0c
55 #define AX88772_IPG2_DEFAULT 0x12
57 /* AX88772 & AX88178 Medium Mode Register */
58 #define AX_MEDIUM_PF 0x0080
59 #define AX_MEDIUM_JFE 0x0040
60 #define AX_MEDIUM_TFC 0x0020
61 #define AX_MEDIUM_RFC 0x0010
62 #define AX_MEDIUM_ENCK 0x0008
63 #define AX_MEDIUM_AC 0x0004
64 #define AX_MEDIUM_FD 0x0002
65 #define AX_MEDIUM_GM 0x0001
66 #define AX_MEDIUM_SM 0x1000
67 #define AX_MEDIUM_SBP 0x0800
68 #define AX_MEDIUM_PS 0x0200
69 #define AX_MEDIUM_RE 0x0100
71 #define AX88178_MEDIUM_DEFAULT \
72 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
73 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
76 #define AX88772_MEDIUM_DEFAULT \
77 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
78 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
79 AX_MEDIUM_AC | AX_MEDIUM_RE)
81 /* AX88772 & AX88178 RX_CTL values */
82 #define AX_RX_CTL_SO 0x0080
83 #define AX_RX_CTL_AB 0x0008
85 #define AX_DEFAULT_RX_CTL \
86 (AX_RX_CTL_SO | AX_RX_CTL_AB)
89 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
90 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
91 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
94 #define ASIX_BASE_NAME "asx"
95 #define USB_CTRL_SET_TIMEOUT 5000
96 #define USB_CTRL_GET_TIMEOUT 5000
97 #define USB_BULK_SEND_TIMEOUT 5000
98 #define USB_BULK_RECV_TIMEOUT 5000
100 #define AX_RX_URB_SIZE 2048
101 #define PHY_CONNECT_TIMEOUT 5000
103 /* asix_flags defines */
105 #define FLAG_TYPE_AX88172 (1U << 0)
106 #define FLAG_TYPE_AX88772 (1U << 1)
107 #define FLAG_EEPROM_MAC (1U << 2) /* initial mac address in eeprom */
110 static int curr_eth_dev; /* index for name of next device detected */
113 struct asix_private {
118 * Asix infrastructure commands
120 static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
121 u16 size, void *data)
125 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
126 "size=%d\n", cmd, value, index, size);
128 len = usb_control_msg(
130 usb_sndctrlpipe(dev->pusb_dev, 0),
132 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
137 USB_CTRL_SET_TIMEOUT);
139 return len == size ? 0 : -1;
142 static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
143 u16 size, void *data)
147 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
148 cmd, value, index, size);
150 len = usb_control_msg(
152 usb_rcvctrlpipe(dev->pusb_dev, 0),
154 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
159 USB_CTRL_GET_TIMEOUT);
160 return len == size ? 0 : -1;
163 static inline int asix_set_sw_mii(struct ueth_data *dev)
167 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
169 debug("Failed to enable software MII access\n");
173 static inline int asix_set_hw_mii(struct ueth_data *dev)
177 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
179 debug("Failed to enable hardware MII access\n");
183 static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
185 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
187 asix_set_sw_mii(dev);
188 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
189 asix_set_hw_mii(dev);
191 debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
192 phy_id, loc, le16_to_cpu(*res));
194 return le16_to_cpu(*res);
198 asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
200 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
201 *res = cpu_to_le16(val);
203 debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
205 asix_set_sw_mii(dev);
206 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
207 asix_set_hw_mii(dev);
211 * Asix "high level" commands
213 static int asix_sw_reset(struct ueth_data *dev, u8 flags)
217 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
219 debug("Failed to send software reset: %02x\n", ret);
226 static inline int asix_get_phy_addr(struct ueth_data *dev)
228 ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
230 int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
232 debug("asix_get_phy_addr()\n");
235 debug("Error reading PHYID register: %02x\n", ret);
238 debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
245 static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
249 debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
250 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
253 debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
259 static u16 asix_read_rx_ctl(struct ueth_data *dev)
261 ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
263 int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
266 debug("Error reading RX_CTL register: %02x\n", ret);
268 ret = le16_to_cpu(*v);
272 static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
276 debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
277 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
279 debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
285 static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
289 debug("asix_write_gpio() - value = 0x%04x\n", value);
290 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
292 debug("Failed to write GPIO value 0x%04x: %02x\n",
296 udelay(sleep * 1000);
301 static int asix_write_hwaddr(struct eth_device *eth)
303 struct ueth_data *dev = (struct ueth_data *)eth->priv;
305 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
307 memcpy(buf, eth->enetaddr, ETH_ALEN);
309 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
311 debug("Failed to set MAC address: %02x\n", ret);
321 * mii_nway_restart - restart NWay (autonegotiation) for this interface
323 * Returns 0 on success, negative on error.
325 static int mii_nway_restart(struct ueth_data *dev)
330 /* if autoneg is off, it's an error */
331 bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
333 if (bmcr & BMCR_ANENABLE) {
334 bmcr |= BMCR_ANRESTART;
335 asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
342 static int asix_read_mac(struct eth_device *eth)
344 struct ueth_data *dev = (struct ueth_data *)eth->priv;
345 struct asix_private *priv = (struct asix_private *)dev->dev_priv;
347 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
349 if (priv->flags & FLAG_EEPROM_MAC) {
350 for (i = 0; i < (ETH_ALEN >> 1); i++) {
351 if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
352 0x04 + i, 0, 2, buf) < 0) {
353 debug("Failed to read SROM address 04h.\n");
356 memcpy((eth->enetaddr + i * 2), buf, 2);
359 if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf)
361 debug("Failed to read MAC address.\n");
364 memcpy(eth->enetaddr, buf, ETH_ALEN);
370 static int asix_basic_reset(struct ueth_data *dev)
375 if (asix_write_gpio(dev,
376 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
379 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
380 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
381 if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
382 embd_phy, 0, 0, NULL) < 0) {
383 debug("Select PHY #1 failed\n");
387 if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
390 if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
394 if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
397 if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
401 rx_ctl = asix_read_rx_ctl(dev);
402 debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
403 if (asix_write_rx_ctl(dev, 0x0000) < 0)
406 rx_ctl = asix_read_rx_ctl(dev);
407 debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
415 static int asix_init(struct eth_device *eth, bd_t *bd)
417 struct ueth_data *dev = (struct ueth_data *)eth->priv;
419 #define TIMEOUT_RESOLUTION 50 /* ms */
422 debug("** %s()\n", __func__);
424 dev->phy_id = asix_get_phy_addr(dev);
426 debug("Failed to read phy id\n");
428 if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0)
431 if (asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL) < 0)
434 asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
435 asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
436 ADVERTISE_ALL | ADVERTISE_CSMA);
437 mii_nway_restart(dev);
439 if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
442 if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
443 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
444 AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
445 debug("Write IPG,IPG1,IPG2 failed\n");
449 if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
453 link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
455 if (!link_detected) {
457 printf("Waiting for Ethernet connection... ");
458 udelay(TIMEOUT_RESOLUTION * 1000);
459 timeout += TIMEOUT_RESOLUTION;
461 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
466 printf("unable to connect.\n");
475 static int asix_send(struct eth_device *eth, void *packet, int length)
477 struct ueth_data *dev = (struct ueth_data *)eth->priv;
481 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
482 PKTSIZE + sizeof(packet_len));
484 debug("** %s(), len %d\n", __func__, length);
486 packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
487 cpu_to_le32s(&packet_len);
489 memcpy(msg, &packet_len, sizeof(packet_len));
490 memcpy(msg + sizeof(packet_len), (void *)packet, length);
494 err = usb_bulk_msg(dev->pusb_dev,
495 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
497 length + sizeof(packet_len),
499 USB_BULK_SEND_TIMEOUT);
500 debug("Tx: len = %u, actual = %u, err = %d\n",
501 length + sizeof(packet_len), actual_len, err);
506 static int asix_recv(struct eth_device *eth)
508 struct ueth_data *dev = (struct ueth_data *)eth->priv;
509 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
510 unsigned char *buf_ptr;
515 debug("** %s()\n", __func__);
517 err = usb_bulk_msg(dev->pusb_dev,
518 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
522 USB_BULK_RECV_TIMEOUT);
523 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
526 debug("Rx: failed to receive\n");
529 if (actual_len > AX_RX_URB_SIZE) {
530 debug("Rx: received too many bytes %d\n", actual_len);
535 while (actual_len > 0) {
537 * 1st 4 bytes contain the length of the actual data as two
538 * complementary 16-bit words. Extract the length of the data.
540 if (actual_len < sizeof(packet_len)) {
541 debug("Rx: incomplete packet length\n");
544 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
545 le32_to_cpus(&packet_len);
546 if (((packet_len >> 16) ^ 0xffff) != (packet_len & 0xffff)) {
547 debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
548 packet_len, (packet_len >> 16) ^ 0xffff,
549 packet_len & 0xffff);
552 packet_len = packet_len & 0xffff;
553 if (packet_len > actual_len - sizeof(packet_len)) {
554 debug("Rx: too large packet: %d\n", packet_len);
558 /* Notify net stack */
559 NetReceive(buf_ptr + sizeof(packet_len), packet_len);
561 /* Adjust for next iteration. Packets are padded to 16-bits */
564 actual_len -= sizeof(packet_len) + packet_len;
565 buf_ptr += sizeof(packet_len) + packet_len;
571 static void asix_halt(struct eth_device *eth)
573 debug("** %s()\n", __func__);
577 * Asix probing functions
579 void asix_eth_before_probe(void)
585 unsigned short vendor;
586 unsigned short product;
590 static const struct asix_dongle const asix_dongles[] = {
591 { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
592 { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
593 /* Cables-to-Go USB Ethernet Adapter */
594 { 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
595 { 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
596 { 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
597 { 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
598 { 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
599 { 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
600 /* DLink DUB-E100 H/W Ver B1 Alternate */
601 { 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
602 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
605 /* Probe to see if a new device is actually an asix device */
606 int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
607 struct ueth_data *ss)
609 struct usb_interface *iface;
610 struct usb_interface_descriptor *iface_desc;
613 /* let's examine the device now */
614 iface = &dev->config.if_desc[ifnum];
615 iface_desc = &dev->config.if_desc[ifnum].desc;
617 for (i = 0; asix_dongles[i].vendor != 0; i++) {
618 if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
619 dev->descriptor.idProduct == asix_dongles[i].product)
620 /* Found a supported dongle */
624 if (asix_dongles[i].vendor == 0)
627 memset(ss, 0, sizeof(struct ueth_data));
629 /* At this point, we know we've got a live one */
630 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
631 dev->descriptor.idVendor, dev->descriptor.idProduct);
633 /* Initialize the ueth_data structure with some useful info */
636 ss->subclass = iface_desc->bInterfaceSubClass;
637 ss->protocol = iface_desc->bInterfaceProtocol;
639 /* alloc driver private */
640 ss->dev_priv = calloc(1, sizeof(struct asix_private));
644 ((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
647 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
648 * int. We will ignore any others.
650 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
651 /* is it an BULK endpoint? */
652 if ((iface->ep_desc[i].bmAttributes &
653 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
654 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
655 ss->ep_in = iface->ep_desc[i].bEndpointAddress &
656 USB_ENDPOINT_NUMBER_MASK;
659 iface->ep_desc[i].bEndpointAddress &
660 USB_ENDPOINT_NUMBER_MASK;
663 /* is it an interrupt endpoint? */
664 if ((iface->ep_desc[i].bmAttributes &
665 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
666 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
667 USB_ENDPOINT_NUMBER_MASK;
668 ss->irqinterval = iface->ep_desc[i].bInterval;
671 debug("Endpoints In %d Out %d Int %d\n",
672 ss->ep_in, ss->ep_out, ss->ep_int);
674 /* Do some basic sanity checks, and bail if we find a problem */
675 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
676 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
677 debug("Problems with device\n");
680 dev->privptr = (void *)ss;
684 int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
685 struct eth_device *eth)
687 struct asix_private *priv = (struct asix_private *)ss->dev_priv;
690 debug("%s: missing parameter.\n", __func__);
693 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
694 eth->init = asix_init;
695 eth->send = asix_send;
696 eth->recv = asix_recv;
697 eth->halt = asix_halt;
698 if (!(priv->flags & FLAG_TYPE_AX88172))
699 eth->write_hwaddr = asix_write_hwaddr;
702 if (asix_basic_reset(ss))
705 /* Get the MAC address */
706 if (asix_read_mac(eth))
708 debug("MAC %pM\n", eth->enetaddr);