2 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
13 #include <usb/lin_gadget_compat.h>
14 #include <linux/mii.h>
15 #include <linux/bitops.h>
16 #include "usb_ether.h"
21 static int curr_eth_dev; /* index for name of next device detected */
24 unsigned short vendor;
25 unsigned short product;
28 static const struct r8152_dongle const r8152_dongles[] = {
55 struct r8152_version {
57 unsigned short version;
61 static const struct r8152_version const r8152_versions[] = {
62 { 0x4c00, RTL_VER_01, 0 },
63 { 0x4c10, RTL_VER_02, 0 },
64 { 0x5c00, RTL_VER_03, 1 },
65 { 0x5c10, RTL_VER_04, 1 },
66 { 0x5c20, RTL_VER_05, 1 },
67 { 0x5c30, RTL_VER_06, 1 },
68 { 0x4800, RTL_VER_07, 0 },
72 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
74 return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
75 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
76 value, index, data, size, 500);
80 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
82 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
83 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
84 value, index, data, size, 500);
87 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
94 /* both size and index must be 4 bytes align */
95 if ((size & 3) || !size || (index & 3) || !data)
98 if (index + size > 0xffff)
102 txsize = min(size, burst_size);
103 ret = get_registers(tp, index, type, txsize, data);
115 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
116 u16 size, void *data, u16 type)
119 u16 byteen_start, byteen_end, byte_en_to_hw;
120 u16 burst_size = 512;
123 /* both size and index must be 4 bytes align */
124 if ((size & 3) || !size || (index & 3) || !data)
127 if (index + size > 0xffff)
130 byteen_start = byteen & BYTE_EN_START_MASK;
131 byteen_end = byteen & BYTE_EN_END_MASK;
133 byte_en_to_hw = byteen_start | (byteen_start << 4);
134 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
146 txsize = min(size, burst_size);
148 ret = set_registers(tp, index,
149 type | BYTE_EN_DWORD,
159 byte_en_to_hw = byteen_end | (byteen_end >> 4);
160 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
168 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
170 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
173 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
175 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
178 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
180 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
183 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
185 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
188 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
192 generic_ocp_read(tp, index, sizeof(data), &data, type);
194 return __le32_to_cpu(data);
197 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
199 __le32 tmp = __cpu_to_le32(data);
201 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
204 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
208 u8 shift = index & 2;
212 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
214 data = __le32_to_cpu(tmp);
215 data >>= (shift * 8);
221 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
225 u16 byen = BYTE_EN_WORD;
226 u8 shift = index & 2;
232 mask <<= (shift * 8);
233 data <<= (shift * 8);
237 tmp = __cpu_to_le32(data);
239 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
242 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
246 u8 shift = index & 3;
250 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
252 data = __le32_to_cpu(tmp);
253 data >>= (shift * 8);
259 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
263 u16 byen = BYTE_EN_BYTE;
264 u8 shift = index & 3;
270 mask <<= (shift * 8);
271 data <<= (shift * 8);
275 tmp = __cpu_to_le32(data);
277 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
280 u16 ocp_reg_read(struct r8152 *tp, u16 addr)
282 u16 ocp_base, ocp_index;
284 ocp_base = addr & 0xf000;
285 if (ocp_base != tp->ocp_base) {
286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
287 tp->ocp_base = ocp_base;
290 ocp_index = (addr & 0x0fff) | 0xb000;
291 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
294 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
296 u16 ocp_base, ocp_index;
298 ocp_base = addr & 0xf000;
299 if (ocp_base != tp->ocp_base) {
300 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
301 tp->ocp_base = ocp_base;
304 ocp_index = (addr & 0x0fff) | 0xb000;
305 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
308 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
310 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
313 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
315 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
318 void sram_write(struct r8152 *tp, u16 addr, u16 data)
320 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
321 ocp_reg_write(tp, OCP_SRAM_DATA, data);
324 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
325 const u32 mask, bool set, unsigned int timeout)
331 val = ocp_reg_read(tp, index);
333 val = ocp_read_dword(tp, type, index);
338 if ((val & mask) == mask)
344 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
345 __func__, index, mask, timeout);
350 static void r8152b_reset_packet_filter(struct r8152 *tp)
354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
355 ocp_data &= ~FMC_FCR_MCU_EN;
356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
357 ocp_data |= FMC_FCR_MCU_EN;
358 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
361 static void rtl8152_wait_fifo_empty(struct r8152 *tp)
365 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
366 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
368 debug("Timeout waiting for FIFO empty\n");
370 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
371 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
373 debug("Timeout waiting for TX empty\n");
376 static void rtl8152_nic_reset(struct r8152 *tp)
381 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
382 ocp_data |= BIST_CTRL_SW_RESET;
383 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
385 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
386 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
388 debug("Timeout waiting for NIC reset\n");
391 static u8 rtl8152_get_speed(struct r8152 *tp)
393 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
396 static void rtl_set_eee_plus(struct r8152 *tp)
400 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
401 ocp_data &= ~EEEP_CR_EEEP_TX;
402 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
405 static void rxdy_gated_en(struct r8152 *tp, bool enable)
409 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
411 ocp_data |= RXDY_GATED_EN;
413 ocp_data &= ~RXDY_GATED_EN;
414 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
417 static void rtl8152_set_rx_mode(struct r8152 *tp)
425 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
427 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
428 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
429 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
432 static int rtl_enable(struct r8152 *tp)
436 r8152b_reset_packet_filter(tp);
438 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
439 ocp_data |= PLA_CR_RE | PLA_CR_TE;
440 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
442 rxdy_gated_en(tp, false);
444 rtl8152_set_rx_mode(tp);
449 static int rtl8152_enable(struct r8152 *tp)
451 rtl_set_eee_plus(tp);
453 return rtl_enable(tp);
456 static void r8153_set_rx_early_timeout(struct r8152 *tp)
458 u32 ocp_data = tp->coalesce / 8;
460 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
463 static void r8153_set_rx_early_size(struct r8152 *tp)
465 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4;
467 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
470 static int rtl8153_enable(struct r8152 *tp)
472 rtl_set_eee_plus(tp);
473 r8153_set_rx_early_timeout(tp);
474 r8153_set_rx_early_size(tp);
476 return rtl_enable(tp);
479 static void rtl_disable(struct r8152 *tp)
483 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
484 ocp_data &= ~RCR_ACPT_ALL;
485 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
487 rxdy_gated_en(tp, true);
489 rtl8152_wait_fifo_empty(tp);
490 rtl8152_nic_reset(tp);
493 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
497 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
499 ocp_data |= POWER_CUT;
501 ocp_data &= ~POWER_CUT;
502 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
504 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
505 ocp_data &= ~RESUME_INDICATE;
506 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
509 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
513 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
515 ocp_data |= CPCR_RX_VLAN;
517 ocp_data &= ~CPCR_RX_VLAN;
518 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
521 static void r8153_u1u2en(struct r8152 *tp, bool enable)
526 memset(u1u2, 0xff, sizeof(u1u2));
528 memset(u1u2, 0x00, sizeof(u1u2));
530 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
533 static void r8153_u2p3en(struct r8152 *tp, bool enable)
537 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
538 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
539 ocp_data |= U2P3_ENABLE;
541 ocp_data &= ~U2P3_ENABLE;
542 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
545 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
549 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
551 ocp_data |= PWR_EN | PHASE2_EN;
553 ocp_data &= ~(PWR_EN | PHASE2_EN);
554 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
556 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
557 ocp_data &= ~PCUT_STATUS;
558 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
561 static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
564 unsigned char enetaddr[8] = {0};
566 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
570 memcpy(macaddr, enetaddr, ETH_ALEN);
574 static void r8152b_disable_aldps(struct r8152 *tp)
576 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
580 static void r8152b_enable_aldps(struct r8152 *tp)
582 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
583 LINKENA | DIS_SDSAVE);
586 static void rtl8152_disable(struct r8152 *tp)
588 r8152b_disable_aldps(tp);
590 r8152b_enable_aldps(tp);
593 static void r8152b_hw_phy_cfg(struct r8152 *tp)
597 data = r8152_mdio_read(tp, MII_BMCR);
598 if (data & BMCR_PDOWN) {
600 r8152_mdio_write(tp, MII_BMCR, data);
606 static void rtl8152_reinit_ll(struct r8152 *tp)
611 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
612 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
614 debug("Timeout waiting for link list ready\n");
616 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
617 ocp_data |= RE_INIT_LL;
618 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
620 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
621 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
623 debug("Timeout waiting for link list ready\n");
626 static void r8152b_exit_oob(struct r8152 *tp)
630 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
631 ocp_data &= ~RCR_ACPT_ALL;
632 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
634 rxdy_gated_en(tp, true);
635 r8152b_hw_phy_cfg(tp);
637 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
638 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
640 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
641 ocp_data &= ~NOW_IS_OOB;
642 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
644 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
645 ocp_data &= ~MCU_BORW_EN;
646 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
648 rtl8152_reinit_ll(tp);
649 rtl8152_nic_reset(tp);
651 /* rx share fifo credit full threshold */
652 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
654 if (tp->udev->speed == USB_SPEED_FULL ||
655 tp->udev->speed == USB_SPEED_LOW) {
656 /* rx share fifo credit near full threshold */
657 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
659 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
662 /* rx share fifo credit near full threshold */
663 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
665 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
669 /* TX share fifo free credit full threshold */
670 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
672 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
673 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
674 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
675 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
677 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
679 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
680 ocp_data |= TCR0_AUTO_FIFO;
681 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
684 static void r8152b_enter_oob(struct r8152 *tp)
688 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
689 ocp_data &= ~NOW_IS_OOB;
690 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
692 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
693 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
694 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
698 rtl8152_reinit_ll(tp);
700 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
702 rtl_rx_vlan_en(tp, false);
704 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
705 ocp_data |= ALDPS_PROXY_MODE;
706 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
708 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
709 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
710 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
712 rxdy_gated_en(tp, false);
714 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
715 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
716 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
719 static void r8153_hw_phy_cfg(struct r8152 *tp)
724 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
725 tp->version == RTL_VER_05)
726 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
728 data = r8152_mdio_read(tp, MII_BMCR);
729 if (data & BMCR_PDOWN) {
731 r8152_mdio_write(tp, MII_BMCR, data);
736 if (tp->version == RTL_VER_03) {
737 data = ocp_reg_read(tp, OCP_EEE_CFG);
738 data &= ~CTAP_SHORT_EN;
739 ocp_reg_write(tp, OCP_EEE_CFG, data);
742 data = ocp_reg_read(tp, OCP_POWER_CFG);
743 data |= EEE_CLKDIV_EN;
744 ocp_reg_write(tp, OCP_POWER_CFG, data);
746 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
747 data |= EN_10M_BGOFF;
748 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
749 data = ocp_reg_read(tp, OCP_POWER_CFG);
750 data |= EN_10M_PLLOFF;
751 ocp_reg_write(tp, OCP_POWER_CFG, data);
752 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
754 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
755 ocp_data |= PFM_PWM_SWITCH;
756 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
758 /* Enable LPF corner auto tune */
759 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
761 /* Adjust 10M Amplitude */
762 sram_write(tp, SRAM_10M_AMP1, 0x00af);
763 sram_write(tp, SRAM_10M_AMP2, 0x0208);
766 static void r8153_first_init(struct r8152 *tp)
770 rxdy_gated_en(tp, true);
772 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
773 ocp_data &= ~RCR_ACPT_ALL;
774 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
776 r8153_hw_phy_cfg(tp);
778 rtl8152_nic_reset(tp);
780 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
781 ocp_data &= ~NOW_IS_OOB;
782 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
784 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
785 ocp_data &= ~MCU_BORW_EN;
786 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
788 rtl8152_reinit_ll(tp);
790 rtl_rx_vlan_en(tp, false);
792 ocp_data = RTL8153_RMS;
793 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
794 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
796 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
797 ocp_data |= TCR0_AUTO_FIFO;
798 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
800 rtl8152_nic_reset(tp);
802 /* rx share fifo credit full threshold */
803 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
804 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
805 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
806 /* TX share fifo free credit full threshold */
807 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
810 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
812 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
813 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
816 static void r8153_enter_oob(struct r8152 *tp)
820 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
821 ocp_data &= ~NOW_IS_OOB;
822 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
826 rtl8152_reinit_ll(tp);
828 ocp_data = RTL8153_RMS;
829 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
831 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
832 ocp_data &= ~TEREDO_WAKE_MASK;
833 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
835 rtl_rx_vlan_en(tp, false);
837 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
838 ocp_data |= ALDPS_PROXY_MODE;
839 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
841 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
842 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
843 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
845 rxdy_gated_en(tp, false);
847 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
848 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
849 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
852 static void r8153_disable_aldps(struct r8152 *tp)
856 data = ocp_reg_read(tp, OCP_POWER_CFG);
858 ocp_reg_write(tp, OCP_POWER_CFG, data);
862 static void rtl8153_disable(struct r8152 *tp)
864 r8153_disable_aldps(tp);
868 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
870 u16 bmcr, anar, gbcr;
872 anar = r8152_mdio_read(tp, MII_ADVERTISE);
873 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
874 ADVERTISE_100HALF | ADVERTISE_100FULL);
875 if (tp->supports_gmii) {
876 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
877 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
882 if (autoneg == AUTONEG_DISABLE) {
883 if (speed == SPEED_10) {
885 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
886 } else if (speed == SPEED_100) {
887 bmcr = BMCR_SPEED100;
888 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
889 } else if (speed == SPEED_1000 && tp->supports_gmii) {
890 bmcr = BMCR_SPEED1000;
891 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
896 if (duplex == DUPLEX_FULL)
897 bmcr |= BMCR_FULLDPLX;
899 if (speed == SPEED_10) {
900 if (duplex == DUPLEX_FULL)
901 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
903 anar |= ADVERTISE_10HALF;
904 } else if (speed == SPEED_100) {
905 if (duplex == DUPLEX_FULL) {
906 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
907 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
909 anar |= ADVERTISE_10HALF;
910 anar |= ADVERTISE_100HALF;
912 } else if (speed == SPEED_1000 && tp->supports_gmii) {
913 if (duplex == DUPLEX_FULL) {
914 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
915 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
916 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
918 anar |= ADVERTISE_10HALF;
919 anar |= ADVERTISE_100HALF;
920 gbcr |= ADVERTISE_1000HALF;
926 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
929 if (tp->supports_gmii)
930 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
932 r8152_mdio_write(tp, MII_ADVERTISE, anar);
933 r8152_mdio_write(tp, MII_BMCR, bmcr);
938 static void rtl8152_up(struct r8152 *tp)
940 r8152b_disable_aldps(tp);
942 r8152b_enable_aldps(tp);
945 static void rtl8152_down(struct r8152 *tp)
947 r8152_power_cut_en(tp, false);
948 r8152b_disable_aldps(tp);
949 r8152b_enter_oob(tp);
950 r8152b_enable_aldps(tp);
953 static void rtl8153_up(struct r8152 *tp)
955 r8153_u1u2en(tp, false);
956 r8153_disable_aldps(tp);
957 r8153_first_init(tp);
958 r8153_u2p3en(tp, false);
961 static void rtl8153_down(struct r8152 *tp)
963 r8153_u1u2en(tp, false);
964 r8153_u2p3en(tp, false);
965 r8153_power_cut_en(tp, false);
966 r8153_disable_aldps(tp);
970 static void r8152b_get_version(struct r8152 *tp)
976 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
977 tcr = (u16)(ocp_data & VERSION_MASK);
979 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
980 if (tcr == r8152_versions[i].tcr) {
981 /* Found a supported version */
982 tp->version = r8152_versions[i].version;
983 tp->supports_gmii = r8152_versions[i].gmii;
988 if (tp->version == RTL_VER_UNKNOWN)
989 debug("r8152 Unknown tcr version 0x%04x\n", tcr);
992 static void r8152b_enable_fc(struct r8152 *tp)
995 anar = r8152_mdio_read(tp, MII_ADVERTISE);
996 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
997 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1000 static void rtl_tally_reset(struct r8152 *tp)
1004 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
1005 ocp_data |= TALLY_RESET;
1006 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
1009 static void r8152b_init(struct r8152 *tp)
1013 r8152b_disable_aldps(tp);
1015 if (tp->version == RTL_VER_01) {
1016 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1017 ocp_data &= ~LED_MODE_MASK;
1018 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1021 r8152_power_cut_en(tp, false);
1023 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1024 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1025 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1026 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1027 ocp_data &= ~MCU_CLK_RATIO_MASK;
1028 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1029 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1030 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1031 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1032 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1034 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
1035 ocp_data |= BIT(15);
1036 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1037 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
1038 ocp_data &= ~BIT(15);
1039 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1041 r8152b_enable_fc(tp);
1042 rtl_tally_reset(tp);
1044 /* enable rx aggregation */
1045 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1047 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1048 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1051 static void r8153_init(struct r8152 *tp)
1056 r8153_disable_aldps(tp);
1057 r8153_u1u2en(tp, false);
1059 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1060 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1062 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1063 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1064 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1070 r8153_u2p3en(tp, false);
1072 if (tp->version == RTL_VER_04) {
1073 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
1074 ocp_data &= ~pwd_dn_scale_mask;
1075 ocp_data |= pwd_dn_scale(96);
1076 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
1078 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
1079 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
1080 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
1081 } else if (tp->version == RTL_VER_05) {
1082 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
1083 ocp_data &= ~ECM_ALDPS;
1084 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
1086 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1087 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1088 ocp_data &= ~DYNAMIC_BURST;
1090 ocp_data |= DYNAMIC_BURST;
1091 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1092 } else if (tp->version == RTL_VER_06) {
1093 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1094 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1095 ocp_data &= ~DYNAMIC_BURST;
1097 ocp_data |= DYNAMIC_BURST;
1098 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1101 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
1102 ocp_data |= EP4_FULL_FC;
1103 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
1105 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
1106 ocp_data &= ~TIMER11_EN;
1107 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
1109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1110 ocp_data &= ~LED_MODE_MASK;
1111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1113 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
1114 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
1115 ocp_data |= LPM_TIMER_500MS;
1117 ocp_data |= LPM_TIMER_500US;
1118 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
1120 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
1121 ocp_data &= ~SEN_VAL_MASK;
1122 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
1123 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
1125 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1127 r8153_power_cut_en(tp, false);
1129 r8152b_enable_fc(tp);
1130 rtl_tally_reset(tp);
1133 static void rtl8152_unload(struct r8152 *tp)
1135 if (tp->version != RTL_VER_01)
1136 r8152_power_cut_en(tp, true);
1139 static void rtl8153_unload(struct r8152 *tp)
1141 r8153_power_cut_en(tp, false);
1144 static int rtl_ops_init(struct r8152 *tp)
1146 struct rtl_ops *ops = &tp->rtl_ops;
1149 switch (tp->version) {
1153 ops->init = r8152b_init;
1154 ops->enable = rtl8152_enable;
1155 ops->disable = rtl8152_disable;
1156 ops->up = rtl8152_up;
1157 ops->down = rtl8152_down;
1158 ops->unload = rtl8152_unload;
1165 ops->init = r8153_init;
1166 ops->enable = rtl8153_enable;
1167 ops->disable = rtl8153_disable;
1168 ops->up = rtl8153_up;
1169 ops->down = rtl8153_down;
1170 ops->unload = rtl8153_unload;
1175 printf("r8152 Unknown Device\n");
1182 static int r8152_init_common(struct r8152 *tp)
1188 debug("** %s()\n", __func__);
1191 speed = rtl8152_get_speed(tp);
1193 link_detected = speed & LINK_STATUS;
1194 if (!link_detected) {
1196 printf("Waiting for Ethernet connection... ");
1197 mdelay(TIMEOUT_RESOLUTION);
1198 timeout += TIMEOUT_RESOLUTION;
1200 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
1201 if (link_detected) {
1202 tp->rtl_ops.enable(tp);
1207 printf("unable to connect.\n");
1213 static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
1215 struct usb_device *udev = ueth->pusb_dev;
1216 u32 opts1, opts2 = 0;
1219 unsigned char msg[PKTSIZE + sizeof(struct tx_desc)];
1220 struct tx_desc *tx_desc = (struct tx_desc *)msg;
1222 debug("** %s(), len %d\n", __func__, length);
1224 opts1 = length | TX_FS | TX_LS;
1226 tx_desc->opts2 = cpu_to_le32(opts2);
1227 tx_desc->opts1 = cpu_to_le32(opts1);
1229 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
1231 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out),
1232 (void *)msg, length + sizeof(struct tx_desc),
1233 &actual_len, USB_BULK_SEND_TIMEOUT);
1234 debug("Tx: len = %zu, actual = %u, err = %d\n",
1235 length + sizeof(struct tx_desc), actual_len, err);
1240 #ifndef CONFIG_DM_ETH
1241 static int r8152_init(struct eth_device *eth, bd_t *bd)
1243 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1244 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1246 return r8152_init_common(tp);
1249 static int r8152_send(struct eth_device *eth, void *packet, int length)
1251 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1253 return r8152_send_common(dev, packet, length);
1256 static int r8152_recv(struct eth_device *eth)
1258 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1260 static unsigned char recv_buf[RTL8152_AGG_BUF_SZ];
1261 unsigned char *pkt_ptr;
1266 u32 bytes_process = 0;
1267 struct rx_desc *rx_desc;
1269 debug("** %s()\n", __func__);
1271 err = usb_bulk_msg(dev->pusb_dev,
1272 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
1276 USB_BULK_RECV_TIMEOUT);
1277 debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
1280 debug("Rx: failed to receive\n");
1283 if (actual_len > RTL8152_AGG_BUF_SZ) {
1284 debug("Rx: received too many bytes %d\n", actual_len);
1288 while (bytes_process < actual_len) {
1289 rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
1290 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
1292 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1293 packet_len -= CRC_SIZE;
1295 net_process_received_packet(pkt_ptr, packet_len);
1298 (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
1300 if (bytes_process % 8)
1301 bytes_process = bytes_process + 8 - (bytes_process % 8);
1307 static void r8152_halt(struct eth_device *eth)
1309 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1310 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1312 debug("** %s()\n", __func__);
1314 tp->rtl_ops.disable(tp);
1317 static int r8152_write_hwaddr(struct eth_device *eth)
1319 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1320 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1322 unsigned char enetaddr[8] = {0};
1324 memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
1326 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1327 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1328 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1330 debug("MAC %pM\n", eth->enetaddr);
1334 void r8152_eth_before_probe(void)
1339 /* Probe to see if a new device is actually an realtek device */
1340 int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
1341 struct ueth_data *ss)
1343 struct usb_interface *iface;
1344 struct usb_interface_descriptor *iface_desc;
1345 int ep_in_found = 0, ep_out_found = 0;
1350 /* let's examine the device now */
1351 iface = &dev->config.if_desc[ifnum];
1352 iface_desc = &dev->config.if_desc[ifnum].desc;
1354 for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
1355 if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
1356 dev->descriptor.idProduct == r8152_dongles[i].product)
1357 /* Found a supported dongle */
1361 if (i == ARRAY_SIZE(r8152_dongles))
1364 memset(ss, 0, sizeof(struct ueth_data));
1366 /* At this point, we know we've got a live one */
1367 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
1368 dev->descriptor.idVendor, dev->descriptor.idProduct);
1370 /* Initialize the ueth_data structure with some useful info */
1373 ss->subclass = iface_desc->bInterfaceSubClass;
1374 ss->protocol = iface_desc->bInterfaceProtocol;
1376 /* alloc driver private */
1377 ss->dev_priv = calloc(1, sizeof(struct r8152));
1383 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
1384 * int. We will ignore any others.
1386 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
1387 /* is it an BULK endpoint? */
1388 if ((iface->ep_desc[i].bmAttributes &
1389 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1390 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
1391 if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
1392 ss->ep_in = ep_addr &
1393 USB_ENDPOINT_NUMBER_MASK;
1396 if (!ep_out_found) {
1397 ss->ep_out = ep_addr &
1398 USB_ENDPOINT_NUMBER_MASK;
1404 /* is it an interrupt endpoint? */
1405 if ((iface->ep_desc[i].bmAttributes &
1406 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
1407 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
1408 USB_ENDPOINT_NUMBER_MASK;
1409 ss->irqinterval = iface->ep_desc[i].bInterval;
1413 debug("Endpoints In %d Out %d Int %d\n",
1414 ss->ep_in, ss->ep_out, ss->ep_int);
1416 /* Do some basic sanity checks, and bail if we find a problem */
1417 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
1418 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
1419 debug("Problems with device\n");
1423 dev->privptr = (void *)ss;
1429 r8152b_get_version(tp);
1431 if (rtl_ops_init(tp))
1434 tp->rtl_ops.init(tp);
1437 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1438 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1444 int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
1445 struct eth_device *eth)
1448 debug("%s: missing parameter.\n", __func__);
1452 sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
1453 eth->init = r8152_init;
1454 eth->send = r8152_send;
1455 eth->recv = r8152_recv;
1456 eth->halt = r8152_halt;
1457 eth->write_hwaddr = r8152_write_hwaddr;
1460 /* Get the MAC address */
1461 if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
1464 debug("MAC %pM\n", eth->enetaddr);
1467 #endif /* !CONFIG_DM_ETH */
1469 #ifdef CONFIG_DM_ETH
1470 static int r8152_eth_start(struct udevice *dev)
1472 struct r8152 *tp = dev_get_priv(dev);
1474 debug("** %s (%d)\n", __func__, __LINE__);
1476 return r8152_init_common(tp);
1479 void r8152_eth_stop(struct udevice *dev)
1481 struct r8152 *tp = dev_get_priv(dev);
1483 debug("** %s (%d)\n", __func__, __LINE__);
1485 tp->rtl_ops.disable(tp);
1488 int r8152_eth_send(struct udevice *dev, void *packet, int length)
1490 struct r8152 *tp = dev_get_priv(dev);
1492 return r8152_send_common(&tp->ueth, packet, length);
1495 int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1497 struct r8152 *tp = dev_get_priv(dev);
1498 struct ueth_data *ueth = &tp->ueth;
1501 struct rx_desc *rx_desc;
1504 len = usb_ether_get_rx_bytes(ueth, &ptr);
1505 debug("%s: first try, len=%d\n", __func__, len);
1507 if (!(flags & ETH_RECV_CHECK_DEVICE))
1509 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ);
1513 len = usb_ether_get_rx_bytes(ueth, &ptr);
1514 debug("%s: second try, len=%d\n", __func__, len);
1517 rx_desc = (struct rx_desc *)ptr;
1518 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1519 packet_len -= CRC_SIZE;
1521 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) {
1522 debug("Rx: too large packet: %d\n", packet_len);
1526 *packetp = ptr + sizeof(struct rx_desc);
1530 usb_ether_advance_rxbuf(ueth, -1);
1534 static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1536 struct r8152 *tp = dev_get_priv(dev);
1538 packet_len += sizeof(struct rx_desc) + CRC_SIZE;
1539 packet_len = ALIGN(packet_len, 8);
1540 usb_ether_advance_rxbuf(&tp->ueth, packet_len);
1545 static int r8152_write_hwaddr(struct udevice *dev)
1547 struct eth_pdata *pdata = dev_get_platdata(dev);
1548 struct r8152 *tp = dev_get_priv(dev);
1550 unsigned char enetaddr[8] = { 0 };
1552 debug("** %s (%d)\n", __func__, __LINE__);
1553 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN);
1555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1556 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1557 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1559 debug("MAC %pM\n", pdata->enetaddr);
1563 int r8152_read_rom_hwaddr(struct udevice *dev)
1565 struct eth_pdata *pdata = dev_get_platdata(dev);
1566 struct r8152 *tp = dev_get_priv(dev);
1568 debug("** %s (%d)\n", __func__, __LINE__);
1569 r8152_read_mac(tp, pdata->enetaddr);
1573 static int r8152_eth_probe(struct udevice *dev)
1575 struct usb_device *udev = dev_get_parent_priv(dev);
1576 struct eth_pdata *pdata = dev_get_platdata(dev);
1577 struct r8152 *tp = dev_get_priv(dev);
1578 struct ueth_data *ueth = &tp->ueth;
1582 r8152_read_mac(tp, pdata->enetaddr);
1584 r8152b_get_version(tp);
1586 ret = rtl_ops_init(tp);
1590 tp->rtl_ops.init(tp);
1593 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1594 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1597 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ);
1600 static const struct eth_ops r8152_eth_ops = {
1601 .start = r8152_eth_start,
1602 .send = r8152_eth_send,
1603 .recv = r8152_eth_recv,
1604 .free_pkt = r8152_free_pkt,
1605 .stop = r8152_eth_stop,
1606 .write_hwaddr = r8152_write_hwaddr,
1607 .read_rom_hwaddr = r8152_read_rom_hwaddr,
1610 U_BOOT_DRIVER(r8152_eth) = {
1611 .name = "r8152_eth",
1613 .probe = r8152_eth_probe,
1614 .ops = &r8152_eth_ops,
1615 .priv_auto_alloc_size = sizeof(struct r8152),
1616 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1619 static const struct usb_device_id r8152_eth_id_table[] = {
1621 { USB_DEVICE(0x0bda, 0x8050) },
1622 { USB_DEVICE(0x0bda, 0x8152) },
1623 { USB_DEVICE(0x0bda, 0x8153) },
1626 { USB_DEVICE(0x04e8, 0xa101) },
1629 { USB_DEVICE(0x17ef, 0x304f) },
1630 { USB_DEVICE(0x17ef, 0x3052) },
1631 { USB_DEVICE(0x17ef, 0x3054) },
1632 { USB_DEVICE(0x17ef, 0x3057) },
1633 { USB_DEVICE(0x17ef, 0x7205) },
1634 { USB_DEVICE(0x17ef, 0x720a) },
1635 { USB_DEVICE(0x17ef, 0x720b) },
1636 { USB_DEVICE(0x17ef, 0x720c) },
1639 { USB_DEVICE(0x2357, 0x0601) },
1642 { USB_DEVICE(0x0955, 0x09ff) },
1644 { } /* Terminating entry */
1647 U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
1648 #endif /* CONFIG_DM_ETH */