2 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
14 #include <usb/lin_gadget_compat.h>
15 #include <linux/mii.h>
16 #include <linux/bitops.h>
17 #include "usb_ether.h"
22 static int curr_eth_dev; /* index for name of next device detected */
25 unsigned short vendor;
26 unsigned short product;
29 static const struct r8152_dongle const r8152_dongles[] = {
56 struct r8152_version {
58 unsigned short version;
62 static const struct r8152_version const r8152_versions[] = {
63 { 0x4c00, RTL_VER_01, 0 },
64 { 0x4c10, RTL_VER_02, 0 },
65 { 0x5c00, RTL_VER_03, 1 },
66 { 0x5c10, RTL_VER_04, 1 },
67 { 0x5c20, RTL_VER_05, 1 },
68 { 0x5c30, RTL_VER_06, 1 },
69 { 0x4800, RTL_VER_07, 0 },
73 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
75 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
78 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
79 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
80 value, index, tmp, size, 500);
81 memcpy(data, tmp, size);
86 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
88 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
90 memcpy(tmp, data, size);
91 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
92 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
93 value, index, tmp, size, 500);
96 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
103 /* both size and index must be 4 bytes align */
104 if ((size & 3) || !size || (index & 3) || !data)
107 if (index + size > 0xffff)
111 txsize = min(size, burst_size);
112 ret = get_registers(tp, index, type, txsize, data);
124 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
125 u16 size, void *data, u16 type)
128 u16 byteen_start, byteen_end, byte_en_to_hw;
129 u16 burst_size = 512;
132 /* both size and index must be 4 bytes align */
133 if ((size & 3) || !size || (index & 3) || !data)
136 if (index + size > 0xffff)
139 byteen_start = byteen & BYTE_EN_START_MASK;
140 byteen_end = byteen & BYTE_EN_END_MASK;
142 byte_en_to_hw = byteen_start | (byteen_start << 4);
143 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
155 txsize = min(size, burst_size);
157 ret = set_registers(tp, index,
158 type | BYTE_EN_DWORD,
168 byte_en_to_hw = byteen_end | (byteen_end >> 4);
169 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
177 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
179 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
182 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
184 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
187 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
189 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
192 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
194 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
197 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
201 generic_ocp_read(tp, index, sizeof(data), &data, type);
203 return __le32_to_cpu(data);
206 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
208 __le32 tmp = __cpu_to_le32(data);
210 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
213 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
217 u8 shift = index & 2;
221 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
223 data = __le32_to_cpu(tmp);
224 data >>= (shift * 8);
230 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
234 u16 byen = BYTE_EN_WORD;
235 u8 shift = index & 2;
241 mask <<= (shift * 8);
242 data <<= (shift * 8);
246 tmp = __cpu_to_le32(data);
248 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
251 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
255 u8 shift = index & 3;
259 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
261 data = __le32_to_cpu(tmp);
262 data >>= (shift * 8);
268 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
272 u16 byen = BYTE_EN_BYTE;
273 u8 shift = index & 3;
279 mask <<= (shift * 8);
280 data <<= (shift * 8);
284 tmp = __cpu_to_le32(data);
286 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
289 u16 ocp_reg_read(struct r8152 *tp, u16 addr)
291 u16 ocp_base, ocp_index;
293 ocp_base = addr & 0xf000;
294 if (ocp_base != tp->ocp_base) {
295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
296 tp->ocp_base = ocp_base;
299 ocp_index = (addr & 0x0fff) | 0xb000;
300 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
303 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
305 u16 ocp_base, ocp_index;
307 ocp_base = addr & 0xf000;
308 if (ocp_base != tp->ocp_base) {
309 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
310 tp->ocp_base = ocp_base;
313 ocp_index = (addr & 0x0fff) | 0xb000;
314 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
317 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
319 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
322 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
324 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
327 void sram_write(struct r8152 *tp, u16 addr, u16 data)
329 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
330 ocp_reg_write(tp, OCP_SRAM_DATA, data);
333 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
334 const u32 mask, bool set, unsigned int timeout)
340 val = ocp_reg_read(tp, index);
342 val = ocp_read_dword(tp, type, index);
347 if ((val & mask) == mask)
353 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
354 __func__, index, mask, timeout);
359 static void r8152b_reset_packet_filter(struct r8152 *tp)
363 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
364 ocp_data &= ~FMC_FCR_MCU_EN;
365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
366 ocp_data |= FMC_FCR_MCU_EN;
367 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
370 static void rtl8152_wait_fifo_empty(struct r8152 *tp)
374 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
375 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
377 debug("Timeout waiting for FIFO empty\n");
379 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
380 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
382 debug("Timeout waiting for TX empty\n");
385 static void rtl8152_nic_reset(struct r8152 *tp)
390 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
391 ocp_data |= BIST_CTRL_SW_RESET;
392 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
394 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
395 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
397 debug("Timeout waiting for NIC reset\n");
400 static u8 rtl8152_get_speed(struct r8152 *tp)
402 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
405 static void rtl_set_eee_plus(struct r8152 *tp)
409 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
410 ocp_data &= ~EEEP_CR_EEEP_TX;
411 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
414 static void rxdy_gated_en(struct r8152 *tp, bool enable)
418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
420 ocp_data |= RXDY_GATED_EN;
422 ocp_data &= ~RXDY_GATED_EN;
423 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
426 static void rtl8152_set_rx_mode(struct r8152 *tp)
434 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
436 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
437 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
441 static int rtl_enable(struct r8152 *tp)
445 r8152b_reset_packet_filter(tp);
447 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
448 ocp_data |= PLA_CR_RE | PLA_CR_TE;
449 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
451 rxdy_gated_en(tp, false);
453 rtl8152_set_rx_mode(tp);
458 static int rtl8152_enable(struct r8152 *tp)
460 rtl_set_eee_plus(tp);
462 return rtl_enable(tp);
465 static void r8153_set_rx_early_timeout(struct r8152 *tp)
467 u32 ocp_data = tp->coalesce / 8;
469 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
472 static void r8153_set_rx_early_size(struct r8152 *tp)
474 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4;
476 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
479 static int rtl8153_enable(struct r8152 *tp)
481 rtl_set_eee_plus(tp);
482 r8153_set_rx_early_timeout(tp);
483 r8153_set_rx_early_size(tp);
485 return rtl_enable(tp);
488 static void rtl_disable(struct r8152 *tp)
492 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
493 ocp_data &= ~RCR_ACPT_ALL;
494 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
496 rxdy_gated_en(tp, true);
498 rtl8152_wait_fifo_empty(tp);
499 rtl8152_nic_reset(tp);
502 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
506 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
508 ocp_data |= POWER_CUT;
510 ocp_data &= ~POWER_CUT;
511 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
513 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
514 ocp_data &= ~RESUME_INDICATE;
515 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
518 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
522 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
524 ocp_data |= CPCR_RX_VLAN;
526 ocp_data &= ~CPCR_RX_VLAN;
527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
530 static void r8153_u1u2en(struct r8152 *tp, bool enable)
535 memset(u1u2, 0xff, sizeof(u1u2));
537 memset(u1u2, 0x00, sizeof(u1u2));
539 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
542 static void r8153_u2p3en(struct r8152 *tp, bool enable)
546 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
547 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
548 ocp_data |= U2P3_ENABLE;
550 ocp_data &= ~U2P3_ENABLE;
551 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
554 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
558 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
560 ocp_data |= PWR_EN | PHASE2_EN;
562 ocp_data &= ~(PWR_EN | PHASE2_EN);
563 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
565 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
566 ocp_data &= ~PCUT_STATUS;
567 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
570 static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
573 unsigned char enetaddr[8] = {0};
575 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
579 memcpy(macaddr, enetaddr, ETH_ALEN);
583 static void r8152b_disable_aldps(struct r8152 *tp)
585 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
589 static void r8152b_enable_aldps(struct r8152 *tp)
591 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
592 LINKENA | DIS_SDSAVE);
595 static void rtl8152_disable(struct r8152 *tp)
597 r8152b_disable_aldps(tp);
599 r8152b_enable_aldps(tp);
602 static void r8152b_hw_phy_cfg(struct r8152 *tp)
606 data = r8152_mdio_read(tp, MII_BMCR);
607 if (data & BMCR_PDOWN) {
609 r8152_mdio_write(tp, MII_BMCR, data);
615 static void rtl8152_reinit_ll(struct r8152 *tp)
620 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
621 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
623 debug("Timeout waiting for link list ready\n");
625 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
626 ocp_data |= RE_INIT_LL;
627 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
629 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
630 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
632 debug("Timeout waiting for link list ready\n");
635 static void r8152b_exit_oob(struct r8152 *tp)
639 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
640 ocp_data &= ~RCR_ACPT_ALL;
641 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
643 rxdy_gated_en(tp, true);
644 r8152b_hw_phy_cfg(tp);
646 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
647 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
649 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
650 ocp_data &= ~NOW_IS_OOB;
651 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
653 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
654 ocp_data &= ~MCU_BORW_EN;
655 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
657 rtl8152_reinit_ll(tp);
658 rtl8152_nic_reset(tp);
660 /* rx share fifo credit full threshold */
661 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
663 if (tp->udev->speed == USB_SPEED_FULL ||
664 tp->udev->speed == USB_SPEED_LOW) {
665 /* rx share fifo credit near full threshold */
666 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
668 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
671 /* rx share fifo credit near full threshold */
672 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
674 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
678 /* TX share fifo free credit full threshold */
679 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
681 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
682 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
683 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
684 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
686 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
688 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
689 ocp_data |= TCR0_AUTO_FIFO;
690 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
693 static void r8152b_enter_oob(struct r8152 *tp)
697 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
698 ocp_data &= ~NOW_IS_OOB;
699 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
701 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
702 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
703 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
707 rtl8152_reinit_ll(tp);
709 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
711 rtl_rx_vlan_en(tp, false);
713 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
714 ocp_data |= ALDPS_PROXY_MODE;
715 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
717 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
718 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
719 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
721 rxdy_gated_en(tp, false);
723 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
724 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
725 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
728 static void r8153_hw_phy_cfg(struct r8152 *tp)
733 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
734 tp->version == RTL_VER_05)
735 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
737 data = r8152_mdio_read(tp, MII_BMCR);
738 if (data & BMCR_PDOWN) {
740 r8152_mdio_write(tp, MII_BMCR, data);
745 if (tp->version == RTL_VER_03) {
746 data = ocp_reg_read(tp, OCP_EEE_CFG);
747 data &= ~CTAP_SHORT_EN;
748 ocp_reg_write(tp, OCP_EEE_CFG, data);
751 data = ocp_reg_read(tp, OCP_POWER_CFG);
752 data |= EEE_CLKDIV_EN;
753 ocp_reg_write(tp, OCP_POWER_CFG, data);
755 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
756 data |= EN_10M_BGOFF;
757 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
758 data = ocp_reg_read(tp, OCP_POWER_CFG);
759 data |= EN_10M_PLLOFF;
760 ocp_reg_write(tp, OCP_POWER_CFG, data);
761 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
763 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
764 ocp_data |= PFM_PWM_SWITCH;
765 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
767 /* Enable LPF corner auto tune */
768 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
770 /* Adjust 10M Amplitude */
771 sram_write(tp, SRAM_10M_AMP1, 0x00af);
772 sram_write(tp, SRAM_10M_AMP2, 0x0208);
775 static void r8153_first_init(struct r8152 *tp)
779 rxdy_gated_en(tp, true);
781 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
782 ocp_data &= ~RCR_ACPT_ALL;
783 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
785 r8153_hw_phy_cfg(tp);
787 rtl8152_nic_reset(tp);
789 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
790 ocp_data &= ~NOW_IS_OOB;
791 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
793 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
794 ocp_data &= ~MCU_BORW_EN;
795 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
797 rtl8152_reinit_ll(tp);
799 rtl_rx_vlan_en(tp, false);
801 ocp_data = RTL8153_RMS;
802 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
803 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
805 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
806 ocp_data |= TCR0_AUTO_FIFO;
807 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
809 rtl8152_nic_reset(tp);
811 /* rx share fifo credit full threshold */
812 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
813 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
814 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
815 /* TX share fifo free credit full threshold */
816 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
819 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
821 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
822 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
825 static void r8153_enter_oob(struct r8152 *tp)
829 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
830 ocp_data &= ~NOW_IS_OOB;
831 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
835 rtl8152_reinit_ll(tp);
837 ocp_data = RTL8153_RMS;
838 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
840 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
841 ocp_data &= ~TEREDO_WAKE_MASK;
842 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
844 rtl_rx_vlan_en(tp, false);
846 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
847 ocp_data |= ALDPS_PROXY_MODE;
848 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
850 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
851 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
852 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
854 rxdy_gated_en(tp, false);
856 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
857 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
858 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
861 static void r8153_disable_aldps(struct r8152 *tp)
865 data = ocp_reg_read(tp, OCP_POWER_CFG);
867 ocp_reg_write(tp, OCP_POWER_CFG, data);
871 static void rtl8153_disable(struct r8152 *tp)
873 r8153_disable_aldps(tp);
877 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
879 u16 bmcr, anar, gbcr;
881 anar = r8152_mdio_read(tp, MII_ADVERTISE);
882 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
883 ADVERTISE_100HALF | ADVERTISE_100FULL);
884 if (tp->supports_gmii) {
885 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
886 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
891 if (autoneg == AUTONEG_DISABLE) {
892 if (speed == SPEED_10) {
894 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
895 } else if (speed == SPEED_100) {
896 bmcr = BMCR_SPEED100;
897 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
898 } else if (speed == SPEED_1000 && tp->supports_gmii) {
899 bmcr = BMCR_SPEED1000;
900 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
905 if (duplex == DUPLEX_FULL)
906 bmcr |= BMCR_FULLDPLX;
908 if (speed == SPEED_10) {
909 if (duplex == DUPLEX_FULL)
910 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
912 anar |= ADVERTISE_10HALF;
913 } else if (speed == SPEED_100) {
914 if (duplex == DUPLEX_FULL) {
915 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
916 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
918 anar |= ADVERTISE_10HALF;
919 anar |= ADVERTISE_100HALF;
921 } else if (speed == SPEED_1000 && tp->supports_gmii) {
922 if (duplex == DUPLEX_FULL) {
923 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
924 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
925 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
927 anar |= ADVERTISE_10HALF;
928 anar |= ADVERTISE_100HALF;
929 gbcr |= ADVERTISE_1000HALF;
935 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
938 if (tp->supports_gmii)
939 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
941 r8152_mdio_write(tp, MII_ADVERTISE, anar);
942 r8152_mdio_write(tp, MII_BMCR, bmcr);
947 static void rtl8152_up(struct r8152 *tp)
949 r8152b_disable_aldps(tp);
951 r8152b_enable_aldps(tp);
954 static void rtl8152_down(struct r8152 *tp)
956 r8152_power_cut_en(tp, false);
957 r8152b_disable_aldps(tp);
958 r8152b_enter_oob(tp);
959 r8152b_enable_aldps(tp);
962 static void rtl8153_up(struct r8152 *tp)
964 r8153_u1u2en(tp, false);
965 r8153_disable_aldps(tp);
966 r8153_first_init(tp);
967 r8153_u2p3en(tp, false);
970 static void rtl8153_down(struct r8152 *tp)
972 r8153_u1u2en(tp, false);
973 r8153_u2p3en(tp, false);
974 r8153_power_cut_en(tp, false);
975 r8153_disable_aldps(tp);
979 static void r8152b_get_version(struct r8152 *tp)
985 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
986 tcr = (u16)(ocp_data & VERSION_MASK);
988 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
989 if (tcr == r8152_versions[i].tcr) {
990 /* Found a supported version */
991 tp->version = r8152_versions[i].version;
992 tp->supports_gmii = r8152_versions[i].gmii;
997 if (tp->version == RTL_VER_UNKNOWN)
998 debug("r8152 Unknown tcr version 0x%04x\n", tcr);
1001 static void r8152b_enable_fc(struct r8152 *tp)
1004 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1005 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1006 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1009 static void rtl_tally_reset(struct r8152 *tp)
1013 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
1014 ocp_data |= TALLY_RESET;
1015 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
1018 static void r8152b_init(struct r8152 *tp)
1022 r8152b_disable_aldps(tp);
1024 if (tp->version == RTL_VER_01) {
1025 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1026 ocp_data &= ~LED_MODE_MASK;
1027 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1030 r8152_power_cut_en(tp, false);
1032 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1033 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1034 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1035 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1036 ocp_data &= ~MCU_CLK_RATIO_MASK;
1037 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1038 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1039 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1040 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1041 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1043 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
1044 ocp_data |= BIT(15);
1045 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1046 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
1047 ocp_data &= ~BIT(15);
1048 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1050 r8152b_enable_fc(tp);
1051 rtl_tally_reset(tp);
1053 /* enable rx aggregation */
1054 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1056 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1057 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1060 static void r8153_init(struct r8152 *tp)
1065 r8153_disable_aldps(tp);
1066 r8153_u1u2en(tp, false);
1068 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1069 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1071 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1072 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1073 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1079 r8153_u2p3en(tp, false);
1081 if (tp->version == RTL_VER_04) {
1082 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
1083 ocp_data &= ~pwd_dn_scale_mask;
1084 ocp_data |= pwd_dn_scale(96);
1085 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
1087 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
1088 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
1089 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
1090 } else if (tp->version == RTL_VER_05) {
1091 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
1092 ocp_data &= ~ECM_ALDPS;
1093 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
1095 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1096 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1097 ocp_data &= ~DYNAMIC_BURST;
1099 ocp_data |= DYNAMIC_BURST;
1100 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1101 } else if (tp->version == RTL_VER_06) {
1102 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1103 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1104 ocp_data &= ~DYNAMIC_BURST;
1106 ocp_data |= DYNAMIC_BURST;
1107 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1110 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
1111 ocp_data |= EP4_FULL_FC;
1112 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
1114 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
1115 ocp_data &= ~TIMER11_EN;
1116 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
1118 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1119 ocp_data &= ~LED_MODE_MASK;
1120 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1122 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
1123 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
1124 ocp_data |= LPM_TIMER_500MS;
1126 ocp_data |= LPM_TIMER_500US;
1127 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
1129 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
1130 ocp_data &= ~SEN_VAL_MASK;
1131 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
1132 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
1134 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1136 r8153_power_cut_en(tp, false);
1138 r8152b_enable_fc(tp);
1139 rtl_tally_reset(tp);
1142 static void rtl8152_unload(struct r8152 *tp)
1144 if (tp->version != RTL_VER_01)
1145 r8152_power_cut_en(tp, true);
1148 static void rtl8153_unload(struct r8152 *tp)
1150 r8153_power_cut_en(tp, false);
1153 static int rtl_ops_init(struct r8152 *tp)
1155 struct rtl_ops *ops = &tp->rtl_ops;
1158 switch (tp->version) {
1162 ops->init = r8152b_init;
1163 ops->enable = rtl8152_enable;
1164 ops->disable = rtl8152_disable;
1165 ops->up = rtl8152_up;
1166 ops->down = rtl8152_down;
1167 ops->unload = rtl8152_unload;
1174 ops->init = r8153_init;
1175 ops->enable = rtl8153_enable;
1176 ops->disable = rtl8153_disable;
1177 ops->up = rtl8153_up;
1178 ops->down = rtl8153_down;
1179 ops->unload = rtl8153_unload;
1184 printf("r8152 Unknown Device\n");
1191 static int r8152_init_common(struct r8152 *tp)
1197 debug("** %s()\n", __func__);
1200 speed = rtl8152_get_speed(tp);
1202 link_detected = speed & LINK_STATUS;
1203 if (!link_detected) {
1205 printf("Waiting for Ethernet connection... ");
1206 mdelay(TIMEOUT_RESOLUTION);
1207 timeout += TIMEOUT_RESOLUTION;
1209 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
1210 if (link_detected) {
1211 tp->rtl_ops.enable(tp);
1216 printf("unable to connect.\n");
1222 static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
1224 struct usb_device *udev = ueth->pusb_dev;
1225 u32 opts1, opts2 = 0;
1228 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg,
1229 PKTSIZE + sizeof(struct tx_desc));
1230 struct tx_desc *tx_desc = (struct tx_desc *)msg;
1232 debug("** %s(), len %d\n", __func__, length);
1234 opts1 = length | TX_FS | TX_LS;
1236 tx_desc->opts2 = cpu_to_le32(opts2);
1237 tx_desc->opts1 = cpu_to_le32(opts1);
1239 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
1241 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out),
1242 (void *)msg, length + sizeof(struct tx_desc),
1243 &actual_len, USB_BULK_SEND_TIMEOUT);
1244 debug("Tx: len = %zu, actual = %u, err = %d\n",
1245 length + sizeof(struct tx_desc), actual_len, err);
1250 #ifndef CONFIG_DM_ETH
1251 static int r8152_init(struct eth_device *eth, bd_t *bd)
1253 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1254 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1256 return r8152_init_common(tp);
1259 static int r8152_send(struct eth_device *eth, void *packet, int length)
1261 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1263 return r8152_send_common(dev, packet, length);
1266 static int r8152_recv(struct eth_device *eth)
1268 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1270 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ);
1271 unsigned char *pkt_ptr;
1276 u32 bytes_process = 0;
1277 struct rx_desc *rx_desc;
1279 debug("** %s()\n", __func__);
1281 err = usb_bulk_msg(dev->pusb_dev,
1282 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
1286 USB_BULK_RECV_TIMEOUT);
1287 debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
1290 debug("Rx: failed to receive\n");
1293 if (actual_len > RTL8152_AGG_BUF_SZ) {
1294 debug("Rx: received too many bytes %d\n", actual_len);
1298 while (bytes_process < actual_len) {
1299 rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
1300 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
1302 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1303 packet_len -= CRC_SIZE;
1305 net_process_received_packet(pkt_ptr, packet_len);
1308 (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
1310 if (bytes_process % 8)
1311 bytes_process = bytes_process + 8 - (bytes_process % 8);
1317 static void r8152_halt(struct eth_device *eth)
1319 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1320 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1322 debug("** %s()\n", __func__);
1324 tp->rtl_ops.disable(tp);
1327 static int r8152_write_hwaddr(struct eth_device *eth)
1329 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1330 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1332 unsigned char enetaddr[8] = {0};
1334 memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
1336 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1337 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1338 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1340 debug("MAC %pM\n", eth->enetaddr);
1344 void r8152_eth_before_probe(void)
1349 /* Probe to see if a new device is actually an realtek device */
1350 int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
1351 struct ueth_data *ss)
1353 struct usb_interface *iface;
1354 struct usb_interface_descriptor *iface_desc;
1355 int ep_in_found = 0, ep_out_found = 0;
1360 /* let's examine the device now */
1361 iface = &dev->config.if_desc[ifnum];
1362 iface_desc = &dev->config.if_desc[ifnum].desc;
1364 for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
1365 if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
1366 dev->descriptor.idProduct == r8152_dongles[i].product)
1367 /* Found a supported dongle */
1371 if (i == ARRAY_SIZE(r8152_dongles))
1374 memset(ss, 0, sizeof(struct ueth_data));
1376 /* At this point, we know we've got a live one */
1377 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
1378 dev->descriptor.idVendor, dev->descriptor.idProduct);
1380 /* Initialize the ueth_data structure with some useful info */
1383 ss->subclass = iface_desc->bInterfaceSubClass;
1384 ss->protocol = iface_desc->bInterfaceProtocol;
1386 /* alloc driver private */
1387 ss->dev_priv = calloc(1, sizeof(struct r8152));
1393 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
1394 * int. We will ignore any others.
1396 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
1397 /* is it an BULK endpoint? */
1398 if ((iface->ep_desc[i].bmAttributes &
1399 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1400 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
1401 if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
1402 ss->ep_in = ep_addr &
1403 USB_ENDPOINT_NUMBER_MASK;
1406 if (!ep_out_found) {
1407 ss->ep_out = ep_addr &
1408 USB_ENDPOINT_NUMBER_MASK;
1414 /* is it an interrupt endpoint? */
1415 if ((iface->ep_desc[i].bmAttributes &
1416 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
1417 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
1418 USB_ENDPOINT_NUMBER_MASK;
1419 ss->irqinterval = iface->ep_desc[i].bInterval;
1423 debug("Endpoints In %d Out %d Int %d\n",
1424 ss->ep_in, ss->ep_out, ss->ep_int);
1426 /* Do some basic sanity checks, and bail if we find a problem */
1427 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
1428 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
1429 debug("Problems with device\n");
1433 dev->privptr = (void *)ss;
1439 r8152b_get_version(tp);
1441 if (rtl_ops_init(tp))
1444 tp->rtl_ops.init(tp);
1447 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1448 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1454 int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
1455 struct eth_device *eth)
1458 debug("%s: missing parameter.\n", __func__);
1462 sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
1463 eth->init = r8152_init;
1464 eth->send = r8152_send;
1465 eth->recv = r8152_recv;
1466 eth->halt = r8152_halt;
1467 eth->write_hwaddr = r8152_write_hwaddr;
1470 /* Get the MAC address */
1471 if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
1474 debug("MAC %pM\n", eth->enetaddr);
1477 #endif /* !CONFIG_DM_ETH */
1479 #ifdef CONFIG_DM_ETH
1480 static int r8152_eth_start(struct udevice *dev)
1482 struct r8152 *tp = dev_get_priv(dev);
1484 debug("** %s (%d)\n", __func__, __LINE__);
1486 return r8152_init_common(tp);
1489 void r8152_eth_stop(struct udevice *dev)
1491 struct r8152 *tp = dev_get_priv(dev);
1493 debug("** %s (%d)\n", __func__, __LINE__);
1495 tp->rtl_ops.disable(tp);
1498 int r8152_eth_send(struct udevice *dev, void *packet, int length)
1500 struct r8152 *tp = dev_get_priv(dev);
1502 return r8152_send_common(&tp->ueth, packet, length);
1505 int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1507 struct r8152 *tp = dev_get_priv(dev);
1508 struct ueth_data *ueth = &tp->ueth;
1511 struct rx_desc *rx_desc;
1514 len = usb_ether_get_rx_bytes(ueth, &ptr);
1515 debug("%s: first try, len=%d\n", __func__, len);
1517 if (!(flags & ETH_RECV_CHECK_DEVICE))
1519 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ);
1523 len = usb_ether_get_rx_bytes(ueth, &ptr);
1524 debug("%s: second try, len=%d\n", __func__, len);
1527 rx_desc = (struct rx_desc *)ptr;
1528 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1529 packet_len -= CRC_SIZE;
1531 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) {
1532 debug("Rx: too large packet: %d\n", packet_len);
1536 *packetp = ptr + sizeof(struct rx_desc);
1540 usb_ether_advance_rxbuf(ueth, -1);
1544 static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1546 struct r8152 *tp = dev_get_priv(dev);
1548 packet_len += sizeof(struct rx_desc) + CRC_SIZE;
1549 packet_len = ALIGN(packet_len, 8);
1550 usb_ether_advance_rxbuf(&tp->ueth, packet_len);
1555 static int r8152_write_hwaddr(struct udevice *dev)
1557 struct eth_pdata *pdata = dev_get_platdata(dev);
1558 struct r8152 *tp = dev_get_priv(dev);
1560 unsigned char enetaddr[8] = { 0 };
1562 debug("** %s (%d)\n", __func__, __LINE__);
1563 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN);
1565 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1566 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1567 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1569 debug("MAC %pM\n", pdata->enetaddr);
1573 int r8152_read_rom_hwaddr(struct udevice *dev)
1575 struct eth_pdata *pdata = dev_get_platdata(dev);
1576 struct r8152 *tp = dev_get_priv(dev);
1578 debug("** %s (%d)\n", __func__, __LINE__);
1579 r8152_read_mac(tp, pdata->enetaddr);
1583 static int r8152_eth_probe(struct udevice *dev)
1585 struct usb_device *udev = dev_get_parent_priv(dev);
1586 struct eth_pdata *pdata = dev_get_platdata(dev);
1587 struct r8152 *tp = dev_get_priv(dev);
1588 struct ueth_data *ueth = &tp->ueth;
1592 r8152_read_mac(tp, pdata->enetaddr);
1594 r8152b_get_version(tp);
1596 ret = rtl_ops_init(tp);
1600 tp->rtl_ops.init(tp);
1603 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1604 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1607 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ);
1610 static const struct eth_ops r8152_eth_ops = {
1611 .start = r8152_eth_start,
1612 .send = r8152_eth_send,
1613 .recv = r8152_eth_recv,
1614 .free_pkt = r8152_free_pkt,
1615 .stop = r8152_eth_stop,
1616 .write_hwaddr = r8152_write_hwaddr,
1617 .read_rom_hwaddr = r8152_read_rom_hwaddr,
1620 U_BOOT_DRIVER(r8152_eth) = {
1621 .name = "r8152_eth",
1623 .probe = r8152_eth_probe,
1624 .ops = &r8152_eth_ops,
1625 .priv_auto_alloc_size = sizeof(struct r8152),
1626 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1629 static const struct usb_device_id r8152_eth_id_table[] = {
1631 { USB_DEVICE(0x0bda, 0x8050) },
1632 { USB_DEVICE(0x0bda, 0x8152) },
1633 { USB_DEVICE(0x0bda, 0x8153) },
1636 { USB_DEVICE(0x04e8, 0xa101) },
1639 { USB_DEVICE(0x17ef, 0x304f) },
1640 { USB_DEVICE(0x17ef, 0x3052) },
1641 { USB_DEVICE(0x17ef, 0x3054) },
1642 { USB_DEVICE(0x17ef, 0x3057) },
1643 { USB_DEVICE(0x17ef, 0x7205) },
1644 { USB_DEVICE(0x17ef, 0x720a) },
1645 { USB_DEVICE(0x17ef, 0x720b) },
1646 { USB_DEVICE(0x17ef, 0x720c) },
1649 { USB_DEVICE(0x2357, 0x0601) },
1652 { USB_DEVICE(0x0955, 0x09ff) },
1654 { } /* Terminating entry */
1657 U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
1658 #endif /* CONFIG_DM_ETH */