2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (C) 2009 NVIDIA, Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/unaligned.h>
26 #include <linux/mii.h>
27 #include "usb_ether.h"
29 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
31 /* Tx command words */
32 #define TX_CMD_A_FIRST_SEG_ 0x00002000
33 #define TX_CMD_A_LAST_SEG_ 0x00001000
36 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
37 #define RX_STS_ES_ 0x00008000 /* Error Summary */
45 #define TX_CFG_ON_ 0x00000004
48 #define HW_CFG_BIR_ 0x00001000
49 #define HW_CFG_RXDOFF_ 0x00000600
50 #define HW_CFG_MEF_ 0x00000020
51 #define HW_CFG_BCE_ 0x00000002
52 #define HW_CFG_LRST_ 0x00000008
55 #define PM_CTL_PHY_RST_ 0x00000010
60 * Hi watermark = 15.5Kb (~10 mtu pkts)
61 * low watermark = 3k (~2 mtu pkts)
62 * backpressure duration = ~ 350us
63 * Apply FC on any frame.
65 #define AFC_CFG_DEFAULT 0x00F830A1
68 #define E2P_CMD_BUSY_ 0x80000000
69 #define E2P_CMD_READ_ 0x00000000
70 #define E2P_CMD_TIMEOUT_ 0x00000400
71 #define E2P_CMD_LOADED_ 0x00000200
72 #define E2P_CMD_ADDR_ 0x000001FF
76 #define BURST_CAP 0x38
78 #define INT_EP_CTL 0x68
79 #define INT_EP_CTL_PHY_INT_ 0x00008000
81 #define BULK_IN_DLY 0x6C
85 #define MAC_CR_MCPAS_ 0x00080000
86 #define MAC_CR_PRMS_ 0x00040000
87 #define MAC_CR_HPFILT_ 0x00002000
88 #define MAC_CR_TXEN_ 0x00000008
89 #define MAC_CR_RXEN_ 0x00000004
95 #define MII_ADDR 0x114
96 #define MII_WRITE_ 0x02
97 #define MII_BUSY_ 0x01
98 #define MII_READ_ 0x00 /* ~of MII Write bit */
100 #define MII_DATA 0x118
107 #define Tx_COE_EN_ 0x00010000
108 #define Rx_COE_EN_ 0x00000001
110 /* Vendor-specific PHY Definitions */
111 #define PHY_INT_SRC 29
113 #define PHY_INT_MASK 30
114 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
115 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
116 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
117 PHY_INT_MASK_LINK_DOWN_)
119 /* USB Vendor Requests */
120 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
121 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
123 /* Some extra defines */
124 #define HS_USB_PKT_SIZE 512
125 #define FS_USB_PKT_SIZE 64
126 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
127 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
128 #define DEFAULT_BULK_IN_DELAY 0x00002000
129 #define MAX_SINGLE_PACKET_SIZE 2048
130 #define EEPROM_MAC_OFFSET 0x01
131 #define SMSC95XX_INTERNAL_PHY_ID 1
132 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
135 #define SMSC95XX_BASE_NAME "sms"
136 #define USB_CTRL_SET_TIMEOUT 5000
137 #define USB_CTRL_GET_TIMEOUT 5000
138 #define USB_BULK_SEND_TIMEOUT 5000
139 #define USB_BULK_RECV_TIMEOUT 5000
141 #define AX_RX_URB_SIZE 2048
142 #define PHY_CONNECT_TIMEOUT 5000
147 static int curr_eth_dev; /* index for name of next device detected */
151 * Smsc95xx infrastructure commands
153 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data)
159 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0),
160 USB_VENDOR_REQUEST_WRITE_REGISTER,
161 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
162 00, index, &data, sizeof(data), USB_CTRL_SET_TIMEOUT);
163 if (len != sizeof(data)) {
164 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
171 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data)
175 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0),
176 USB_VENDOR_REQUEST_READ_REGISTER,
177 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
178 00, index, data, sizeof(data), USB_CTRL_GET_TIMEOUT);
179 if (len != sizeof(data)) {
180 debug("smsc95xx_read_reg failed: index=%d, len=%d",
189 /* Loop until the read is completed with timeout */
190 static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev)
192 unsigned long start_time = get_timer(0);
196 smsc95xx_read_reg(dev, MII_ADDR, &val);
197 if (!(val & MII_BUSY_))
199 } while (get_timer(start_time) < 1 * 1000 * 1000);
204 static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx)
208 /* confirm MII not busy */
209 if (smsc95xx_phy_wait_not_busy(dev)) {
210 debug("MII is busy in smsc95xx_mdio_read\n");
214 /* set the address, index & direction (read from PHY) */
215 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
216 smsc95xx_write_reg(dev, MII_ADDR, addr);
218 if (smsc95xx_phy_wait_not_busy(dev)) {
219 debug("Timed out reading MII reg %02X\n", idx);
223 smsc95xx_read_reg(dev, MII_DATA, &val);
225 return (u16)(val & 0xFFFF);
228 static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx,
233 /* confirm MII not busy */
234 if (smsc95xx_phy_wait_not_busy(dev)) {
235 debug("MII is busy in smsc95xx_mdio_write\n");
240 smsc95xx_write_reg(dev, MII_DATA, val);
242 /* set the address, index & direction (write to PHY) */
243 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
244 smsc95xx_write_reg(dev, MII_ADDR, addr);
246 if (smsc95xx_phy_wait_not_busy(dev))
247 debug("Timed out writing MII reg %02X\n", idx);
250 static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev)
252 unsigned long start_time = get_timer(0);
256 smsc95xx_read_reg(dev, E2P_CMD, &val);
257 if (!(val & E2P_CMD_LOADED_)) {
258 debug("No EEPROM present\n");
261 if (!(val & E2P_CMD_BUSY_))
264 } while (get_timer(start_time) < 1 * 1000 * 1000);
266 debug("EEPROM is busy\n");
270 static int smsc95xx_wait_eeprom(struct ueth_data *dev)
272 unsigned long start_time = get_timer(0);
276 smsc95xx_read_reg(dev, E2P_CMD, &val);
277 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
280 } while (get_timer(start_time) < 1 * 1000 * 1000);
282 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
283 debug("EEPROM read operation timeout\n");
289 static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length,
295 ret = smsc95xx_eeprom_confirm_not_busy(dev);
299 for (i = 0; i < length; i++) {
300 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
301 smsc95xx_write_reg(dev, E2P_CMD, val);
303 ret = smsc95xx_wait_eeprom(dev);
307 smsc95xx_read_reg(dev, E2P_DATA, &val);
308 data[i] = val & 0xFF;
315 * mii_nway_restart - restart NWay (autonegotiation) for this interface
317 * Returns 0 on success, negative on error.
319 static int mii_nway_restart(struct ueth_data *dev)
324 /* if autoneg is off, it's an error */
325 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR);
327 if (bmcr & BMCR_ANENABLE) {
328 bmcr |= BMCR_ANRESTART;
329 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
335 static int smsc95xx_phy_initialize(struct ueth_data *dev)
337 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
338 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
339 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
340 ADVERTISE_PAUSE_ASYM);
343 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC);
345 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK,
346 PHY_INT_MASK_DEFAULT_);
347 mii_nway_restart(dev);
349 debug("phy initialised succesfully\n");
353 static int smsc95xx_init_mac_address(struct eth_device *eth,
354 struct ueth_data *dev)
356 /* try reading mac address from EEPROM */
357 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
358 eth->enetaddr) == 0) {
359 if (is_valid_ether_addr(eth->enetaddr)) {
360 /* eeprom values are valid so use them */
361 debug("MAC address read from EEPROM\n");
367 * No eeprom, or eeprom values are invalid. Generating a random MAC
368 * address is not safe. Just return an error.
373 static int smsc95xx_write_hwaddr(struct eth_device *eth)
375 struct ueth_data *dev = (struct ueth_data *)eth->priv;
376 u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]);
377 u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]);
380 /* set hardware address */
381 debug("** %s()\n", __func__);
382 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
386 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
390 debug("MAC %pM\n", eth->enetaddr);
391 dev->have_hwaddr = 1;
395 /* Enable or disable Tx & Rx checksum offload engines */
396 static int smsc95xx_set_csums(struct ueth_data *dev,
397 int use_tx_csum, int use_rx_csum)
400 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
405 read_buf |= Tx_COE_EN_;
407 read_buf &= ~Tx_COE_EN_;
410 read_buf |= Rx_COE_EN_;
412 read_buf &= ~Rx_COE_EN_;
414 ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
418 debug("COE_CR = 0x%08x\n", read_buf);
422 static void smsc95xx_set_multicast(struct ueth_data *dev)
424 /* No multicast in u-boot */
425 dev->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
428 /* starts the TX path */
429 static void smsc95xx_start_tx_path(struct ueth_data *dev)
433 /* Enable Tx at MAC */
434 dev->mac_cr |= MAC_CR_TXEN_;
436 smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);
438 /* Enable Tx at SCSRs */
439 reg_val = TX_CFG_ON_;
440 smsc95xx_write_reg(dev, TX_CFG, reg_val);
443 /* Starts the Receive path */
444 static void smsc95xx_start_rx_path(struct ueth_data *dev)
446 dev->mac_cr |= MAC_CR_RXEN_;
447 smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);
453 static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
460 struct ueth_data *dev = (struct ueth_data *)eth->priv;
461 #define TIMEOUT_RESOLUTION 50 /* ms */
464 debug("** %s()\n", __func__);
465 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
467 write_buf = HW_CFG_LRST_;
468 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
474 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
479 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
481 if (timeout >= 100) {
482 debug("timeout waiting for completion of Lite Reset\n");
486 write_buf = PM_CTL_PHY_RST_;
487 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
493 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
498 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
499 if (timeout >= 100) {
500 debug("timeout waiting for PHY Reset\n");
503 if (!dev->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)
504 dev->have_hwaddr = 1;
505 if (!dev->have_hwaddr) {
506 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
509 if (smsc95xx_write_hwaddr(eth) < 0)
512 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
515 debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
517 read_buf |= HW_CFG_BIR_;
518 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
522 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
525 debug("Read Value from HW_CFG after writing "
526 "HW_CFG_BIR_: 0x%08x\n", read_buf);
529 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
530 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
531 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
533 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
534 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
538 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
540 debug("rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
542 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
546 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
549 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
551 read_buf = DEFAULT_BULK_IN_DELAY;
552 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
556 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
559 debug("Read Value from BULK_IN_DLY after writing: "
560 "0x%08x\n", read_buf);
562 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
565 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
568 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
570 read_buf &= ~HW_CFG_RXDOFF_;
572 #define NET_IP_ALIGN 0
573 read_buf |= NET_IP_ALIGN << 9;
575 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
579 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
582 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
584 write_buf = 0xFFFFFFFF;
585 ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
589 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
592 debug("ID_REV = 0x%08x\n", read_buf);
596 ret = smsc95xx_write_reg(dev, FLOW, write_buf);
600 read_buf = AFC_CFG_DEFAULT;
601 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
605 ret = smsc95xx_read_reg(dev, MAC_CR, &dev->mac_cr);
609 /* Init Rx. Set Vlan */
610 write_buf = (u32)ETH_P_8021Q;
611 ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
615 /* Disable checksum offload engines */
616 ret = smsc95xx_set_csums(dev, 0, 0);
618 debug("Failed to set csum offload: %d\n", ret);
621 smsc95xx_set_multicast(dev);
623 if (smsc95xx_phy_initialize(dev) < 0)
625 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
629 /* enable PHY interrupts */
630 read_buf |= INT_EP_CTL_PHY_INT_;
632 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
636 smsc95xx_start_tx_path(dev);
637 smsc95xx_start_rx_path(dev);
641 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR)
643 if (!link_detected) {
645 printf("Waiting for Ethernet connection... ");
646 udelay(TIMEOUT_RESOLUTION * 1000);
647 timeout += TIMEOUT_RESOLUTION;
649 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
654 printf("unable to connect.\n");
660 static int smsc95xx_send(struct eth_device *eth, volatile void* packet,
663 struct ueth_data *dev = (struct ueth_data *)eth->priv;
668 unsigned char msg[PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)];
670 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
671 if (length > PKTSIZE)
674 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
675 tx_cmd_b = (u32)length;
676 cpu_to_le32s(&tx_cmd_a);
677 cpu_to_le32s(&tx_cmd_b);
679 /* prepend cmd_a and cmd_b */
680 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
681 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
682 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
684 err = usb_bulk_msg(dev->pusb_dev,
685 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
687 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
689 USB_BULK_SEND_TIMEOUT);
690 debug("Tx: len = %u, actual = %u, err = %d\n",
691 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
696 static int smsc95xx_recv(struct eth_device *eth)
698 struct ueth_data *dev = (struct ueth_data *)eth->priv;
699 static unsigned char recv_buf[AX_RX_URB_SIZE];
700 unsigned char *buf_ptr;
706 debug("** %s()\n", __func__);
707 err = usb_bulk_msg(dev->pusb_dev,
708 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
712 USB_BULK_RECV_TIMEOUT);
713 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
716 debug("Rx: failed to receive\n");
719 if (actual_len > AX_RX_URB_SIZE) {
720 debug("Rx: received too many bytes %d\n", actual_len);
725 while (actual_len > 0) {
727 * 1st 4 bytes contain the length of the actual data plus error
728 * info. Extract data length.
730 if (actual_len < sizeof(packet_len)) {
731 debug("Rx: incomplete packet length\n");
734 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
735 le32_to_cpus(&packet_len);
736 if (packet_len & RX_STS_ES_) {
737 debug("Rx: Error header=%#x", packet_len);
740 packet_len = ((packet_len & RX_STS_FL_) >> 16);
742 if (packet_len > actual_len - sizeof(packet_len)) {
743 debug("Rx: too large packet: %d\n", packet_len);
747 /* Notify net stack */
748 NetReceive(buf_ptr + sizeof(packet_len), packet_len - 4);
750 /* Adjust for next iteration */
751 actual_len -= sizeof(packet_len) + packet_len;
752 buf_ptr += sizeof(packet_len) + packet_len;
753 cur_buf_align = (int)buf_ptr - (int)recv_buf;
755 if (cur_buf_align & 0x03) {
756 int align = 4 - (cur_buf_align & 0x03);
765 static void smsc95xx_halt(struct eth_device *eth)
767 debug("** %s()\n", __func__);
771 * SMSC probing functions
773 void smsc95xx_eth_before_probe(void)
778 struct smsc95xx_dongle {
779 unsigned short vendor;
780 unsigned short product;
783 static const struct smsc95xx_dongle smsc95xx_dongles[] = {
784 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
785 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
786 { 0x0000, 0x0000 } /* END - Do not remove */
789 /* Probe to see if a new device is actually an SMSC device */
790 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
791 struct ueth_data *ss)
793 struct usb_interface *iface;
794 struct usb_interface_descriptor *iface_desc;
797 /* let's examine the device now */
798 iface = &dev->config.if_desc[ifnum];
799 iface_desc = &dev->config.if_desc[ifnum].desc;
801 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
802 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
803 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
804 /* Found a supported dongle */
807 if (smsc95xx_dongles[i].vendor == 0)
810 /* At this point, we know we've got a live one */
811 debug("\n\nUSB Ethernet device detected\n");
812 memset(ss, '\0', sizeof(struct ueth_data));
814 /* Initialize the ueth_data structure with some useful info */
817 ss->subclass = iface_desc->bInterfaceSubClass;
818 ss->protocol = iface_desc->bInterfaceProtocol;
821 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
822 * We will ignore any others.
824 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
825 /* is it an BULK endpoint? */
826 if ((iface->ep_desc[i].bmAttributes &
827 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
828 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
830 iface->ep_desc[i].bEndpointAddress &
831 USB_ENDPOINT_NUMBER_MASK;
834 iface->ep_desc[i].bEndpointAddress &
835 USB_ENDPOINT_NUMBER_MASK;
838 /* is it an interrupt endpoint? */
839 if ((iface->ep_desc[i].bmAttributes &
840 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
841 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
842 USB_ENDPOINT_NUMBER_MASK;
843 ss->irqinterval = iface->ep_desc[i].bInterval;
846 debug("Endpoints In %d Out %d Int %d\n",
847 ss->ep_in, ss->ep_out, ss->ep_int);
849 /* Do some basic sanity checks, and bail if we find a problem */
850 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
851 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
852 debug("Problems with device\n");
855 dev->privptr = (void *)ss;
859 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
860 struct eth_device *eth)
862 debug("** %s()\n", __func__);
864 debug("%s: missing parameter.\n", __func__);
867 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
868 eth->init = smsc95xx_init;
869 eth->send = smsc95xx_send;
870 eth->recv = smsc95xx_recv;
871 eth->halt = smsc95xx_halt;
872 eth->write_hwaddr = smsc95xx_write_hwaddr;