2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (C) 2009 NVIDIA, Corporation
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/unaligned.h>
11 #include <linux/mii.h>
12 #include "usb_ether.h"
15 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
18 #define LED_GPIO_CFG (0x24)
19 #define LED_GPIO_CFG_SPD_LED (0x01000000)
20 #define LED_GPIO_CFG_LNK_LED (0x00100000)
21 #define LED_GPIO_CFG_FDX_LED (0x00010000)
23 /* Tx command words */
24 #define TX_CMD_A_FIRST_SEG_ 0x00002000
25 #define TX_CMD_A_LAST_SEG_ 0x00001000
28 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
29 #define RX_STS_ES_ 0x00008000 /* Error Summary */
37 #define TX_CFG_ON_ 0x00000004
40 #define HW_CFG_BIR_ 0x00001000
41 #define HW_CFG_RXDOFF_ 0x00000600
42 #define HW_CFG_MEF_ 0x00000020
43 #define HW_CFG_BCE_ 0x00000002
44 #define HW_CFG_LRST_ 0x00000008
47 #define PM_CTL_PHY_RST_ 0x00000010
52 * Hi watermark = 15.5Kb (~10 mtu pkts)
53 * low watermark = 3k (~2 mtu pkts)
54 * backpressure duration = ~ 350us
55 * Apply FC on any frame.
57 #define AFC_CFG_DEFAULT 0x00F830A1
60 #define E2P_CMD_BUSY_ 0x80000000
61 #define E2P_CMD_READ_ 0x00000000
62 #define E2P_CMD_TIMEOUT_ 0x00000400
63 #define E2P_CMD_LOADED_ 0x00000200
64 #define E2P_CMD_ADDR_ 0x000001FF
68 #define BURST_CAP 0x38
70 #define INT_EP_CTL 0x68
71 #define INT_EP_CTL_PHY_INT_ 0x00008000
73 #define BULK_IN_DLY 0x6C
77 #define MAC_CR_MCPAS_ 0x00080000
78 #define MAC_CR_PRMS_ 0x00040000
79 #define MAC_CR_HPFILT_ 0x00002000
80 #define MAC_CR_TXEN_ 0x00000008
81 #define MAC_CR_RXEN_ 0x00000004
87 #define MII_ADDR 0x114
88 #define MII_WRITE_ 0x02
89 #define MII_BUSY_ 0x01
90 #define MII_READ_ 0x00 /* ~of MII Write bit */
92 #define MII_DATA 0x118
99 #define Tx_COE_EN_ 0x00010000
100 #define Rx_COE_EN_ 0x00000001
102 /* Vendor-specific PHY Definitions */
103 #define PHY_INT_SRC 29
105 #define PHY_INT_MASK 30
106 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
107 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
108 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
109 PHY_INT_MASK_LINK_DOWN_)
111 /* USB Vendor Requests */
112 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
113 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
115 /* Some extra defines */
116 #define HS_USB_PKT_SIZE 512
117 #define FS_USB_PKT_SIZE 64
118 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
119 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
120 #define DEFAULT_BULK_IN_DELAY 0x00002000
121 #define MAX_SINGLE_PACKET_SIZE 2048
122 #define EEPROM_MAC_OFFSET 0x01
123 #define SMSC95XX_INTERNAL_PHY_ID 1
124 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
127 #define SMSC95XX_BASE_NAME "sms"
128 #define USB_CTRL_SET_TIMEOUT 5000
129 #define USB_CTRL_GET_TIMEOUT 5000
130 #define USB_BULK_SEND_TIMEOUT 5000
131 #define USB_BULK_RECV_TIMEOUT 5000
133 #define AX_RX_URB_SIZE 2048
134 #define PHY_CONNECT_TIMEOUT 5000
139 static int curr_eth_dev; /* index for name of next device detected */
142 struct smsc95xx_private {
143 size_t rx_urb_size; /* maximum USB URB size */
144 u32 mac_cr; /* MAC control register value */
145 int have_hwaddr; /* 1 if we have a hardware MAC address */
149 * Smsc95xx infrastructure commands
151 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data)
154 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
159 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0),
160 USB_VENDOR_REQUEST_WRITE_REGISTER,
161 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
162 00, index, tmpbuf, sizeof(data), USB_CTRL_SET_TIMEOUT);
163 if (len != sizeof(data)) {
164 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
171 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data)
174 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
176 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0),
177 USB_VENDOR_REQUEST_READ_REGISTER,
178 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
179 00, index, tmpbuf, sizeof(data), USB_CTRL_GET_TIMEOUT);
181 if (len != sizeof(data)) {
182 debug("smsc95xx_read_reg failed: index=%d, len=%d",
191 /* Loop until the read is completed with timeout */
192 static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev)
194 unsigned long start_time = get_timer(0);
198 smsc95xx_read_reg(dev, MII_ADDR, &val);
199 if (!(val & MII_BUSY_))
201 } while (get_timer(start_time) < 1 * 1000 * 1000);
206 static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx)
210 /* confirm MII not busy */
211 if (smsc95xx_phy_wait_not_busy(dev)) {
212 debug("MII is busy in smsc95xx_mdio_read\n");
216 /* set the address, index & direction (read from PHY) */
217 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
218 smsc95xx_write_reg(dev, MII_ADDR, addr);
220 if (smsc95xx_phy_wait_not_busy(dev)) {
221 debug("Timed out reading MII reg %02X\n", idx);
225 smsc95xx_read_reg(dev, MII_DATA, &val);
227 return (u16)(val & 0xFFFF);
230 static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx,
235 /* confirm MII not busy */
236 if (smsc95xx_phy_wait_not_busy(dev)) {
237 debug("MII is busy in smsc95xx_mdio_write\n");
242 smsc95xx_write_reg(dev, MII_DATA, val);
244 /* set the address, index & direction (write to PHY) */
245 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
246 smsc95xx_write_reg(dev, MII_ADDR, addr);
248 if (smsc95xx_phy_wait_not_busy(dev))
249 debug("Timed out writing MII reg %02X\n", idx);
252 static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev)
254 unsigned long start_time = get_timer(0);
258 smsc95xx_read_reg(dev, E2P_CMD, &val);
259 if (!(val & E2P_CMD_BUSY_))
262 } while (get_timer(start_time) < 1 * 1000 * 1000);
264 debug("EEPROM is busy\n");
268 static int smsc95xx_wait_eeprom(struct ueth_data *dev)
270 unsigned long start_time = get_timer(0);
274 smsc95xx_read_reg(dev, E2P_CMD, &val);
275 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
278 } while (get_timer(start_time) < 1 * 1000 * 1000);
280 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
281 debug("EEPROM read operation timeout\n");
287 static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length,
293 ret = smsc95xx_eeprom_confirm_not_busy(dev);
297 for (i = 0; i < length; i++) {
298 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
299 smsc95xx_write_reg(dev, E2P_CMD, val);
301 ret = smsc95xx_wait_eeprom(dev);
305 smsc95xx_read_reg(dev, E2P_DATA, &val);
306 data[i] = val & 0xFF;
313 * mii_nway_restart - restart NWay (autonegotiation) for this interface
315 * Returns 0 on success, negative on error.
317 static int mii_nway_restart(struct ueth_data *dev)
322 /* if autoneg is off, it's an error */
323 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR);
325 if (bmcr & BMCR_ANENABLE) {
326 bmcr |= BMCR_ANRESTART;
327 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
333 static int smsc95xx_phy_initialize(struct ueth_data *dev)
335 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
336 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
337 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
338 ADVERTISE_PAUSE_ASYM);
341 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC);
343 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK,
344 PHY_INT_MASK_DEFAULT_);
345 mii_nway_restart(dev);
347 debug("phy initialised succesfully\n");
351 static int smsc95xx_init_mac_address(struct eth_device *eth,
352 struct ueth_data *dev)
354 /* try reading mac address from EEPROM */
355 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
356 eth->enetaddr) == 0) {
357 if (is_valid_ether_addr(eth->enetaddr)) {
358 /* eeprom values are valid so use them */
359 debug("MAC address read from EEPROM\n");
365 * No eeprom, or eeprom values are invalid. Generating a random MAC
366 * address is not safe. Just return an error.
371 static int smsc95xx_write_hwaddr(struct eth_device *eth)
373 struct ueth_data *dev = (struct ueth_data *)eth->priv;
374 struct smsc95xx_private *priv = dev->dev_priv;
375 u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]);
376 u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]);
379 /* set hardware address */
380 debug("** %s()\n", __func__);
381 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
385 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
389 debug("MAC %pM\n", eth->enetaddr);
390 priv->have_hwaddr = 1;
394 /* Enable or disable Tx & Rx checksum offload engines */
395 static int smsc95xx_set_csums(struct ueth_data *dev,
396 int use_tx_csum, int use_rx_csum)
399 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
404 read_buf |= Tx_COE_EN_;
406 read_buf &= ~Tx_COE_EN_;
409 read_buf |= Rx_COE_EN_;
411 read_buf &= ~Rx_COE_EN_;
413 ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
417 debug("COE_CR = 0x%08x\n", read_buf);
421 static void smsc95xx_set_multicast(struct ueth_data *dev)
423 struct smsc95xx_private *priv = dev->dev_priv;
425 /* No multicast in u-boot */
426 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
429 /* starts the TX path */
430 static void smsc95xx_start_tx_path(struct ueth_data *dev)
432 struct smsc95xx_private *priv = dev->dev_priv;
435 /* Enable Tx at MAC */
436 priv->mac_cr |= MAC_CR_TXEN_;
438 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
440 /* Enable Tx at SCSRs */
441 reg_val = TX_CFG_ON_;
442 smsc95xx_write_reg(dev, TX_CFG, reg_val);
445 /* Starts the Receive path */
446 static void smsc95xx_start_rx_path(struct ueth_data *dev)
448 struct smsc95xx_private *priv = dev->dev_priv;
450 priv->mac_cr |= MAC_CR_RXEN_;
451 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
457 static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
464 struct ueth_data *dev = (struct ueth_data *)eth->priv;
465 struct smsc95xx_private *priv =
466 (struct smsc95xx_private *)dev->dev_priv;
467 #define TIMEOUT_RESOLUTION 50 /* ms */
470 debug("** %s()\n", __func__);
471 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
473 write_buf = HW_CFG_LRST_;
474 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
480 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
485 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
487 if (timeout >= 100) {
488 debug("timeout waiting for completion of Lite Reset\n");
492 write_buf = PM_CTL_PHY_RST_;
493 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
499 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
504 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
505 if (timeout >= 100) {
506 debug("timeout waiting for PHY Reset\n");
509 if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)
510 priv->have_hwaddr = 1;
511 if (!priv->have_hwaddr) {
512 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
515 if (smsc95xx_write_hwaddr(eth) < 0)
518 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
521 debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
523 read_buf |= HW_CFG_BIR_;
524 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
528 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
531 debug("Read Value from HW_CFG after writing "
532 "HW_CFG_BIR_: 0x%08x\n", read_buf);
535 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
536 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
537 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
539 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
540 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
544 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
546 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
548 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
552 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
555 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
557 read_buf = DEFAULT_BULK_IN_DELAY;
558 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
562 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
565 debug("Read Value from BULK_IN_DLY after writing: "
566 "0x%08x\n", read_buf);
568 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
571 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
574 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
576 read_buf &= ~HW_CFG_RXDOFF_;
578 #define NET_IP_ALIGN 0
579 read_buf |= NET_IP_ALIGN << 9;
581 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
585 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
588 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
590 write_buf = 0xFFFFFFFF;
591 ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
595 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
598 debug("ID_REV = 0x%08x\n", read_buf);
600 /* Configure GPIO pins as LED outputs */
601 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
602 LED_GPIO_CFG_FDX_LED;
603 ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
606 debug("LED_GPIO_CFG set\n");
610 ret = smsc95xx_write_reg(dev, FLOW, write_buf);
614 read_buf = AFC_CFG_DEFAULT;
615 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
619 ret = smsc95xx_read_reg(dev, MAC_CR, &priv->mac_cr);
623 /* Init Rx. Set Vlan */
624 write_buf = (u32)ETH_P_8021Q;
625 ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
629 /* Disable checksum offload engines */
630 ret = smsc95xx_set_csums(dev, 0, 0);
632 debug("Failed to set csum offload: %d\n", ret);
635 smsc95xx_set_multicast(dev);
637 if (smsc95xx_phy_initialize(dev) < 0)
639 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
643 /* enable PHY interrupts */
644 read_buf |= INT_EP_CTL_PHY_INT_;
646 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
650 smsc95xx_start_tx_path(dev);
651 smsc95xx_start_rx_path(dev);
655 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR)
657 if (!link_detected) {
659 printf("Waiting for Ethernet connection... ");
660 udelay(TIMEOUT_RESOLUTION * 1000);
661 timeout += TIMEOUT_RESOLUTION;
663 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
668 printf("unable to connect.\n");
674 static int smsc95xx_send(struct eth_device *eth, void* packet, int length)
676 struct ueth_data *dev = (struct ueth_data *)eth->priv;
681 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
682 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
684 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
685 if (length > PKTSIZE)
688 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
689 tx_cmd_b = (u32)length;
690 cpu_to_le32s(&tx_cmd_a);
691 cpu_to_le32s(&tx_cmd_b);
693 /* prepend cmd_a and cmd_b */
694 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
695 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
696 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
698 err = usb_bulk_msg(dev->pusb_dev,
699 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
701 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
703 USB_BULK_SEND_TIMEOUT);
704 debug("Tx: len = %u, actual = %u, err = %d\n",
705 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
710 static int smsc95xx_recv(struct eth_device *eth)
712 struct ueth_data *dev = (struct ueth_data *)eth->priv;
713 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
714 unsigned char *buf_ptr;
720 debug("** %s()\n", __func__);
721 err = usb_bulk_msg(dev->pusb_dev,
722 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
726 USB_BULK_RECV_TIMEOUT);
727 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
730 debug("Rx: failed to receive\n");
733 if (actual_len > AX_RX_URB_SIZE) {
734 debug("Rx: received too many bytes %d\n", actual_len);
739 while (actual_len > 0) {
741 * 1st 4 bytes contain the length of the actual data plus error
742 * info. Extract data length.
744 if (actual_len < sizeof(packet_len)) {
745 debug("Rx: incomplete packet length\n");
748 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
749 le32_to_cpus(&packet_len);
750 if (packet_len & RX_STS_ES_) {
751 debug("Rx: Error header=%#x", packet_len);
754 packet_len = ((packet_len & RX_STS_FL_) >> 16);
756 if (packet_len > actual_len - sizeof(packet_len)) {
757 debug("Rx: too large packet: %d\n", packet_len);
761 /* Notify net stack */
762 NetReceive(buf_ptr + sizeof(packet_len), packet_len - 4);
764 /* Adjust for next iteration */
765 actual_len -= sizeof(packet_len) + packet_len;
766 buf_ptr += sizeof(packet_len) + packet_len;
767 cur_buf_align = (int)buf_ptr - (int)recv_buf;
769 if (cur_buf_align & 0x03) {
770 int align = 4 - (cur_buf_align & 0x03);
779 static void smsc95xx_halt(struct eth_device *eth)
781 debug("** %s()\n", __func__);
785 * SMSC probing functions
787 void smsc95xx_eth_before_probe(void)
792 struct smsc95xx_dongle {
793 unsigned short vendor;
794 unsigned short product;
797 static const struct smsc95xx_dongle smsc95xx_dongles[] = {
798 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
799 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
800 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
801 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
802 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
803 { 0x0000, 0x0000 } /* END - Do not remove */
806 /* Probe to see if a new device is actually an SMSC device */
807 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
808 struct ueth_data *ss)
810 struct usb_interface *iface;
811 struct usb_interface_descriptor *iface_desc;
814 /* let's examine the device now */
815 iface = &dev->config.if_desc[ifnum];
816 iface_desc = &dev->config.if_desc[ifnum].desc;
818 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
819 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
820 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
821 /* Found a supported dongle */
824 if (smsc95xx_dongles[i].vendor == 0)
827 /* At this point, we know we've got a live one */
828 debug("\n\nUSB Ethernet device detected\n");
829 memset(ss, '\0', sizeof(struct ueth_data));
831 /* Initialize the ueth_data structure with some useful info */
834 ss->subclass = iface_desc->bInterfaceSubClass;
835 ss->protocol = iface_desc->bInterfaceProtocol;
838 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
839 * We will ignore any others.
841 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
842 /* is it an BULK endpoint? */
843 if ((iface->ep_desc[i].bmAttributes &
844 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
845 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
847 iface->ep_desc[i].bEndpointAddress &
848 USB_ENDPOINT_NUMBER_MASK;
851 iface->ep_desc[i].bEndpointAddress &
852 USB_ENDPOINT_NUMBER_MASK;
855 /* is it an interrupt endpoint? */
856 if ((iface->ep_desc[i].bmAttributes &
857 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
858 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
859 USB_ENDPOINT_NUMBER_MASK;
860 ss->irqinterval = iface->ep_desc[i].bInterval;
863 debug("Endpoints In %d Out %d Int %d\n",
864 ss->ep_in, ss->ep_out, ss->ep_int);
866 /* Do some basic sanity checks, and bail if we find a problem */
867 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
868 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
869 debug("Problems with device\n");
872 dev->privptr = (void *)ss;
874 /* alloc driver private */
875 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
882 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
883 struct eth_device *eth)
885 debug("** %s()\n", __func__);
887 debug("%s: missing parameter.\n", __func__);
890 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
891 eth->init = smsc95xx_init;
892 eth->send = smsc95xx_send;
893 eth->recv = smsc95xx_recv;
894 eth->halt = smsc95xx_halt;
895 eth->write_hwaddr = smsc95xx_write_hwaddr;