2 * Copyright 2011, Marvell Semiconductor Inc.
4 * Licensed under the GPL-2 or later.
6 #ifndef __GADGET__CI_UDC_H__
7 #define __GADGET__CI_UDC_H__
9 #define NUM_ENDPOINTS 6
11 #ifdef CONFIG_CI_UDC_HAS_HOSTPC
13 u32 usbcmd; /* 0x130 */
14 u32 usbsts; /* 0x134 */
16 u32 devaddr; /* 0x144 */
17 u32 epinitaddr; /* 0x148 */
19 u32 portsc; /* 0x174 */
20 u32 pad178[(0x1b4 - (0x174 + 4)) / 4];
21 u32 hostpc1_devlc; /* 0x1b4 */
22 u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4];
23 u32 usbmode; /* 0x1f8 */
24 u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4];
25 u32 epsetupstat; /* 0x208 */
26 u32 epprime; /* 0x20c */
27 u32 epflush; /* 0x210 */
28 u32 epstat; /* 0x214 */
29 u32 epcomp; /* 0x218 */
30 u32 epctrl[16]; /* 0x21c */
34 u32 usbcmd; /* 0x140 */
35 u32 usbsts; /* 0x144 */
37 u32 devaddr; /* 0x154 */
38 u32 epinitaddr; /* 0x158 */
40 u32 portsc; /* 0x184 */
42 u32 usbmode; /* 0x1a8 */
43 u32 epstat; /* 0x1ac */
44 u32 epprime; /* 0x1b0 */
45 u32 epflush; /* 0x1b4 */
47 u32 epcomp; /* 0x1bc */
48 u32 epctrl[16]; /* 0x1c0 */
52 #define PTS(x) (((x) & 0x3) << 30)
53 #define PFSC (1 << 24)
56 #define MICRO_8FRAME 0x8
57 #define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16)
58 #define USBCMD_FS2 (1 << 15)
59 #define USBCMD_RST (1 << 1)
60 #define USBCMD_RUN (1)
62 #define STS_SLI (1 << 8)
63 #define STS_URI (1 << 6)
64 #define STS_PCI (1 << 2)
65 #define STS_UEI (1 << 1)
66 #define STS_UI (1 << 0)
68 #define USBMODE_DEVICE 2
70 #define EPT_TX(x) (1 << (((x) & 0xffff) + 16))
71 #define EPT_RX(x) (1 << ((x) & 0xffff))
73 #define CTRL_TXE (1 << 23)
74 #define CTRL_TXR (1 << 22)
75 #define CTRL_RXE (1 << 7)
76 #define CTRL_RXR (1 << 6)
77 #define CTRL_TXT_BULK (2 << 18)
78 #define CTRL_RXT_BULK (2 << 2)
81 struct usb_request req;
82 struct list_head queue;
83 /* Bounce buffer allocated if needed to align the transfer */
86 /* Buffer for the current transfer. Either req.buf/len or b_buf/len */
94 struct list_head queue;
96 const struct usb_endpoint_descriptor *desc;
100 struct usb_gadget gadget;
101 struct ci_req *ep0_req;
103 struct usb_gadget_driver *driver;
104 struct ehci_ctrl *ctrl;
105 struct ept_queue_head *epts;
107 struct ci_ep ep[NUM_ENDPOINTS];
110 struct ept_queue_head {
112 unsigned current; /* read-only */
123 unsigned char setup_data[8];
131 #define CONFIG_MAX_PKT(n) ((n) << 16)
132 #define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
133 #define CONFIG_IOS (1 << 15) /* IRQ on setup */
135 struct ept_queue_item {
147 #define INFO_BYTES(n) ((n) << 16)
148 #define INFO_IOC (1 << 15)
149 #define INFO_ACTIVE (1 << 7)
150 #define INFO_HALTED (1 << 6)
151 #define INFO_BUFFER_ERROR (1 << 5)
152 #define INFO_TX_ERROR (1 << 3)