git.sur5r.net Git - u-boot/blob - drivers/usb/gadget/designware_udc.c

   1 /*
   2  * Based on drivers/usb/gadget/omap1510_udc.c
   3  * TI OMAP1510 USB bus interface driver
   4  *
   5  * (C) Copyright 2009
   6  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <asm/io.h>
  29
  30 #include <usbdevice.h>
  31 #include "ep0.h"
  32 #include <usb/designware_udc.h>
  33 #include <asm/arch/hardware.h>
  34
  35 #define UDC_INIT_MDELAY         80      /* Device settle delay */
  36
  37 /* Some kind of debugging output... */
  38 #ifndef DEBUG_DWUSBTTY
  39 #define UDCDBG(str)
  40 #define UDCDBGA(fmt, args...)
  41 #else
  42 #define UDCDBG(str) serial_printf(str "\n")
  43 #define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
  44 #endif
  45
  46 static struct urb *ep0_urb;
  47 static struct usb_device_instance *udc_device;
  48
  49 static struct plug_regs *const plug_regs_p =
  50     (struct plug_regs * const)CONFIG_SYS_PLUG_BASE;
  51 static struct udc_regs *const udc_regs_p =
  52     (struct udc_regs * const)CONFIG_SYS_USBD_BASE;
  53 static struct udc_endp_regs *const outep_regs_p =
  54     &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0];
  55 static struct udc_endp_regs *const inep_regs_p =
  56     &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0];
  57
  58 /*
  59  * udc_state_transition - Write the next packet to TxFIFO.
  60  * @initial:    Initial state.
  61  * @final:      Final state.
  62  *
  63  * Helper function to implement device state changes. The device states and
  64  * the events that transition between them are:
  65  *
  66  *                              STATE_ATTACHED
  67  *                              ||      /\
  68  *                              \/      ||
  69  *      DEVICE_HUB_CONFIGURED                   DEVICE_HUB_RESET
  70  *                              ||      /\
  71  *                              \/      ||
  72  *                              STATE_POWERED
  73  *                              ||      /\
  74  *                              \/      ||
  75  *      DEVICE_RESET                            DEVICE_POWER_INTERRUPTION
  76  *                              ||      /\
  77  *                              \/      ||
  78  *                              STATE_DEFAULT
  79  *                              ||      /\
  80  *                              \/      ||
  81  *      DEVICE_ADDRESS_ASSIGNED                 DEVICE_RESET
  82  *                              ||      /\
  83  *                              \/      ||
  84  *                              STATE_ADDRESSED
  85  *                              ||      /\
  86  *                              \/      ||
  87  *      DEVICE_CONFIGURED                       DEVICE_DE_CONFIGURED
  88  *                              ||      /\
  89  *                              \/      ||
  90  *                              STATE_CONFIGURED
  91  *
  92  * udc_state_transition transitions up (in the direction from STATE_ATTACHED
  93  * to STATE_CONFIGURED) from the specified initial state to the specified final
  94  * state, passing through each intermediate state on the way. If the initial
  95  * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
  96  * no state transitions will take place.
  97  *
  98  * udc_state_transition also transitions down (in the direction from
  99  * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
 100  * specified final state, passing through each intermediate state on the way.
 101  * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
 102  * state, then no state transitions will take place.
 103  *
 104  * This function must only be called with interrupts disabled.
 105  */
 106 static void udc_state_transition(usb_device_state_t initial,
 107                                  usb_device_state_t final)
 108 {
 109         if (initial < final) {
 110                 switch (initial) {
 111                 case STATE_ATTACHED:
 112                         usbd_device_event_irq(udc_device,
 113                                               DEVICE_HUB_CONFIGURED, 0);
 114                         if (final == STATE_POWERED)
 115                                 break;
 116                 case STATE_POWERED:
 117                         usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
 118                         if (final == STATE_DEFAULT)
 119                                 break;
 120                 case STATE_DEFAULT:
 121                         usbd_device_event_irq(udc_device,
 122                                               DEVICE_ADDRESS_ASSIGNED, 0);
 123                         if (final == STATE_ADDRESSED)
 124                                 break;
 125                 case STATE_ADDRESSED:
 126                         usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
 127                 case STATE_CONFIGURED:
 128                         break;
 129                 default:
 130                         break;
 131                 }
 132         } else if (initial > final) {
 133                 switch (initial) {
 134                 case STATE_CONFIGURED:
 135                         usbd_device_event_irq(udc_device,
 136                                               DEVICE_DE_CONFIGURED, 0);
 137                         if (final == STATE_ADDRESSED)
 138                                 break;
 139                 case STATE_ADDRESSED:
 140                         usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
 141                         if (final == STATE_DEFAULT)
 142                                 break;
 143                 case STATE_DEFAULT:
 144                         usbd_device_event_irq(udc_device,
 145                                               DEVICE_POWER_INTERRUPTION, 0);
 146                         if (final == STATE_POWERED)
 147                                 break;
 148                 case STATE_POWERED:
 149                         usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
 150                 case STATE_ATTACHED:
 151                         break;
 152                 default:
 153                         break;
 154                 }
 155         }
 156 }
 157
 158 /* Stall endpoint */
 159 static void udc_stall_ep(u32 ep_num)
 160 {
 161         writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
 162                &inep_regs_p[ep_num].endp_cntl);
 163
 164         writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
 165                &outep_regs_p[ep_num].endp_cntl);
 166 }
 167
 168 static void *get_fifo(int ep_num, int in)
 169 {
 170         u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE;
 171
 172         switch (ep_num) {
 173         case UDC_EP3:
 174                 fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn);
 175                 /* break intentionally left out */
 176
 177         case UDC_EP1:
 178                 fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn);
 179                 /* break intentionally left out */
 180
 181         case UDC_EP0:
 182         default:
 183                 if (in) {
 184                         fifo_ptr +=
 185                             readl(&outep_regs_p[2].endp_maxpacksize) >> 16;
 186                         /* break intentionally left out */
 187                 } else {
 188                         break;
 189                 }
 190
 191         case UDC_EP2:
 192                 fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16;
 193                 /* break intentionally left out */
 194         }
 195
 196         return (void *)fifo_ptr;
 197 }
 198
 199 static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len)
 200 {
 201         u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0);
 202         u32 i, nw, nb;
 203         u32 *wrdp;
 204         u8 *bytp;
 205
 206         if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY)
 207                 return -1;
 208
 209         nw = len / sizeof(u32);
 210         nb = len % sizeof(u32);
 211
 212         wrdp = (u32 *)bufp;
 213         for (i = 0; i < nw; i++) {
 214                 writel(readl(fifo_ptr), wrdp);
 215                 wrdp++;
 216         }
 217
 218         bytp = (u8 *)wrdp;
 219         for (i = 0; i < nb; i++) {
 220                 writeb(readb(fifo_ptr), bytp);
 221                 fifo_ptr++;
 222                 bytp++;
 223         }
 224         readl(&outep_regs_p[epNum].write_done);
 225
 226         return 0;
 227 }
 228
 229 static void usbputpcktofifo(int epNum, u8 *bufp, u32 len)
 230 {
 231         u32 i, nw, nb;
 232         u32 *wrdp;
 233         u8 *bytp;
 234         u8 *fifo_ptr = get_fifo(epNum, 1);
 235
 236         nw = len / sizeof(int);
 237         nb = len % sizeof(int);
 238         wrdp = (u32 *)bufp;
 239         for (i = 0; i < nw; i++) {
 240                 writel(*wrdp, fifo_ptr);
 241                 wrdp++;
 242         }
 243
 244         bytp = (u8 *)wrdp;
 245         for (i = 0; i < nb; i++) {
 246                 writeb(*bytp, fifo_ptr);
 247                 fifo_ptr++;
 248                 bytp++;
 249         }
 250 }
 251
 252 /*
 253  * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO.
 254  * @endpoint:           Endpoint pointer.
 255  *
 256  * If the endpoint has an active tx_urb, then the next packet of data from the
 257  * URB is written to the tx FIFO.  The total amount of data in the urb is given
 258  * by urb->actual_length.  The maximum amount of data that can be sent in any
 259  * one packet is given by endpoint->tx_packetSize.  The number of data bytes
 260  * from this URB that have already been transmitted is given by endpoint->sent.
 261  * endpoint->last is updated by this routine with the number of data bytes
 262  * transmitted in this packet.
 263  *
 264  */
 265 static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance
 266                                        *endpoint)
 267 {
 268         struct urb *urb = endpoint->tx_urb;
 269         int align;
 270
 271         if (urb) {
 272                 u32 last;
 273
 274                 UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
 275                         urb->buffer, urb->buffer_length, urb->actual_length);
 276
 277                 last = MIN(urb->actual_length - endpoint->sent,
 278                            endpoint->tx_packetSize);
 279
 280                 if (last) {
 281                         u8 *cp = urb->buffer + endpoint->sent;
 282
 283                         /*
 284                          * This ensures that USBD packet fifo is accessed
 285                          * - through word aligned pointer or
 286                          * - through non word aligned pointer but only
 287                          *   with a max length to make the next packet
 288                          *   word aligned
 289                          */
 290
 291                         align = ((ulong)cp % sizeof(int));
 292                         if (align)
 293                                 last = MIN(last, sizeof(int) - align);
 294
 295                         UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
 296                                 endpoint->sent, endpoint->tx_packetSize, last);
 297
 298                         usbputpcktofifo(endpoint->endpoint_address &
 299                                         USB_ENDPOINT_NUMBER_MASK, cp, last);
 300                 }
 301                 endpoint->last = last;
 302         }
 303 }
 304
 305 /*
 306  * Handle SETUP USB interrupt.
 307  * This function implements TRM Figure 14-14.
 308  */
 309 static void dw_udc_setup(struct usb_endpoint_instance *endpoint)
 310 {
 311         u8 *datap = (u8 *)&ep0_urb->device_request;
 312         int ep_addr = endpoint->endpoint_address;
 313
 314         UDCDBG("-> Entering device setup");
 315         usbgetpckfromfifo(ep_addr, datap, 8);
 316
 317         /* Try to process setup packet */
 318         if (ep0_recv_setup(ep0_urb)) {
 319                 /* Not a setup packet, stall next EP0 transaction */
 320                 udc_stall_ep(0);
 321                 UDCDBG("can't parse setup packet, still waiting for setup");
 322                 return;
 323         }
 324
 325         /* Check direction */
 326         if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK)
 327             == USB_REQ_HOST2DEVICE) {
 328                 UDCDBG("control write on EP0");
 329                 if (le16_to_cpu(ep0_urb->device_request.wLength)) {
 330                         /* Stall this request */
 331                         UDCDBG("Stalling unsupported EP0 control write data "
 332                                "stage.");
 333                         udc_stall_ep(0);
 334                 }
 335         } else {
 336
 337                 UDCDBG("control read on EP0");
 338                 /*
 339                  * The ep0_recv_setup function has already placed our response
 340                  * packet data in ep0_urb->buffer and the packet length in
 341                  * ep0_urb->actual_length.
 342                  */
 343                 endpoint->tx_urb = ep0_urb;
 344                 endpoint->sent = 0;
 345                 /*
 346                  * Write packet data to the FIFO.  dw_write_noniso_tx_fifo
 347                  * will update endpoint->last with the number of bytes written
 348                  * to the FIFO.
 349                  */
 350                 dw_write_noniso_tx_fifo(endpoint);
 351
 352                 writel(0x0, &inep_regs_p[ep_addr].write_done);
 353         }
 354
 355         udc_unset_nak(endpoint->endpoint_address);
 356
 357         UDCDBG("<- Leaving device setup");
 358 }
 359
 360 /*
 361  * Handle endpoint 0 RX interrupt
 362  */
 363 static void dw_udc_ep0_rx(struct usb_endpoint_instance *endpoint)
 364 {
 365         u8 dummy[64];
 366
 367         UDCDBG("RX on EP0");
 368
 369         /* Check direction */
 370         if ((ep0_urb->device_request.bmRequestType
 371              & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) {
 372                 /*
 373                  * This rx interrupt must be for a control write data
 374                  * stage packet.
 375                  *
 376                  * We don't support control write data stages.
 377                  * We should never end up here.
 378                  */
 379
 380                 UDCDBG("Stalling unexpected EP0 control write "
 381                        "data stage packet");
 382                 udc_stall_ep(0);
 383         } else {
 384                 /*
 385                  * This rx interrupt must be for a control read status
 386                  * stage packet.
 387                  */
 388                 UDCDBG("ACK on EP0 control read status stage packet");
 389                 u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff;
 390                 usbgetpckfromfifo(0, dummy, len);
 391         }
 392 }
 393
 394 /*
 395  * Handle endpoint 0 TX interrupt
 396  */
 397 static void dw_udc_ep0_tx(struct usb_endpoint_instance *endpoint)
 398 {
 399         struct usb_device_request *request = &ep0_urb->device_request;
 400         int ep_addr;
 401
 402         UDCDBG("TX on EP0");
 403
 404         /* Check direction */
 405         if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) ==
 406             USB_REQ_HOST2DEVICE) {
 407                 /*
 408                  * This tx interrupt must be for a control write status
 409                  * stage packet.
 410                  */
 411                 UDCDBG("ACK on EP0 control write status stage packet");
 412         } else {
 413                 /*
 414                  * This tx interrupt must be for a control read data
 415                  * stage packet.
 416                  */
 417                 int wLength = le16_to_cpu(request->wLength);
 418
 419                 /*
 420                  * Update our count of bytes sent so far in this
 421                  * transfer.
 422                  */
 423                 endpoint->sent += endpoint->last;
 424
 425                 /*
 426                  * We are finished with this transfer if we have sent
 427                  * all of the bytes in our tx urb (urb->actual_length)
 428                  * unless we need a zero-length terminating packet.  We
 429                  * need a zero-length terminating packet if we returned
 430                  * fewer bytes than were requested (wLength) by the host,
 431                  * and the number of bytes we returned is an exact
 432                  * multiple of the packet size endpoint->tx_packetSize.
 433                  */
 434                 if ((endpoint->sent == ep0_urb->actual_length) &&
 435                     ((ep0_urb->actual_length == wLength) ||
 436                      (endpoint->last != endpoint->tx_packetSize))) {
 437                         /* Done with control read data stage. */
 438                         UDCDBG("control read data stage complete");
 439                 } else {
 440                         /*
 441                          * We still have another packet of data to send
 442                          * in this control read data stage or else we
 443                          * need a zero-length terminating packet.
 444                          */
 445                         UDCDBG("ACK control read data stage packet");
 446                         dw_write_noniso_tx_fifo(endpoint);
 447
 448                         ep_addr = endpoint->endpoint_address;
 449                         writel(0x0, &inep_regs_p[ep_addr].write_done);
 450                 }
 451         }
 452 }
 453
 454 static struct usb_endpoint_instance *dw_find_ep(int ep)
 455 {
 456         int i;
 457
 458         for (i = 0; i < udc_device->bus->max_endpoints; i++) {
 459                 if ((udc_device->bus->endpoint_array[i].endpoint_address &
 460                      USB_ENDPOINT_NUMBER_MASK) == ep)
 461                         return &udc_device->bus->endpoint_array[i];
 462         }
 463         return NULL;
 464 }
 465
 466 /*
 467  * Handle RX transaction on non-ISO endpoint.
 468  * The ep argument is a physical endpoint number for a non-ISO IN endpoint
 469  * in the range 1 to 15.
 470  */
 471 static void dw_udc_epn_rx(int ep)
 472 {
 473         int nbytes = 0;
 474         struct urb *urb;
 475         struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
 476
 477         if (endpoint) {
 478                 urb = endpoint->rcv_urb;
 479
 480                 if (urb) {
 481                         u8 *cp = urb->buffer + urb->actual_length;
 482
 483                         nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) &
 484                             0xfff;
 485                         usbgetpckfromfifo(ep, cp, nbytes);
 486                         usbd_rcv_complete(endpoint, nbytes, 0);
 487                 }
 488         }
 489 }
 490
 491 /*
 492  * Handle TX transaction on non-ISO endpoint.
 493  * The ep argument is a physical endpoint number for a non-ISO IN endpoint
 494  * in the range 16 to 30.
 495  */
 496 static void dw_udc_epn_tx(int ep)
 497 {
 498         struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
 499
 500         if (!endpoint)
 501                 return;
 502
 503         /*
 504          * We need to transmit a terminating zero-length packet now if
 505          * we have sent all of the data in this URB and the transfer
 506          * size was an exact multiple of the packet size.
 507          */
 508         if (endpoint->tx_urb &&
 509             (endpoint->last == endpoint->tx_packetSize) &&
 510             (endpoint->tx_urb->actual_length - endpoint->sent -
 511              endpoint->last == 0)) {
 512                 /* handle zero length packet here */
 513                 writel(0x0, &inep_regs_p[ep].write_done);
 514
 515         }
 516
 517         if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
 518                 /* retire the data that was just sent */
 519                 usbd_tx_complete(endpoint);
 520                 /*
 521                  * Check to see if we have more data ready to transmit
 522                  * now.
 523                  */
 524                 if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
 525                         /* write data to FIFO */
 526                         dw_write_noniso_tx_fifo(endpoint);
 527                         writel(0x0, &inep_regs_p[ep].write_done);
 528
 529                 } else if (endpoint->tx_urb
 530                            && (endpoint->tx_urb->actual_length == 0)) {
 531                         /* udc_set_nak(ep); */
 532                 }
 533         }
 534 }
 535
 536 /*
 537  * Start of public functions.
 538  */
 539
 540 /* Called to start packet transmission. */
 541 int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
 542 {
 543         udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK);
 544         return 0;
 545 }
 546
 547 /* Start to initialize h/w stuff */
 548 int udc_init(void)
 549 {
 550         int i;
 551         u32 plug_st;
 552
 553         udc_device = NULL;
 554
 555         UDCDBG("starting");
 556
 557         readl(&plug_regs_p->plug_pending);
 558
 559         for (i = 0; i < UDC_INIT_MDELAY; i++)
 560                 udelay(1000);
 561
 562         plug_st = readl(&plug_regs_p->plug_state);
 563         writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state);
 564
 565         writel(~0x0, &udc_regs_p->endp_int);
 566         writel(~0x0, &udc_regs_p->dev_int_mask);
 567         writel(~0x0, &udc_regs_p->endp_int_mask);
 568
 569 #ifndef CONFIG_USBD_HS
 570         writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
 571                DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
 572 #else
 573         writel(DEV_CONF_HS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
 574                         DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
 575 #endif
 576
 577         writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
 578
 579         /* Clear all interrupts pending */
 580         writel(DEV_INT_MSK, &udc_regs_p->dev_int);
 581
 582         return 0;
 583 }
 584
 585 int is_usbd_high_speed(void)
 586 {
 587         return (readl(&udc_regs_p->dev_stat) & DEV_STAT_ENUM) ? 0 : 1;
 588 }
 589
 590 /*
 591  * udc_setup_ep - setup endpoint
 592  * Associate a physical endpoint with endpoint_instance
 593  */
 594 void udc_setup_ep(struct usb_device_instance *device,
 595                   u32 ep, struct usb_endpoint_instance *endpoint)
 596 {
 597         UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address);
 598         int ep_addr;
 599         int ep_num, ep_type;
 600         int packet_size;
 601         int buffer_size;
 602         int attributes;
 603         char *tt;
 604         u32 endp_intmask;
 605
 606         if ((ep != 0) && (udc_device->device_state < STATE_ADDRESSED))
 607                 return;
 608
 609         tt = getenv("usbtty");
 610         if (!tt)
 611                 tt = "generic";
 612
 613         ep_addr = endpoint->endpoint_address;
 614         ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
 615
 616         if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
 617                 /* IN endpoint */
 618                 packet_size = endpoint->tx_packetSize;
 619                 buffer_size = packet_size * 2;
 620                 attributes = endpoint->tx_attributes;
 621         } else {
 622                 /* OUT endpoint */
 623                 packet_size = endpoint->rcv_packetSize;
 624                 buffer_size = packet_size * 2;
 625                 attributes = endpoint->rcv_attributes;
 626         }
 627
 628         switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) {
 629         case USB_ENDPOINT_XFER_CONTROL:
 630                 ep_type = ENDP_EPTYPE_CNTL;
 631                 break;
 632         case USB_ENDPOINT_XFER_BULK:
 633         default:
 634                 ep_type = ENDP_EPTYPE_BULK;
 635                 break;
 636         case USB_ENDPOINT_XFER_INT:
 637                 ep_type = ENDP_EPTYPE_INT;
 638                 break;
 639         case USB_ENDPOINT_XFER_ISOC:
 640                 ep_type = ENDP_EPTYPE_ISO;
 641                 break;
 642         }
 643
 644         struct udc_endp_regs *out_p = &outep_regs_p[ep_num];
 645         struct udc_endp_regs *in_p = &inep_regs_p[ep_num];
 646
 647         if (!ep_addr) {
 648                 /* Setup endpoint 0 */
 649                 buffer_size = packet_size;
 650
 651                 writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK,
 652                        &in_p->endp_cntl);
 653
 654                 writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK,
 655                        &out_p->endp_cntl);
 656
 657                 writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl);
 658
 659                 writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
 660
 661                 writel(packet_size, &in_p->endp_maxpacksize);
 662
 663                 writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl);
 664
 665                 writel(packet_size | ((buffer_size / sizeof(int)) << 16),
 666                        &out_p->endp_maxpacksize);
 667
 668         } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
 669                 /* Setup the IN endpoint */
 670                 writel(0x0, &in_p->endp_status);
 671                 writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl);
 672                 writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
 673                 writel(packet_size, &in_p->endp_maxpacksize);
 674
 675                 if (!strcmp(tt, "cdc_acm")) {
 676                         if (ep_type == ENDP_EPTYPE_INT) {
 677                                 /* Conf no. 1 Interface no. 0 */
 678                                 writel((packet_size << 19) |
 679                                        ENDP_EPDIR_IN | (1 << 7) |
 680                                        (0 << 11) | (ep_type << 5) | ep_num,
 681                                        &udc_regs_p->udc_endp_reg[ep_num]);
 682                         } else {
 683                                 /* Conf no. 1 Interface no. 1 */
 684                                 writel((packet_size << 19) |
 685                                        ENDP_EPDIR_IN | (1 << 7) |
 686                                        (1 << 11) | (ep_type << 5) | ep_num,
 687                                        &udc_regs_p->udc_endp_reg[ep_num]);
 688                         }
 689                 } else {
 690                         /* Conf no. 1 Interface no. 0 */
 691                         writel((packet_size << 19) |
 692                                ENDP_EPDIR_IN | (1 << 7) |
 693                                (0 << 11) | (ep_type << 5) | ep_num,
 694                                &udc_regs_p->udc_endp_reg[ep_num]);
 695                 }
 696
 697         } else {
 698                 /* Setup the OUT endpoint */
 699                 writel(0x0, &out_p->endp_status);
 700                 writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl);
 701                 writel(packet_size | ((buffer_size / sizeof(int)) << 16),
 702                        &out_p->endp_maxpacksize);
 703
 704                 if (!strcmp(tt, "cdc_acm")) {
 705                         writel((packet_size << 19) |
 706                                ENDP_EPDIR_OUT | (1 << 7) |
 707                                (1 << 11) | (ep_type << 5) | ep_num,
 708                                &udc_regs_p->udc_endp_reg[ep_num]);
 709                 } else {
 710                         writel((packet_size << 19) |
 711                                ENDP_EPDIR_OUT | (1 << 7) |
 712                                (0 << 11) | (ep_type << 5) | ep_num,
 713                                &udc_regs_p->udc_endp_reg[ep_num]);
 714                 }
 715
 716         }
 717
 718         endp_intmask = readl(&udc_regs_p->endp_int_mask);
 719         endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num);
 720         writel(endp_intmask, &udc_regs_p->endp_int_mask);
 721 }
 722
 723 /* Turn on the USB connection by enabling the pullup resistor */
 724 void udc_connect(void)
 725 {
 726         u32 plug_st, dev_cntl;
 727
 728         dev_cntl = readl(&udc_regs_p->dev_cntl);
 729         dev_cntl |= DEV_CNTL_SOFTDISCONNECT;
 730         writel(dev_cntl, &udc_regs_p->dev_cntl);
 731
 732         udelay(1000);
 733
 734         dev_cntl = readl(&udc_regs_p->dev_cntl);
 735         dev_cntl &= ~DEV_CNTL_SOFTDISCONNECT;
 736         writel(dev_cntl, &udc_regs_p->dev_cntl);
 737
 738         plug_st = readl(&plug_regs_p->plug_state);
 739         plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
 740         writel(plug_st, &plug_regs_p->plug_state);
 741 }
 742
 743 /* Turn off the USB connection by disabling the pullup resistor */
 744 void udc_disconnect(void)
 745 {
 746         u32 plug_st;
 747
 748         writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
 749
 750         plug_st = readl(&plug_regs_p->plug_state);
 751         plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
 752         writel(plug_st, &plug_regs_p->plug_state);
 753 }
 754
 755 /* Switch on the UDC */
 756 void udc_enable(struct usb_device_instance *device)
 757 {
 758         UDCDBGA("enable device %p, status %d", device, device->status);
 759
 760         /* Save the device structure pointer */
 761         udc_device = device;
 762
 763         /* Setup ep0 urb */
 764         if (!ep0_urb) {
 765                 ep0_urb =
 766                     usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array);
 767         } else {
 768                 serial_printf("udc_enable: ep0_urb already allocated %p\n",
 769                               ep0_urb);
 770         }
 771
 772         writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
 773 }
 774
 775 /**
 776  * udc_startup - allow udc code to do any additional startup
 777  */
 778 void udc_startup_events(struct usb_device_instance *device)
 779 {
 780         /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
 781         usbd_device_event_irq(device, DEVICE_INIT, 0);
 782
 783         /*
 784          * The DEVICE_CREATE event puts the USB device in the state
 785          * STATE_ATTACHED.
 786          */
 787         usbd_device_event_irq(device, DEVICE_CREATE, 0);
 788
 789         /*
 790          * Some USB controller driver implementations signal
 791          * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
 792          * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
 793          * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
 794          * The DW USB client controller has the capability to detect when the
 795          * USB cable is connected to a powered USB bus, so we will defer the
 796          * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
 797          */
 798
 799         udc_enable(device);
 800 }
 801
 802 /*
 803  * Plug detection interrupt handling
 804  */
 805 void dw_udc_plug_irq(void)
 806 {
 807         if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) {
 808                 /*
 809                  * USB cable attached
 810                  * Turn off PHY reset bit (PLUG detect).
 811                  * Switch PHY opmode to normal operation (PLUG detect).
 812                  */
 813                 udc_connect();
 814                 writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
 815
 816                 UDCDBG("device attached and powered");
 817                 udc_state_transition(udc_device->device_state, STATE_POWERED);
 818         } else {
 819                 writel(~0x0, &udc_regs_p->dev_int_mask);
 820
 821                 UDCDBG("device detached or unpowered");
 822                 udc_state_transition(udc_device->device_state, STATE_ATTACHED);
 823         }
 824 }
 825
 826 /*
 827  * Device interrupt handling
 828  */
 829 void dw_udc_dev_irq(void)
 830 {
 831         if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) {
 832                 writel(~0x0, &udc_regs_p->endp_int_mask);
 833
 834                 writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH,
 835                        &inep_regs_p[0].endp_cntl);
 836
 837                 writel(DEV_INT_USBRESET, &udc_regs_p->dev_int);
 838
 839                 /*
 840                  * This endpoint0 specific register can be programmed only
 841                  * after the phy clock is initialized
 842                  */
 843                 writel((EP0_MAX_PACKET_SIZE << 19) | ENDP_EPTYPE_CNTL,
 844                                 &udc_regs_p->udc_endp_reg[0]);
 845
 846                 UDCDBG("device reset in progess");
 847                 udc_state_transition(udc_device->device_state, STATE_DEFAULT);
 848         }
 849
 850         /* Device Enumeration completed */
 851         if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) {
 852                 writel(DEV_INT_ENUM, &udc_regs_p->dev_int);
 853
 854                 /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */
 855                 writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001,
 856                        &udc_regs_p->endp_int_mask);
 857
 858                 UDCDBG("default -> addressed");
 859                 udc_state_transition(udc_device->device_state, STATE_ADDRESSED);
 860         }
 861
 862         /* The USB will be in SUSPEND in 3 ms */
 863         if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) {
 864                 writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int);
 865
 866                 UDCDBG("entering inactive state");
 867                 /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */
 868         }
 869
 870         /* SetConfiguration command received */
 871         if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) {
 872                 writel(DEV_INT_SETCFG, &udc_regs_p->dev_int);
 873
 874                 UDCDBG("entering configured state");
 875                 udc_state_transition(udc_device->device_state,
 876                                      STATE_CONFIGURED);
 877         }
 878
 879         /* SetInterface command received */
 880         if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF)
 881                 writel(DEV_INT_SETINTF, &udc_regs_p->dev_int);
 882
 883         /* USB Suspend detected on cable */
 884         if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) {
 885                 writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int);
 886
 887                 UDCDBG("entering suspended state");
 888                 usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0);
 889         }
 890
 891         /* USB Start-Of-Frame detected on cable */
 892         if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF)
 893                 writel(DEV_INT_SOF, &udc_regs_p->dev_int);
 894 }
 895
 896 /*
 897  * Endpoint interrupt handling
 898  */
 899 void dw_udc_endpoint_irq(void)
 900 {
 901         while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) {
 902
 903                 writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int);
 904
 905                 if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK)
 906                     == ENDP_STATUS_OUT_SETUP) {
 907                         dw_udc_setup(udc_device->bus->endpoint_array + 0);
 908                         writel(ENDP_STATUS_OUT_SETUP,
 909                                &outep_regs_p[0].endp_status);
 910
 911                 } else if ((readl(&outep_regs_p[0].endp_status) &
 912                             ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
 913                         dw_udc_ep0_rx(udc_device->bus->endpoint_array + 0);
 914                         writel(ENDP_STATUS_OUT_DATA,
 915                                &outep_regs_p[0].endp_status);
 916
 917                 } else if ((readl(&outep_regs_p[0].endp_status) &
 918                             ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
 919                         /* NONE received */
 920                 }
 921
 922                 writel(0x0, &outep_regs_p[0].endp_status);
 923         }
 924
 925         if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) {
 926                 dw_udc_ep0_tx(udc_device->bus->endpoint_array + 0);
 927
 928                 writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status);
 929                 writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int);
 930         }
 931
 932         if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) {
 933                 u32 epnum = 0;
 934                 u32 ep_int = readl(&udc_regs_p->endp_int) &
 935                     ENDP_INT_NONISOOUT_MSK;
 936
 937                 ep_int >>= 16;
 938                 while (0x0 == (ep_int & 0x1)) {
 939                         ep_int >>= 1;
 940                         epnum++;
 941                 }
 942
 943                 writel((1 << 16) << epnum, &udc_regs_p->endp_int);
 944
 945                 if ((readl(&outep_regs_p[epnum].endp_status) &
 946                      ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
 947
 948                         dw_udc_epn_rx(epnum);
 949                         writel(ENDP_STATUS_OUT_DATA,
 950                                &outep_regs_p[epnum].endp_status);
 951                 } else if ((readl(&outep_regs_p[epnum].endp_status) &
 952                             ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
 953                         writel(0x0, &outep_regs_p[epnum].endp_status);
 954                 }
 955         }
 956
 957         if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) {
 958                 u32 epnum = 0;
 959                 u32 ep_int = readl(&udc_regs_p->endp_int) &
 960                     ENDP_INT_NONISOIN_MSK;
 961
 962                 while (0x0 == (ep_int & 0x1)) {
 963                         ep_int >>= 1;
 964                         epnum++;
 965                 }
 966
 967                 if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) {
 968                         writel(ENDP_STATUS_IN,
 969                                &outep_regs_p[epnum].endp_status);
 970                         dw_udc_epn_tx(epnum);
 971
 972                         writel(ENDP_STATUS_IN,
 973                                &outep_regs_p[epnum].endp_status);
 974                 }
 975
 976                 writel((1 << epnum), &udc_regs_p->endp_int);
 977         }
 978 }
 979
 980 /*
 981  * UDC interrupts
 982  */
 983 void udc_irq(void)
 984 {
 985         /*
 986          * Loop while we have interrupts.
 987          * If we don't do this, the input chain
 988          * polling delay is likely to miss
 989          * host requests.
 990          */
 991         while (readl(&plug_regs_p->plug_pending))
 992                 dw_udc_plug_irq();
 993
 994         while (readl(&udc_regs_p->dev_int))
 995                 dw_udc_dev_irq();
 996
 997         if (readl(&udc_regs_p->endp_int))
 998                 dw_udc_endpoint_irq();
 999 }
1000
1001 /* Flow control */
1002 void udc_set_nak(int epid)
1003 {
1004         writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
1005                &inep_regs_p[epid].endp_cntl);
1006
1007         writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
1008                &outep_regs_p[epid].endp_cntl);
1009 }
1010
1011 void udc_unset_nak(int epid)
1012 {
1013         u32 val;
1014
1015         val = readl(&inep_regs_p[epid].endp_cntl);
1016         val &= ~ENDP_CNTL_SNAK;
1017         val |= ENDP_CNTL_CNAK;
1018         writel(val, &inep_regs_p[epid].endp_cntl);
1019
1020         val = readl(&outep_regs_p[epid].endp_cntl);
1021         val &= ~ENDP_CNTL_SNAK;
1022         val |= ENDP_CNTL_CNAK;
1023         writel(val, &outep_regs_p[epid].endp_cntl);
1024 }