git.sur5r.net Git - u-boot/blob - drivers/usb/gadget/dwc2_udc_otg_phy.c

   1 /*
   2  * drivers/usb/gadget/dwc2_udc_otg.c
   3  * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
   4  *
   5  * Copyright (C) 2008 for Samsung Electronics
   6  *
   7  * BSP Support for Samsung's UDC driver
   8  * available at:
   9  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10  *
  11  * State machine bugfixes:
  12  * Marek Szyprowski <m.szyprowski@samsung.com>
  13  *
  14  * Ported to u-boot:
  15  * Marek Szyprowski <m.szyprowski@samsung.com>
  16  * Lukasz Majewski <l.majewski@samsumg.com>
  17  *
  18  * SPDX-License-Identifier:     GPL-2.0+
  19  */
  20
  21 #include <common.h>
  22 #include <linux/errno.h>
  23 #include <linux/list.h>
  24 #include <malloc.h>
  25
  26 #include <linux/usb/ch9.h>
  27 #include <linux/usb/gadget.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/unaligned.h>
  31 #include <asm/io.h>
  32
  33 #include <asm/mach-types.h>
  34
  35 #include "dwc2_udc_otg_regs.h"
  36 #include "dwc2_udc_otg_priv.h"
  37 #include <usb/lin_gadget_compat.h>
  38
  39 #include <usb/dwc2_udc.h>
  40
  41 void otg_phy_init(struct dwc2_udc *dev)
  42 {
  43         unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
  44         struct dwc2_usbotg_phy *phy =
  45                 (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
  46
  47         dev->pdata->phy_control(1);
  48
  49         /* USB PHY0 Enable */
  50         printf("USB PHY0 Enable\n");
  51
  52         /* Enable PHY */
  53         writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
  54
  55         if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
  56                 writel((readl(&phy->phypwr)
  57                         &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
  58                         &~FORCE_SUSPEND_0), &phy->phypwr);
  59         else /* C110 GONI */
  60                 writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
  61                         &~FORCE_SUSPEND_0), &phy->phypwr);
  62
  63         if (s5p_cpu_id == 0x4412)
  64                 writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
  65                         EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
  66                        &phy->phyclk); /* PLL 24Mhz */
  67         else
  68                 writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
  69                        CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
  70
  71         writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
  72                | PHY_SW_RST0, &phy->rstcon);
  73         udelay(10);
  74         writel(readl(&phy->rstcon)
  75                &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
  76         udelay(10);
  77 }
  78
  79 void otg_phy_off(struct dwc2_udc *dev)
  80 {
  81         unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
  82         struct dwc2_usbotg_phy *phy =
  83                 (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
  84
  85         /* reset controller just in case */
  86         writel(PHY_SW_RST0, &phy->rstcon);
  87         udelay(20);
  88         writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
  89         udelay(20);
  90
  91         writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
  92                | FORCE_SUSPEND_0, &phy->phypwr);
  93
  94         writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
  95
  96         writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
  97               &phy->phyclk);
  98
  99         udelay(10000);
 100
 101         dev->pdata->phy_control(0);
 102 }