2 * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
3 * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
5 * Copyright (C) 2009 for Samsung Electronics
7 * BSP Support for Samsung's UDC driver
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 static u8 clear_feature_num;
35 int clear_feature_flag;
37 /* Bulk-Only Mass Storage Reset (class-specific request) */
38 #define GET_MAX_LUN_REQUEST 0xFE
39 #define BOT_RESET_REQUEST 0xFF
41 static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
45 flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
46 (unsigned long) usb_ctrl_dma_addr
49 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
50 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
52 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
53 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
54 ®->in_endp[EP0_CON].diepctl);
56 DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
57 __func__, readl(®->in_endp[EP0_CON].diepctl));
58 dev->ep0state = WAIT_FOR_IN_COMPLETE;
61 void s3c_udc_pre_setup(void)
65 DEBUG_IN_EP("%s : Prepare Setup packets.\n", __func__);
67 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
68 (unsigned long) usb_ctrl_dma_addr
71 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
72 ®->out_endp[EP0_CON].doeptsiz);
73 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
75 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
76 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
78 DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
79 __func__, readl(®->in_endp[EP0_CON].diepctl));
80 DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
81 __func__, readl(®->out_endp[EP0_CON].doepctl));
85 static inline void s3c_ep0_complete_out(void)
89 DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
90 __func__, readl(®->in_endp[EP0_CON].diepctl));
91 DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
92 __func__, readl(®->out_endp[EP0_CON].doepctl));
94 DEBUG_IN_EP("%s : Prepare Complete Out packet.\n", __func__);
96 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
97 (unsigned long) usb_ctrl_dma_addr
100 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
101 ®->out_endp[EP0_CON].doeptsiz);
102 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
104 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
105 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
106 ®->out_endp[EP0_CON].doepctl);
108 DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
109 __func__, readl(®->in_endp[EP0_CON].diepctl));
110 DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
111 __func__, readl(®->out_endp[EP0_CON].doepctl));
116 static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
120 u32 ep_num = ep_index(ep);
122 buf = req->req.buf + req->req.actual;
124 length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
129 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
130 (unsigned long) ep->dev->dma_buf[ep_num]
136 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
139 ctrl = readl(®->out_endp[ep_num].doepctl);
141 writel(the_controller->dma_addr[ep_index(ep)+1],
142 ®->out_endp[ep_num].doepdma);
143 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
144 ®->out_endp[ep_num].doeptsiz);
145 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
147 DEBUG_OUT_EP("%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
148 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
149 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
151 readl(®->out_endp[ep_num].doepdma),
152 readl(®->out_endp[ep_num].doeptsiz),
153 readl(®->out_endp[ep_num].doepctl),
154 buf, pktcnt, length);
159 int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
163 u32 ep_num = ep_index(ep);
164 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
166 buf = req->req.buf + req->req.actual;
167 length = req->req.length - req->req.actual;
169 if (ep_num == EP0_CON)
170 length = min_t(length, (u32)ep_maxpacket(ep));
174 memcpy(p, ep->dma_buf, length);
176 flush_dcache_range((unsigned long) p ,
177 (unsigned long) p + DMA_BUFFER_SIZE);
182 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
184 /* Flush the endpoint's Tx FIFO */
185 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
186 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
187 while (readl(®->grstctl) & TX_FIFO_FLUSH)
190 writel(the_controller->dma_addr[ep_index(ep)+1],
191 ®->in_endp[ep_num].diepdma);
192 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
193 ®->in_endp[ep_num].dieptsiz);
195 ctrl = readl(®->in_endp[ep_num].diepctl);
197 /* Write the FIFO number to be used for this endpoint */
198 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
199 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
201 /* Clear reserved (Next EP) bits */
202 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
204 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
206 DEBUG_IN_EP("%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
207 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
208 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
210 readl(®->in_endp[ep_num].diepdma),
211 readl(®->in_endp[ep_num].dieptsiz),
212 readl(®->in_endp[ep_num].diepctl),
213 buf, pktcnt, length);
218 static void complete_rx(struct s3c_udc *dev, u8 ep_num)
220 struct s3c_ep *ep = &dev->ep[ep_num];
221 struct s3c_request *req = NULL;
222 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
223 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
225 if (list_empty(&ep->queue)) {
226 DEBUG_OUT_EP("%s: RX DMA done : NULL REQ on OUT EP-%d\n",
232 req = list_entry(ep->queue.next, struct s3c_request, queue);
233 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
235 if (ep_num == EP0_CON)
236 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
238 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
240 xfer_size = ep->len - xfer_size;
242 invalidate_dcache_range((unsigned long) p,
243 (unsigned long) p + DMA_BUFFER_SIZE);
245 memcpy(ep->dma_buf, p, ep->len);
247 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
248 is_short = (xfer_size < ep->ep.maxpacket);
250 DEBUG_OUT_EP("%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
251 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
252 __func__, ep_num, req->req.actual, req->req.length,
253 is_short, ep_tsr, xfer_size);
255 if (is_short || req->req.actual == req->req.length) {
256 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
257 DEBUG_OUT_EP(" => Send ZLP\n");
258 s3c_udc_ep0_zlp(dev);
259 /* packet will be completed in complete_tx() */
260 dev->ep0state = WAIT_FOR_IN_COMPLETE;
264 if (!list_empty(&ep->queue)) {
265 req = list_entry(ep->queue.next,
266 struct s3c_request, queue);
267 DEBUG_OUT_EP("%s: Next Rx request start...\n",
276 static void complete_tx(struct s3c_udc *dev, u8 ep_num)
278 struct s3c_ep *ep = &dev->ep[ep_num];
279 struct s3c_request *req;
280 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
283 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
284 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
285 s3c_ep0_complete_out();
289 if (list_empty(&ep->queue)) {
290 DEBUG_IN_EP("%s: TX DMA done : NULL REQ on IN EP-%d\n",
296 req = list_entry(ep->queue.next, struct s3c_request, queue);
298 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
301 is_short = (xfer_size < ep->ep.maxpacket);
302 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
304 DEBUG_IN_EP("%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
305 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
306 __func__, ep_num, req->req.actual, req->req.length,
307 is_short, ep_tsr, xfer_size);
310 if (dev->ep0state == DATA_STATE_XMIT) {
311 DEBUG_IN_EP("%s: ep_num = %d, ep0stat =="
314 last = write_fifo_ep0(ep, req);
316 dev->ep0state = WAIT_FOR_COMPLETE;
317 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
318 DEBUG_IN_EP("%s: ep_num = %d, completing request\n",
321 dev->ep0state = WAIT_FOR_SETUP;
322 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
323 DEBUG_IN_EP("%s: ep_num = %d, completing request\n",
326 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
327 s3c_ep0_complete_out();
329 DEBUG_IN_EP("%s: ep_num = %d, invalid ep state\n",
335 if (req->req.actual == req->req.length)
338 if (!list_empty(&ep->queue)) {
339 req = list_entry(ep->queue.next, struct s3c_request, queue);
340 DEBUG_IN_EP("%s: Next Tx request start...\n", __func__);
345 static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
347 struct s3c_ep *ep = &dev->ep[ep_num];
348 struct s3c_request *req;
350 DEBUG_IN_EP("%s: Check queue, ep_num = %d\n", __func__, ep_num);
352 if (!list_empty(&ep->queue)) {
353 req = list_entry(ep->queue.next, struct s3c_request, queue);
354 DEBUG_IN_EP("%s: Next Tx request(0x%p) start...\n",
362 DEBUG_IN_EP("%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
369 static void process_ep_in_intr(struct s3c_udc *dev)
371 u32 ep_intr, ep_intr_status;
374 ep_intr = readl(®->daint);
375 DEBUG_IN_EP("*** %s: EP In interrupt : DAINT = 0x%x\n",
378 ep_intr &= DAINT_MASK;
381 if (ep_intr & DAINT_IN_EP_INT(1)) {
382 ep_intr_status = readl(®->in_endp[ep_num].diepint);
383 DEBUG_IN_EP("\tEP%d-IN : DIEPINT = 0x%x\n",
384 ep_num, ep_intr_status);
386 /* Interrupt Clear */
387 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
389 if (ep_intr_status & TRANSFER_DONE) {
390 complete_tx(dev, ep_num);
394 WAIT_FOR_IN_COMPLETE)
395 dev->ep0state = WAIT_FOR_SETUP;
397 if (dev->ep0state == WAIT_FOR_SETUP)
400 /* continue transfer after
401 set_clear_halt for DMA mode */
402 if (clear_feature_flag == 1) {
403 s3c_udc_check_tx_queue(dev,
405 clear_feature_flag = 0;
415 static void process_ep_out_intr(struct s3c_udc *dev)
417 u32 ep_intr, ep_intr_status;
420 ep_intr = readl(®->daint);
421 DEBUG_OUT_EP("*** %s: EP OUT interrupt : DAINT = 0x%x\n",
424 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
428 ep_intr_status = readl(®->out_endp[ep_num].doepint);
429 DEBUG_OUT_EP("\tEP%d-OUT : DOEPINT = 0x%x\n",
430 ep_num, ep_intr_status);
432 /* Interrupt Clear */
433 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
436 if (ep_intr_status & TRANSFER_DONE) {
438 WAIT_FOR_OUT_COMPLETE)
439 complete_rx(dev, ep_num);
441 dev->ep0state = WAIT_FOR_SETUP;
447 CTRL_OUT_EP_SETUP_PHASE_DONE) {
448 DEBUG_OUT_EP("SETUP packet arrived\n");
452 if (ep_intr_status & TRANSFER_DONE)
453 complete_rx(dev, ep_num);
462 * usb client interrupt handler.
464 static int s3c_udc_irq(int irq, void *_dev)
466 struct s3c_udc *dev = _dev;
468 u32 usb_status, gintmsk;
471 spin_lock_irqsave(&dev->lock, flags);
473 intr_status = readl(®->gintsts);
474 gintmsk = readl(®->gintmsk);
476 DEBUG_ISR("\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
477 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
478 __func__, intr_status, state_names[dev->ep0state], gintmsk,
479 readl(®->daint), readl(®->daintmsk));
482 spin_unlock_irqrestore(&dev->lock, flags);
486 if (intr_status & INT_ENUMDONE) {
487 DEBUG_ISR("\tSpeed Detection interrupt\n");
489 writel(INT_ENUMDONE, ®->gintsts);
490 usb_status = (readl(®->dsts) & 0x6);
492 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
493 DEBUG_ISR("\t\tFull Speed Detection\n");
494 set_max_pktsize(dev, USB_SPEED_FULL);
497 DEBUG_ISR("\t\tHigh Speed Detection : 0x%x\n",
499 set_max_pktsize(dev, USB_SPEED_HIGH);
503 if (intr_status & INT_EARLY_SUSPEND) {
504 DEBUG_ISR("\tEarly suspend interrupt\n");
505 writel(INT_EARLY_SUSPEND, ®->gintsts);
508 if (intr_status & INT_SUSPEND) {
509 usb_status = readl(®->dsts);
510 DEBUG_ISR("\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
511 writel(INT_SUSPEND, ®->gintsts);
513 if (dev->gadget.speed != USB_SPEED_UNKNOWN
515 if (dev->driver->suspend)
516 dev->driver->suspend(&dev->gadget);
518 /* HACK to let gadget detect disconnected state */
519 if (dev->driver->disconnect) {
520 spin_unlock_irqrestore(&dev->lock, flags);
521 dev->driver->disconnect(&dev->gadget);
522 spin_lock_irqsave(&dev->lock, flags);
527 if (intr_status & INT_RESUME) {
528 DEBUG_ISR("\tResume interrupt\n");
529 writel(INT_RESUME, ®->gintsts);
531 if (dev->gadget.speed != USB_SPEED_UNKNOWN
533 && dev->driver->resume) {
535 dev->driver->resume(&dev->gadget);
539 if (intr_status & INT_RESET) {
540 usb_status = readl(®->gotgctl);
541 DEBUG_ISR("\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
542 writel(INT_RESET, ®->gintsts);
544 if ((usb_status & 0xc0000) == (0x3 << 18)) {
545 if (reset_available) {
546 DEBUG_ISR("\t\tOTG core got reset (%d)!!\n",
549 dev->ep0state = WAIT_FOR_SETUP;
557 DEBUG_ISR("\t\tRESET handling skipped\n");
561 if (intr_status & INT_IN_EP)
562 process_ep_in_intr(dev);
564 if (intr_status & INT_OUT_EP)
565 process_ep_out_intr(dev);
567 spin_unlock_irqrestore(&dev->lock, flags);
572 /** Queue one request
573 * Kickstart transfer if needed
575 static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
578 struct s3c_request *req;
584 req = container_of(_req, struct s3c_request, req);
585 if (unlikely(!_req || !_req->complete || !_req->buf
586 || !list_empty(&req->queue))) {
588 DEBUG("%s: bad params\n", __func__);
592 ep = container_of(_ep, struct s3c_ep, ep);
594 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
596 DEBUG("%s: bad ep: %s, %d, %x\n", __func__,
597 ep->ep.name, !ep->desc, _ep);
601 ep_num = ep_index(ep);
603 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
605 DEBUG("%s: bogus device state %p\n", __func__, dev->driver);
609 spin_lock_irqsave(&dev->lock, flags);
611 _req->status = -EINPROGRESS;
614 /* kickstart this i/o queue? */
615 DEBUG("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
616 "Q empty = %d, stopped = %d\n",
617 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
618 _req, _req->length, _req->buf,
619 list_empty(&ep->queue), ep->stopped);
623 int i, len = _req->length;
628 for (i = 0; i < len; i++) {
629 printf("%02x", ((u8 *)_req->buf)[i]);
637 if (list_empty(&ep->queue) && !ep->stopped) {
641 list_add_tail(&req->queue, &ep->queue);
642 s3c_ep0_kick(dev, ep);
645 } else if (ep_is_in(ep)) {
646 gintsts = readl(®->gintsts);
647 DEBUG_IN_EP("%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
652 gintsts = readl(®->gintsts);
653 DEBUG_OUT_EP("%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
660 /* pio or dma irq handler advances the queue. */
661 if (likely(req != 0))
662 list_add_tail(&req->queue, &ep->queue);
664 spin_unlock_irqrestore(&dev->lock, flags);
669 /****************************************************************/
670 /* End Point 0 related functions */
671 /****************************************************************/
673 /* return: 0 = still running, 1 = completed, negative = errno */
674 static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
680 max = ep_maxpacket(ep);
682 DEBUG_EP0("%s: max = %d\n", __func__, max);
684 count = setdma_tx(ep, req);
686 /* last packet is usually short (or a zlp) */
687 if (likely(count != max))
690 if (likely(req->req.length != req->req.actual + count)
697 DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __func__,
700 req->req.length - req->req.actual - count, req);
702 /* requests complete when all IN data is in the FIFO */
704 ep->dev->ep0state = WAIT_FOR_SETUP;
711 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
715 bytes = sizeof(struct usb_ctrlrequest);
717 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
718 (unsigned long) ep->dev->dma_buf[ep_index(ep)]
721 DEBUG_EP0("%s: bytes=%d, ep_index=%d %p\n", __func__,
722 bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
728 * udc_set_address - set the USB address for this device
731 * Called from control endpoint function
732 * after it decodes a set address setup packet.
734 static void udc_set_address(struct s3c_udc *dev, unsigned char address)
736 u32 ctrl = readl(®->dcfg);
737 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
739 s3c_udc_ep0_zlp(dev);
741 DEBUG_EP0("%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
742 __func__, address, readl(®->dcfg));
744 dev->usb_address = address;
747 static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
753 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
755 /* set the disable and stall bits */
756 if (ep_ctrl & DEPCTL_EPENA)
757 ep_ctrl |= DEPCTL_EPDIS;
759 ep_ctrl |= DEPCTL_STALL;
761 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
763 DEBUG_EP0("%s: set ep%d stall, DIEPCTL0 = 0x%x\n",
764 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
766 * The application can only set this bit, and the core clears it,
767 * when a SETUP token is received for this endpoint
769 dev->ep0state = WAIT_FOR_SETUP;
774 static void s3c_ep0_read(struct s3c_udc *dev)
776 struct s3c_request *req;
777 struct s3c_ep *ep = &dev->ep[0];
780 if (!list_empty(&ep->queue)) {
781 req = list_entry(ep->queue.next, struct s3c_request, queue);
784 DEBUG("%s: ---> BUG\n", __func__);
789 DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
790 __func__, req, req->req.length, req->req.actual);
792 if (req->req.length == 0) {
793 /* zlp for Set_configuration, Set_interface,
794 * or Bulk-Only mass storge reset */
797 s3c_udc_ep0_zlp(dev);
799 DEBUG_EP0("%s: req.length = 0, bRequest = %d\n",
800 __func__, usb_ctrl->bRequest);
804 ret = setdma_rx(ep, req);
810 static int s3c_ep0_write(struct s3c_udc *dev)
812 struct s3c_request *req;
813 struct s3c_ep *ep = &dev->ep[0];
814 int ret, need_zlp = 0;
816 if (list_empty(&ep->queue))
819 req = list_entry(ep->queue.next, struct s3c_request, queue);
822 DEBUG_EP0("%s: NULL REQ\n", __func__);
826 DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
827 __func__, req, req->req.length, req->req.actual);
829 if (req->req.length - req->req.actual == ep0_fifo_size) {
830 /* Next write will end with the packet size, */
831 /* so we need Zero-length-packet */
835 ret = write_fifo_ep0(ep, req);
837 if ((ret == 1) && !need_zlp) {
839 dev->ep0state = WAIT_FOR_COMPLETE;
840 DEBUG_EP0("%s: finished, waiting for status\n", __func__);
843 dev->ep0state = DATA_STATE_XMIT;
844 DEBUG_EP0("%s: not finished\n", __func__);
852 int s3c_udc_get_status(struct s3c_udc *dev,
853 struct usb_ctrlrequest *crq)
855 u8 ep_num = crq->wIndex & 0x7F;
857 u32 *p = the_controller->dma_buf[1];
859 DEBUG_SETUP("%s: *** USB_REQ_GET_STATUS\n", __func__);
860 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
861 switch (crq->bRequestType & USB_RECIP_MASK) {
862 case USB_RECIP_INTERFACE:
864 DEBUG_SETUP("\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
868 case USB_RECIP_DEVICE:
869 g_status = 0x1; /* Self powered */
870 DEBUG_SETUP("\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
874 case USB_RECIP_ENDPOINT:
875 if (crq->wLength > 2) {
876 DEBUG_SETUP("\tGET_STATUS:Not support EP or wLength\n");
880 g_status = dev->ep[ep_num].stopped;
881 DEBUG_SETUP("\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
890 memcpy(p, &g_status, sizeof(g_status));
892 flush_dcache_range((unsigned long) p,
893 (unsigned long) p + DMA_BUFFER_SIZE);
895 writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma);
896 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
897 ®->in_endp[EP0_CON].dieptsiz);
899 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
900 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
901 ®->in_endp[EP0_CON].diepctl);
902 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
907 static void s3c_udc_set_nak(struct s3c_ep *ep)
912 ep_num = ep_index(ep);
913 DEBUG("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
916 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
917 ep_ctrl |= DEPCTL_SNAK;
918 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
919 DEBUG("%s: set NAK, DIEPCTL%d = 0x%x\n",
920 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
922 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
923 ep_ctrl |= DEPCTL_SNAK;
924 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
925 DEBUG("%s: set NAK, DOEPCTL%d = 0x%x\n",
926 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
933 void s3c_udc_ep_set_stall(struct s3c_ep *ep)
938 ep_num = ep_index(ep);
939 DEBUG("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
942 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
944 /* set the disable and stall bits */
945 if (ep_ctrl & DEPCTL_EPENA)
946 ep_ctrl |= DEPCTL_EPDIS;
948 ep_ctrl |= DEPCTL_STALL;
950 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
951 DEBUG("%s: set stall, DIEPCTL%d = 0x%x\n",
952 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
955 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
957 /* set the stall bit */
958 ep_ctrl |= DEPCTL_STALL;
960 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
961 DEBUG("%s: set stall, DOEPCTL%d = 0x%x\n",
962 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
968 void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
973 ep_num = ep_index(ep);
974 DEBUG("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
977 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
979 /* clear stall bit */
980 ep_ctrl &= ~DEPCTL_STALL;
983 * USB Spec 9.4.5: For endpoints using data toggle, regardless
984 * of whether an endpoint has the Halt feature set, a
985 * ClearFeature(ENDPOINT_HALT) request always results in the
986 * data toggle being reinitialized to DATA0.
988 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
989 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
990 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
993 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
994 DEBUG("%s: cleared stall, DIEPCTL%d = 0x%x\n",
995 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
998 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1000 /* clear stall bit */
1001 ep_ctrl &= ~DEPCTL_STALL;
1003 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1004 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1005 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1008 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1009 DEBUG("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1010 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1016 static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
1019 struct s3c_udc *dev;
1020 unsigned long flags;
1023 ep = container_of(_ep, struct s3c_ep, ep);
1024 ep_num = ep_index(ep);
1026 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1027 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1028 DEBUG("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1032 /* Attempt to halt IN ep will fail if any transfer requests
1033 * are still queue */
1034 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1035 DEBUG("%s: %s queue not empty, req = %p\n",
1036 __func__, ep->ep.name,
1037 list_entry(ep->queue.next, struct s3c_request, queue));
1043 DEBUG("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1045 spin_lock_irqsave(&dev->lock, flags);
1049 s3c_udc_ep_clear_stall(ep);
1052 dev->ep0state = WAIT_FOR_SETUP;
1055 s3c_udc_ep_set_stall(ep);
1058 spin_unlock_irqrestore(&dev->lock, flags);
1063 void s3c_udc_ep_activate(struct s3c_ep *ep)
1066 u32 ep_ctrl = 0, daintmsk = 0;
1068 ep_num = ep_index(ep);
1070 /* Read DEPCTLn register */
1072 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1073 daintmsk = 1 << ep_num;
1075 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1076 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1079 DEBUG("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1080 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1082 /* If the EP is already active don't change the EP Control
1084 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1085 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1086 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1087 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1088 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1089 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1092 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1093 DEBUG("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1094 __func__, ep_num, ep_num,
1095 readl(®->in_endp[ep_num].diepctl));
1097 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1098 DEBUG("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1099 __func__, ep_num, ep_num,
1100 readl(®->out_endp[ep_num].doepctl));
1104 /* Unmask EP Interrtupt */
1105 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1106 DEBUG("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1110 static int s3c_udc_clear_feature(struct usb_ep *_ep)
1112 struct s3c_udc *dev;
1116 ep = container_of(_ep, struct s3c_ep, ep);
1117 ep_num = ep_index(ep);
1120 DEBUG_SETUP("%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1121 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1123 if (usb_ctrl->wLength != 0) {
1124 DEBUG_SETUP("\tCLEAR_FEATURE: wLength is not zero.....\n");
1128 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1129 case USB_RECIP_DEVICE:
1130 switch (usb_ctrl->wValue) {
1131 case USB_DEVICE_REMOTE_WAKEUP:
1132 DEBUG_SETUP("\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1135 case USB_DEVICE_TEST_MODE:
1136 DEBUG_SETUP("\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1137 /** @todo Add CLEAR_FEATURE for TEST modes. */
1141 s3c_udc_ep0_zlp(dev);
1144 case USB_RECIP_ENDPOINT:
1145 DEBUG_SETUP("\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1148 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1150 s3c_udc_ep0_set_stall(ep);
1154 s3c_udc_ep0_zlp(dev);
1156 s3c_udc_ep_clear_stall(ep);
1157 s3c_udc_ep_activate(ep);
1160 clear_feature_num = ep_num;
1161 clear_feature_flag = 1;
1169 static int s3c_udc_set_feature(struct usb_ep *_ep)
1171 struct s3c_udc *dev;
1175 ep = container_of(_ep, struct s3c_ep, ep);
1176 ep_num = ep_index(ep);
1179 DEBUG_SETUP("%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1182 if (usb_ctrl->wLength != 0) {
1183 DEBUG_SETUP("\tSET_FEATURE: wLength is not zero.....\n");
1187 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1188 case USB_RECIP_DEVICE:
1189 switch (usb_ctrl->wValue) {
1190 case USB_DEVICE_REMOTE_WAKEUP:
1191 DEBUG_SETUP("\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1193 case USB_DEVICE_B_HNP_ENABLE:
1194 DEBUG_SETUP("\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1197 case USB_DEVICE_A_HNP_SUPPORT:
1198 /* RH port supports HNP */
1199 DEBUG_SETUP("\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1202 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1203 /* other RH port does */
1204 DEBUG_SETUP("\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1208 s3c_udc_ep0_zlp(dev);
1211 case USB_RECIP_INTERFACE:
1212 DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1215 case USB_RECIP_ENDPOINT:
1216 DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1217 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1219 s3c_udc_ep0_set_stall(ep);
1223 s3c_udc_ep_set_stall(ep);
1226 s3c_udc_ep0_zlp(dev);
1234 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1236 void s3c_ep0_setup(struct s3c_udc *dev)
1238 struct s3c_ep *ep = &dev->ep[0];
1239 int i, bytes, is_in;
1242 /* Nuke all previous transfers */
1245 /* read control req from fifo (8 bytes) */
1246 bytes = s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
1248 DEBUG_SETUP("%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1249 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1250 __func__, usb_ctrl->bRequestType,
1251 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1253 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1255 #ifdef DEBUG_S3C_UDC
1257 int i, len = sizeof(*usb_ctrl);
1261 for (i = 0; i < len; i++) {
1262 printf("%02x", ((u8 *)p)[i]);
1270 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1271 usb_ctrl->wLength != 1) {
1272 DEBUG_SETUP("\t%s:GET_MAX_LUN_REQUEST:invalid",
1274 DEBUG_SETUP("wLength = %d, setup returned\n",
1277 s3c_udc_ep0_set_stall(ep);
1278 dev->ep0state = WAIT_FOR_SETUP;
1281 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1282 usb_ctrl->wLength != 0) {
1283 /* Bulk-Only *mass storge reset of class-specific request */
1284 DEBUG_SETUP("%s:BOT Rest:invalid wLength =%d, setup returned\n",
1285 __func__, usb_ctrl->wLength);
1287 s3c_udc_ep0_set_stall(ep);
1288 dev->ep0state = WAIT_FOR_SETUP;
1293 /* Set direction of EP0 */
1294 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1295 ep->bEndpointAddress |= USB_DIR_IN;
1299 ep->bEndpointAddress &= ~USB_DIR_IN;
1302 /* cope with automagic for some standard requests. */
1303 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1304 == USB_TYPE_STANDARD;
1305 dev->req_config = 0;
1306 dev->req_pending = 1;
1308 /* Handle some SETUP packets ourselves */
1310 switch (usb_ctrl->bRequest) {
1311 case USB_REQ_SET_ADDRESS:
1312 DEBUG_SETUP("%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1313 __func__, usb_ctrl->wValue);
1314 if (usb_ctrl->bRequestType
1315 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1318 udc_set_address(dev, usb_ctrl->wValue);
1321 case USB_REQ_SET_CONFIGURATION:
1322 DEBUG_SETUP("=====================================\n");
1323 DEBUG_SETUP("%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1324 __func__, usb_ctrl->wValue);
1326 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE) {
1327 reset_available = 1;
1328 dev->req_config = 1;
1332 case USB_REQ_GET_DESCRIPTOR:
1333 DEBUG_SETUP("%s: *** USB_REQ_GET_DESCRIPTOR\n",
1337 case USB_REQ_SET_INTERFACE:
1338 DEBUG_SETUP("%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1339 __func__, usb_ctrl->wValue);
1341 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE) {
1342 reset_available = 1;
1343 dev->req_config = 1;
1347 case USB_REQ_GET_CONFIGURATION:
1348 DEBUG_SETUP("%s: *** USB_REQ_GET_CONFIGURATION\n",
1352 case USB_REQ_GET_STATUS:
1353 if (!s3c_udc_get_status(dev, usb_ctrl))
1358 case USB_REQ_CLEAR_FEATURE:
1359 ep_num = usb_ctrl->wIndex & 0x7f;
1361 if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
1366 case USB_REQ_SET_FEATURE:
1367 ep_num = usb_ctrl->wIndex & 0x7f;
1369 if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
1375 DEBUG_SETUP("%s: *** Default of usb_ctrl->bRequest=0x%x"
1376 "happened.\n", __func__, usb_ctrl->bRequest);
1382 if (likely(dev->driver)) {
1383 /* device-2-host (IN) or no data setup command,
1384 * process immediately */
1385 DEBUG_SETUP("%s:usb_ctrlreq will be passed to fsg_setup()\n",
1388 spin_unlock(&dev->lock);
1389 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1390 spin_lock(&dev->lock);
1393 if (dev->req_config) {
1394 DEBUG_SETUP("\tconfig change 0x%02x fail %d?\n",
1395 (u32)usb_ctrl->bRequest, i);
1399 /* setup processing failed, force stall */
1400 s3c_udc_ep0_set_stall(ep);
1401 dev->ep0state = WAIT_FOR_SETUP;
1403 DEBUG_SETUP("\tdev->driver->setup failed (%d),"
1405 i, usb_ctrl->bRequest);
1408 } else if (dev->req_pending) {
1409 dev->req_pending = 0;
1410 DEBUG_SETUP("\tdev->req_pending...\n");
1413 DEBUG_SETUP("\tep0state = %s\n", state_names[dev->ep0state]);
1419 * handle ep0 interrupt
1421 static void s3c_handle_ep0(struct s3c_udc *dev)
1423 if (dev->ep0state == WAIT_FOR_SETUP) {
1424 DEBUG_OUT_EP("%s: WAIT_FOR_SETUP\n", __func__);
1428 DEBUG_OUT_EP("%s: strange state!!(state = %s)\n",
1429 __func__, state_names[dev->ep0state]);
1433 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
1435 DEBUG_EP0("%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1437 dev->ep0state = DATA_STATE_XMIT;
1441 dev->ep0state = DATA_STATE_RECV;