2 # USB Host Controller Drivers
4 comment "USB Host Controller Drivers"
10 bool "xHCI HCD (USB 3.0) support"
13 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
14 "SuperSpeed" host controller hardware.
19 bool "DesignWare USB3 DRD Core Support"
21 Say Y or if your system has a Dual Role SuperSpeed
22 USB controller based on the DesignWare USB3 IP Core.
25 bool "MVEBU USB 3.0 support"
30 Choose this option to add support for USB 3.0 driver on mvebu
31 SoCs, which includes Armada8K, Armada3700 and other Armada
35 bool "Support for PCI-based xHCI USB controller"
39 Enables support for the PCI-based xHCI controller.
41 config USB_XHCI_ROCKCHIP
42 bool "Support for Rockchip on-chip xHCI USB controller"
43 depends on ARCH_ROCKCHIP
44 depends on DM_REGULATOR
48 Enables support for the on-chip xHCI controller on Rockchip SoCs.
51 bool "Renesas RCar USB 3.0 support"
53 depends on ARCH_RMOBILE
55 Choose this option to add support for USB 3.0 driver on Renesas
59 bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"
63 Enables support for the on-chip xHCI controller on STMicroelectronics
64 STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic
65 to configure the controller.
67 config USB_XHCI_ZYNQMP
68 bool "Support for Xilinx ZynqMP on-chip xHCI USB controller"
69 depends on ARCH_ZYNQMP
71 Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs.
73 config USB_XHCI_DRA7XX_INDEX
74 int "DRA7XX xHCI USB index"
79 Select the DRA7XX xHCI USB index.
80 Current supported values: 0, 1.
83 bool "Support for NXP Layerscape on-chip xHCI USB controller"
84 default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
85 depends on !SPL_NO_USB
87 Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
91 bool "EHCI HCD (USB 2.0) support"
92 default y if ARCH_MX5 || ARCH_MX6
95 The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
96 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
97 If your USB host controller supports USB 2.0, you will likely want to
98 configure this Host Controller Driver.
100 EHCI controllers are packaged with "companion" host controllers (OHCI
101 or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports
102 will connect to EHCI if the device is high speed, otherwise they
103 connect to a companion controller. If you configure EHCI, you should
104 probably configure the OHCI (for NEC and some other vendors) USB Host
105 Controller Driver or UHCI (for Via motherboards) Host Controller
108 You may want to read <file:Documentation/usb/ehci.txt>.
112 config USB_EHCI_ATMEL
113 bool "Support for Atmel on-chip EHCI USB controller"
117 Enables support for the on-chip EHCI controller on Atmel chips.
119 config USB_EHCI_MARVELL
120 bool "Support for Marvell on-chip EHCI USB controller"
121 depends on ARCH_MVEBU || KIRKWOOD || ORION5X
124 Enables support for the on-chip EHCI controller on MVEBU SoCs.
127 bool "Support for i.MX6 on-chip EHCI USB controller"
131 Enables support for the on-chip EHCI controller on i.MX6 SoCs.
134 bool "Support for i.MX7 on-chip EHCI USB controller"
138 Enables support for the on-chip EHCI controller on i.MX7 SoCs.
141 bool "Support for OMAP3+ on-chip EHCI USB controller"
142 depends on ARCH_OMAP2PLUS
145 Enables support for the on-chip EHCI controller on OMAP3 and later
150 config MXC_USB_OTG_HACTIVE
151 bool "USB Power pin high active"
153 Set the USB Power pin polarity to be high active (PWR_POL)
158 bool "Support for Qualcomm on-chip EHCI USB controller"
160 select USB_ULPI_VIEWPORT
163 Enables support for the on-chip EHCI controller on Qualcomm
165 This driver supports combination of Chipidea USB controller
166 and Synapsys USB PHY in host mode only.
169 bool "Support for PCI-based EHCI USB controller"
172 Enables support for the PCI-based EHCI controller.
175 bool "Support for Xilinx Zynq on-chip EHCI USB controller"
179 Enable support for Zynq on-chip EHCI USB controller
181 config USB_EHCI_GENERIC
182 bool "Support for generic EHCI USB controller"
183 depends on OF_CONTROL
187 Enables support for generic EHCI controller.
190 bool "Support for FSL on-chip EHCI USB controller"
192 select CONFIG_EHCI_HCD_INIT_AFTER_RESET
194 Enables support for the on-chip EHCI controller on FSL chips.
198 bool "OHCI HCD (USB 1.1) support"
200 The Open Host Controller Interface (OHCI) is a standard for accessing
201 USB 1.1 host controller hardware. It does more in hardware than Intel's
202 UHCI specification. If your USB host controller follows the OHCI spec,
203 say Y. On most non-x86 systems, and on x86 hardware that's not using a
204 USB controller from Intel or VIA, this is appropriate. If your host
205 controller doesn't use PCI, this is probably appropriate. For a PCI
206 based system where you're not sure, the "lspci -v" entry will list the
207 right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI.
211 config USB_OHCI_GENERIC
212 bool "Support for generic OHCI USB controller"
213 depends on OF_CONTROL
217 Enables support for generic OHCI controller.
222 bool "UHCI HCD (most Intel and VIA) support"
225 The Universal Host Controller Interface is a standard by Intel for
226 accessing the USB hardware in the PC (which is also called the USB
227 host controller). If your USB host controller conforms to this
228 standard, you may want to say Y, but see below. All recent boards
229 with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX,
230 i810, i820) conform to this standard. Also all VIA PCI chipsets
231 (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro
232 133) and LEON/GRLIB SoCs with the GRUSBHC controller.
240 bool "DesignWare USB2 Core support"
243 The DesignWare USB 2.0 controller is compliant with the
244 USB-Implementers Forum (USB-IF) USB 2.0 specifications.
245 Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
246 operation is compliant to the controller Supplement. If you want to
247 enable this controller in host mode, say Y.
250 config USB_DWC2_BUFFER_SIZE
251 int "Data buffer size in kB"
254 By default 64 kB buffer is used but if amount of RAM avaialble on
255 the target is not enough to accommodate allocation of buffer of
256 that size it is possible to shrink it. Smaller sizes should be fine
257 because larger transactions could be split in smaller ones.