2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <usbroothubdes.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 /* Use only HC channel 0. */
24 #define DWC2_HC_CHANNEL 0
26 #define DWC2_STATUS_BUF_SIZE 64
27 #define DWC2_DATA_BUF_SIZE (64 * 1024)
30 #define MAX_ENDPOINT 16
34 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
35 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
37 uint8_t *aligned_buffer;
38 uint8_t *status_buffer;
40 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
41 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
42 struct dwc2_core_regs *regs;
49 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
50 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
52 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
55 static struct dwc2_priv local;
63 * Initializes the FSLSPClkSel field of the HCFG register
64 * depending on the PHY type.
66 static void init_fslspclksel(struct dwc2_core_regs *regs)
70 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
71 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
73 /* High speed PHY running at full speed or high speed */
74 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
77 #ifdef CONFIG_DWC2_ULPI_FS_LS
78 uint32_t hwcfg2 = readl(®s->ghwcfg2);
79 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
80 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
81 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
82 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
84 if (hval == 2 && fval == 1)
85 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
88 clrsetbits_le32(®s->host_regs.hcfg,
89 DWC2_HCFG_FSLSPCLKSEL_MASK,
90 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
96 * @param regs Programming view of DWC_otg controller.
97 * @param num Tx FIFO to flush.
99 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
103 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
105 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
108 printf("%s: Timeout!\n", __func__);
110 /* Wait for 3 PHY Clocks */
117 * @param regs Programming view of DWC_otg controller.
119 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
123 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
124 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
127 printf("%s: Timeout!\n", __func__);
129 /* Wait for 3 PHY Clocks */
134 * Do core a soft reset of the core. Be careful with this because it
135 * resets all the internal state machines of the core.
137 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
141 /* Wait for AHB master IDLE state. */
142 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
145 printf("%s: Timeout!\n", __func__);
147 /* Core Soft Reset */
148 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
149 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST,
152 printf("%s: Timeout!\n", __func__);
155 * Wait for core to come out of reset.
156 * NOTE: This long sleep is _very_ important, otherwise the core will
157 * not stay in host mode after a connector ID change!
163 * This function initializes the DWC_otg controller registers for
166 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
167 * request queues. Host channels are reset to ensure that they are ready for
168 * performing transfers.
170 * @param regs Programming view of DWC_otg controller
173 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
175 uint32_t nptxfifosize = 0;
176 uint32_t ptxfifosize = 0;
178 int i, ret, num_channels;
180 /* Restart the Phy Clock */
181 writel(0, ®s->pcgcctl);
183 /* Initialize Host Configuration Register */
184 init_fslspclksel(regs);
185 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
186 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
189 /* Configure data FIFO sizes */
190 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
191 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
193 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
195 /* Non-periodic Tx FIFO */
196 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
197 DWC2_FIFOSIZE_DEPTH_OFFSET;
198 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
199 DWC2_FIFOSIZE_STARTADDR_OFFSET;
200 writel(nptxfifosize, ®s->gnptxfsiz);
202 /* Periodic Tx FIFO */
203 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
204 DWC2_FIFOSIZE_DEPTH_OFFSET;
205 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
206 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
207 DWC2_FIFOSIZE_STARTADDR_OFFSET;
208 writel(ptxfifosize, ®s->hptxfsiz);
212 /* Clear Host Set HNP Enable in the OTG Control Register */
213 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
215 /* Make sure the FIFOs are flushed. */
216 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
217 dwc_otg_flush_rx_fifo(regs);
219 /* Flush out any leftover queued requests. */
220 num_channels = readl(®s->ghwcfg2);
221 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
222 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
225 for (i = 0; i < num_channels; i++)
226 clrsetbits_le32(®s->hc_regs[i].hcchar,
227 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
230 /* Halt all channels to put them into a known state. */
231 for (i = 0; i < num_channels; i++) {
232 clrsetbits_le32(®s->hc_regs[i].hcchar,
234 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
235 ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar,
236 DWC2_HCCHAR_CHEN, false, 1000, false);
238 printf("%s: Timeout!\n", __func__);
241 /* Turn on the vbus power. */
242 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
243 hprt0 = readl(®s->hprt0);
244 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
245 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
246 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
247 hprt0 |= DWC2_HPRT0_PRTPWR;
248 writel(hprt0, ®s->hprt0);
254 * This function initializes the DWC_otg controller registers and
255 * prepares the core for device mode or host mode operation.
257 * @param regs Programming view of the DWC_otg controller
259 static void dwc_otg_core_init(struct dwc2_priv *priv)
261 struct dwc2_core_regs *regs = priv->regs;
264 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
266 /* Common Initialization */
267 usbcfg = readl(®s->gusbcfg);
269 /* Program the ULPI External VBUS bit if needed */
270 if (priv->ext_vbus) {
271 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
272 if (!priv->oc_disable) {
273 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
274 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
277 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
280 /* Set external TS Dline pulsing */
281 #ifdef CONFIG_DWC2_TS_DLINE
282 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
284 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
286 writel(usbcfg, ®s->gusbcfg);
288 /* Reset the Controller */
289 dwc_otg_core_reset(regs);
292 * This programming sequence needs to happen in FS mode before
293 * any other programming occurs
295 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
296 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
297 /* If FS mode with FS PHY */
298 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
300 /* Reset after a PHY select */
301 dwc_otg_core_reset(regs);
304 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
305 * Also do this on HNP Dev/Host mode switches (done in dev_init
308 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
309 init_fslspclksel(regs);
311 #ifdef CONFIG_DWC2_I2C_ENABLE
312 /* Program GUSBCFG.OtgUtmifsSel to I2C */
313 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
315 /* Program GI2CCTL.I2CEn */
316 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
317 DWC2_GI2CCTL_I2CDEVADDR_MASK,
318 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
319 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
323 /* High speed PHY. */
326 * HS PHY parameters. These parameters are preserved during
327 * soft reset so only program the first time. Do a soft reset
328 * immediately after setting phyif.
330 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
331 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
333 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
334 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
335 usbcfg |= DWC2_GUSBCFG_DDRSEL;
337 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
339 } else { /* UTMI+ interface */
340 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
341 usbcfg |= DWC2_GUSBCFG_PHYIF;
345 writel(usbcfg, ®s->gusbcfg);
347 /* Reset after setting the PHY parameters */
348 dwc_otg_core_reset(regs);
351 usbcfg = readl(®s->gusbcfg);
352 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
353 #ifdef CONFIG_DWC2_ULPI_FS_LS
354 uint32_t hwcfg2 = readl(®s->ghwcfg2);
355 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
356 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
357 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
358 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
359 if (hval == 2 && fval == 1) {
360 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
361 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
364 writel(usbcfg, ®s->gusbcfg);
366 /* Program the GAHBCFG Register. */
367 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
368 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
370 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
371 while (brst_sz > 1) {
372 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
373 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
377 #ifdef CONFIG_DWC2_DMA_ENABLE
378 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
382 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
383 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
384 #ifdef CONFIG_DWC2_DMA_ENABLE
385 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
390 writel(ahbcfg, ®s->gahbcfg);
392 /* Program the GUSBCFG register for HNP/SRP. */
393 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
395 #ifdef CONFIG_DWC2_IC_USB_CAP
396 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
401 * Prepares a host channel for transferring packets to/from a specific
402 * endpoint. The HCCHARn register is set up with the characteristics specified
403 * in _hc. Host channel interrupts that may need to be serviced while this
404 * transfer is in progress are enabled.
406 * @param regs Programming view of DWC_otg controller
407 * @param hc Information needed to initialize the host channel
409 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
410 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
411 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
413 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
414 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
415 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
416 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
417 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
418 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
420 if (dev->speed == USB_SPEED_LOW)
421 hcchar |= DWC2_HCCHAR_LSPDDEV;
424 * Program the HCCHARn register with the endpoint characteristics
425 * for the current transfer.
427 writel(hcchar, &hc_regs->hcchar);
429 /* Program the HCSPLIT register, default to no SPLIT */
430 writel(0, &hc_regs->hcsplt);
433 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
434 uint8_t hub_devnum, uint8_t hub_port)
438 hcsplt = DWC2_HCSPLT_SPLTENA;
439 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
440 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
442 /* Program the HCSPLIT register for SPLITs */
443 writel(hcsplt, &hc_regs->hcsplt);
447 * DWC2 to USB API interface
449 /* Direction: In ; Request: Status */
450 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
451 struct usb_device *dev, void *buffer,
452 int txlen, struct devrequest *cmd)
455 uint32_t port_status = 0;
456 uint32_t port_change = 0;
460 switch (cmd->requesttype & ~USB_DIR_IN) {
462 *(uint16_t *)buffer = cpu_to_le16(1);
465 case USB_RECIP_INTERFACE:
466 case USB_RECIP_ENDPOINT:
467 *(uint16_t *)buffer = cpu_to_le16(0);
471 *(uint32_t *)buffer = cpu_to_le32(0);
474 case USB_RECIP_OTHER | USB_TYPE_CLASS:
475 hprt0 = readl(®s->hprt0);
476 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
477 port_status |= USB_PORT_STAT_CONNECTION;
478 if (hprt0 & DWC2_HPRT0_PRTENA)
479 port_status |= USB_PORT_STAT_ENABLE;
480 if (hprt0 & DWC2_HPRT0_PRTSUSP)
481 port_status |= USB_PORT_STAT_SUSPEND;
482 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
483 port_status |= USB_PORT_STAT_OVERCURRENT;
484 if (hprt0 & DWC2_HPRT0_PRTRST)
485 port_status |= USB_PORT_STAT_RESET;
486 if (hprt0 & DWC2_HPRT0_PRTPWR)
487 port_status |= USB_PORT_STAT_POWER;
489 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
490 port_status |= USB_PORT_STAT_LOW_SPEED;
491 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
492 DWC2_HPRT0_PRTSPD_HIGH)
493 port_status |= USB_PORT_STAT_HIGH_SPEED;
495 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
496 port_change |= USB_PORT_STAT_C_ENABLE;
497 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
498 port_change |= USB_PORT_STAT_C_CONNECTION;
499 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
500 port_change |= USB_PORT_STAT_C_OVERCURRENT;
502 *(uint32_t *)buffer = cpu_to_le32(port_status |
503 (port_change << 16));
507 puts("unsupported root hub command\n");
508 stat = USB_ST_STALLED;
511 dev->act_len = min(len, txlen);
517 /* Direction: In ; Request: Descriptor */
518 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
519 void *buffer, int txlen,
520 struct devrequest *cmd)
522 unsigned char data[32];
526 uint16_t wValue = cpu_to_le16(cmd->value);
527 uint16_t wLength = cpu_to_le16(cmd->length);
529 switch (cmd->requesttype & ~USB_DIR_IN) {
531 switch (wValue & 0xff00) {
532 case 0x0100: /* device descriptor */
533 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
534 memcpy(buffer, root_hub_dev_des, len);
536 case 0x0200: /* configuration descriptor */
537 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
538 memcpy(buffer, root_hub_config_des, len);
540 case 0x0300: /* string descriptors */
541 switch (wValue & 0xff) {
543 len = min3(txlen, (int)sizeof(root_hub_str_index0),
545 memcpy(buffer, root_hub_str_index0, len);
548 len = min3(txlen, (int)sizeof(root_hub_str_index1),
550 memcpy(buffer, root_hub_str_index1, len);
555 stat = USB_ST_STALLED;
560 /* Root port config, set 1 port and nothing else. */
563 data[0] = 9; /* min length; */
565 data[2] = dsc & RH_A_NDP;
571 else if (dsc & RH_A_OCPM)
574 /* corresponds to data[4-7] */
575 data[5] = (dsc & RH_A_POTPGT) >> 24;
576 data[7] = dsc & RH_B_DR;
581 data[8] = (dsc & RH_B_DR) >> 8;
586 len = min3(txlen, (int)data[0], (int)wLength);
587 memcpy(buffer, data, len);
590 puts("unsupported root hub command\n");
591 stat = USB_ST_STALLED;
594 dev->act_len = min(len, txlen);
600 /* Direction: In ; Request: Configuration */
601 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
602 void *buffer, int txlen,
603 struct devrequest *cmd)
608 switch (cmd->requesttype & ~USB_DIR_IN) {
610 *(uint8_t *)buffer = 0x01;
614 puts("unsupported root hub command\n");
615 stat = USB_ST_STALLED;
618 dev->act_len = min(len, txlen);
625 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
626 struct usb_device *dev, void *buffer,
627 int txlen, struct devrequest *cmd)
629 switch (cmd->request) {
630 case USB_REQ_GET_STATUS:
631 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
633 case USB_REQ_GET_DESCRIPTOR:
634 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
636 case USB_REQ_GET_CONFIGURATION:
637 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
640 puts("unsupported root hub command\n");
641 return USB_ST_STALLED;
646 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
647 struct usb_device *dev,
648 void *buffer, int txlen,
649 struct devrequest *cmd)
651 struct dwc2_core_regs *regs = priv->regs;
654 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
655 uint16_t wValue = cpu_to_le16(cmd->value);
657 switch (bmrtype_breq & ~USB_DIR_IN) {
658 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
659 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
662 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
664 case USB_PORT_FEAT_C_CONNECTION:
665 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
670 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
672 case USB_PORT_FEAT_SUSPEND:
675 case USB_PORT_FEAT_RESET:
676 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
677 DWC2_HPRT0_PRTCONNDET |
678 DWC2_HPRT0_PRTENCHNG |
679 DWC2_HPRT0_PRTOVRCURRCHNG,
682 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
685 case USB_PORT_FEAT_POWER:
686 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
687 DWC2_HPRT0_PRTCONNDET |
688 DWC2_HPRT0_PRTENCHNG |
689 DWC2_HPRT0_PRTOVRCURRCHNG,
693 case USB_PORT_FEAT_ENABLE:
697 case (USB_REQ_SET_ADDRESS << 8):
698 priv->root_hub_devnum = wValue;
700 case (USB_REQ_SET_CONFIGURATION << 8):
703 puts("unsupported root hub command\n");
704 stat = USB_ST_STALLED;
707 len = min(len, txlen);
715 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
716 unsigned long pipe, void *buffer, int txlen,
717 struct devrequest *cmd)
721 if (usb_pipeint(pipe)) {
722 puts("Root-Hub submit IRQ: NOT implemented\n");
726 if (cmd->requesttype & USB_DIR_IN)
727 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
729 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
736 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
739 uint32_t hcint, hctsiz;
741 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
746 hcint = readl(&hc_regs->hcint);
747 hctsiz = readl(&hc_regs->hctsiz);
748 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
749 DWC2_HCTSIZ_XFERSIZE_OFFSET;
750 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
752 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
755 if (hcint & DWC2_HCINT_XFERCOMP)
758 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
761 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
765 static int dwc2_eptype[] = {
766 DWC2_HCCHAR_EPTYPE_ISOC,
767 DWC2_HCCHAR_EPTYPE_INTR,
768 DWC2_HCCHAR_EPTYPE_CONTROL,
769 DWC2_HCCHAR_EPTYPE_BULK,
772 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
773 u8 *pid, int in, void *buffer, int num_packets,
774 int xfer_len, int *actual_len, int odd_frame)
779 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
780 *pid, xfer_len, num_packets);
782 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
783 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
784 (*pid << DWC2_HCTSIZ_PID_OFFSET),
787 if (!in && xfer_len) {
788 memcpy(aligned_buffer, buffer, xfer_len);
790 flush_dcache_range((unsigned long)aligned_buffer,
791 (unsigned long)aligned_buffer +
792 roundup(xfer_len, ARCH_DMA_MINALIGN));
795 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
797 /* Clear old interrupt conditions for this host channel. */
798 writel(0x3fff, &hc_regs->hcint);
800 /* Set host channel enable after all other setup is complete. */
801 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
802 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
804 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
805 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
808 ret = wait_for_chhltd(hc_regs, &sub, pid);
815 invalidate_dcache_range((unsigned long)aligned_buffer,
816 (unsigned long)aligned_buffer +
817 roundup(xfer_len, ARCH_DMA_MINALIGN));
819 memcpy(buffer, aligned_buffer, xfer_len);
821 *actual_len = xfer_len;
826 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
827 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
829 struct dwc2_core_regs *regs = priv->regs;
830 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
831 struct dwc2_host_regs *host_regs = ®s->host_regs;
832 int devnum = usb_pipedevice(pipe);
833 int ep = usb_pipeendpoint(pipe);
834 int max = usb_maxpacket(dev, pipe);
835 int eptype = dwc2_eptype[usb_pipetype(pipe)];
839 int complete_split = 0;
841 uint32_t num_packets;
842 int stop_transfer = 0;
843 uint32_t max_xfer_len;
844 int ssplit_frame_num = 0;
846 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
849 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
850 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
851 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
852 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
853 max_xfer_len = DWC2_DATA_BUF_SIZE;
855 /* Make sure that max_xfer_len is a multiple of max packet size. */
856 num_packets = max_xfer_len / max;
857 max_xfer_len = num_packets * max;
859 /* Initialize channel */
860 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
863 /* Check if the target is a FS/LS device behind a HS hub */
864 if (dev->speed != USB_SPEED_HIGH) {
867 uint32_t hprt0 = readl(®s->hprt0);
868 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
869 DWC2_HPRT0_PRTSPD_HIGH) {
870 usb_find_usb2_hub_address_port(dev, &hub_addr,
872 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
884 xfer_len = len - done;
886 if (xfer_len > max_xfer_len)
887 xfer_len = max_xfer_len;
888 else if (xfer_len > max)
889 num_packets = (xfer_len + max - 1) / max;
894 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
896 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
898 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
899 int uframe_num = readl(&host_regs->hfnum);
900 if (!(uframe_num & 0x1))
904 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
905 in, (char *)buffer + done, num_packets,
906 xfer_len, &actual_len, odd_frame);
908 hcint = readl(&hc_regs->hcint);
909 if (complete_split) {
911 if (hcint & DWC2_HCINT_NYET) {
913 int frame_num = DWC2_HFNUM_MAX_FRNUM &
914 readl(&host_regs->hfnum);
915 if (((frame_num - ssplit_frame_num) &
916 DWC2_HFNUM_MAX_FRNUM) > 4)
920 } else if (do_split) {
921 if (hcint & DWC2_HCINT_ACK) {
922 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
923 readl(&host_regs->hfnum);
932 if (actual_len < xfer_len)
937 /* Transactions are done when when either all data is transferred or
938 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
941 } while (((done < len) && !stop_transfer) || complete_split);
943 writel(0, &hc_regs->hcintmsk);
944 writel(0xFFFFFFFF, &hc_regs->hcint);
952 /* U-Boot USB transmission interface */
953 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
954 unsigned long pipe, void *buffer, int len)
956 int devnum = usb_pipedevice(pipe);
957 int ep = usb_pipeendpoint(pipe);
960 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
965 if (usb_pipein(pipe))
966 pid = &priv->in_data_toggle[devnum][ep];
968 pid = &priv->out_data_toggle[devnum][ep];
970 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
973 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
974 unsigned long pipe, void *buffer, int len,
975 struct devrequest *setup)
977 int devnum = usb_pipedevice(pipe);
980 /* For CONTROL endpoint pid should start with DATA1 */
981 int status_direction;
983 if (devnum == priv->root_hub_devnum) {
985 dev->speed = USB_SPEED_HIGH;
986 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
991 pid = DWC2_HC_PID_SETUP;
993 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
994 } while (ret == -EAGAIN);
1001 pid = DWC2_HC_PID_DATA1;
1003 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1005 act_len += dev->act_len;
1006 buffer += dev->act_len;
1007 len -= dev->act_len;
1008 } while (ret == -EAGAIN);
1011 status_direction = usb_pipeout(pipe);
1013 /* No-data CONTROL always ends with an IN transaction */
1014 status_direction = 1;
1018 pid = DWC2_HC_PID_DATA1;
1020 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1021 priv->status_buffer, 0);
1022 } while (ret == -EAGAIN);
1026 dev->act_len = act_len;
1031 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1032 unsigned long pipe, void *buffer, int len, int interval)
1034 unsigned long timeout;
1037 /* FIXME: what is interval? */
1039 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1041 if (get_timer(0) > timeout) {
1042 printf("Timeout poll on interrupt endpoint\n");
1045 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1051 static int dwc2_init_common(struct dwc2_priv *priv)
1053 struct dwc2_core_regs *regs = priv->regs;
1057 snpsid = readl(®s->gsnpsid);
1058 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1060 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1061 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1062 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1066 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1072 dwc_otg_core_init(priv);
1073 dwc_otg_core_host_init(regs);
1075 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1076 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1077 DWC2_HPRT0_PRTOVRCURRCHNG,
1080 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1081 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1084 for (i = 0; i < MAX_DEVICE; i++) {
1085 for (j = 0; j < MAX_ENDPOINT; j++) {
1086 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1087 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1094 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1096 /* Put everything in reset. */
1097 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1098 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1099 DWC2_HPRT0_PRTOVRCURRCHNG,
1103 #ifndef CONFIG_DM_USB
1104 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1105 int len, struct devrequest *setup)
1107 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1110 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1113 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1116 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1117 int len, int interval)
1119 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1122 /* U-Boot USB control interface */
1123 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1125 struct dwc2_priv *priv = &local;
1127 memset(priv, '\0', sizeof(*priv));
1128 priv->root_hub_devnum = 0;
1129 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1130 priv->aligned_buffer = aligned_buffer_addr;
1131 priv->status_buffer = status_buffer_addr;
1133 /* board-dependant init */
1134 if (board_usb_init(index, USB_INIT_HOST))
1137 return dwc2_init_common(priv);
1140 int usb_lowlevel_stop(int index)
1142 dwc2_uninit_common(local.regs);
1148 #ifdef CONFIG_DM_USB
1149 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1150 unsigned long pipe, void *buffer, int length,
1151 struct devrequest *setup)
1153 struct dwc2_priv *priv = dev_get_priv(dev);
1155 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1156 dev->name, udev, udev->dev->name, udev->portnr);
1158 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1161 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1162 unsigned long pipe, void *buffer, int length)
1164 struct dwc2_priv *priv = dev_get_priv(dev);
1166 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1168 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1171 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1172 unsigned long pipe, void *buffer, int length,
1175 struct dwc2_priv *priv = dev_get_priv(dev);
1177 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1179 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1182 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1184 struct dwc2_priv *priv = dev_get_priv(dev);
1188 addr = dev_get_addr(dev);
1189 if (addr == FDT_ADDR_T_NONE)
1191 priv->regs = (struct dwc2_core_regs *)addr;
1193 prop = fdt_getprop(gd->fdt_blob, dev->of_offset, "disable-over-current",
1196 priv->oc_disable = true;
1201 static int dwc2_usb_probe(struct udevice *dev)
1203 struct dwc2_priv *priv = dev_get_priv(dev);
1204 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1206 bus_priv->desc_before_addr = true;
1208 return dwc2_init_common(priv);
1211 static int dwc2_usb_remove(struct udevice *dev)
1213 struct dwc2_priv *priv = dev_get_priv(dev);
1215 dwc2_uninit_common(priv->regs);
1220 struct dm_usb_ops dwc2_usb_ops = {
1221 .control = dwc2_submit_control_msg,
1222 .bulk = dwc2_submit_bulk_msg,
1223 .interrupt = dwc2_submit_int_msg,
1226 static const struct udevice_id dwc2_usb_ids[] = {
1227 { .compatible = "brcm,bcm2835-usb" },
1228 { .compatible = "snps,dwc2" },
1232 U_BOOT_DRIVER(usb_dwc2) = {
1235 .of_match = dwc2_usb_ids,
1236 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1237 .probe = dwc2_usb_probe,
1238 .remove = dwc2_usb_remove,
1239 .ops = &dwc2_usb_ops,
1240 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1241 .flags = DM_FLAG_ALLOC_PRIV_DMA,