git.sur5r.net Git - u-boot/blob - drivers/usb/host/dwc2.c

   1 /*
   2  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <usb.h>
  12 #include <malloc.h>
  13 #include <memalign.h>
  14 #include <phys2bus.h>
  15 #include <usbroothubdes.h>
  16 #include <asm/io.h>
  17
  18 #include "dwc2.h"
  19
  20 /* Use only HC channel 0. */
  21 #define DWC2_HC_CHANNEL                 0
  22
  23 #define DWC2_STATUS_BUF_SIZE            64
  24 #define DWC2_DATA_BUF_SIZE              (64 * 1024)
  25
  26 #define MAX_DEVICE                      16
  27 #define MAX_ENDPOINT                    16
  28
  29 struct dwc2_priv {
  30 #ifdef CONFIG_DM_USB
  31         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  32         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  33 #else
  34         uint8_t *aligned_buffer;
  35         uint8_t *status_buffer;
  36 #endif
  37         int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  38         struct dwc2_core_regs *regs;
  39         int root_hub_devnum;
  40 };
  41
  42 #ifndef CONFIG_DM_USB
  43 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  44 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  45                 ARCH_DMA_MINALIGN);
  46 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  47                 ARCH_DMA_MINALIGN);
  48
  49 static struct dwc2_priv local;
  50 #endif
  51
  52 /*
  53  * DWC2 IP interface
  54  */
  55 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
  56 {
  57         unsigned int timeout = 1000000;
  58         uint32_t val;
  59
  60         while (--timeout) {
  61                 val = readl(reg);
  62                 if (!set)
  63                         val = ~val;
  64
  65                 if ((val & mask) == mask)
  66                         return 0;
  67
  68                 udelay(1);
  69         }
  70
  71         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  72               __func__, reg, mask, set);
  73
  74         return -ETIMEDOUT;
  75 }
  76
  77 /*
  78  * Initializes the FSLSPClkSel field of the HCFG register
  79  * depending on the PHY type.
  80  */
  81 static void init_fslspclksel(struct dwc2_core_regs *regs)
  82 {
  83         uint32_t phyclk;
  84
  85 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  86         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  87 #else
  88         /* High speed PHY running at full speed or high speed */
  89         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  90 #endif
  91
  92 #ifdef CONFIG_DWC2_ULPI_FS_LS
  93         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  94         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  95                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  96         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  97                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  98
  99         if (hval == 2 && fval == 1)
 100                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
 101 #endif
 102
 103         clrsetbits_le32(&regs->host_regs.hcfg,
 104                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 105                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 106 }
 107
 108 /*
 109  * Flush a Tx FIFO.
 110  *
 111  * @param regs Programming view of DWC_otg controller.
 112  * @param num Tx FIFO to flush.
 113  */
 114 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 115 {
 116         int ret;
 117
 118         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 119                &regs->grstctl);
 120         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
 121         if (ret)
 122                 printf("%s: Timeout!\n", __func__);
 123
 124         /* Wait for 3 PHY Clocks */
 125         udelay(1);
 126 }
 127
 128 /*
 129  * Flush Rx FIFO.
 130  *
 131  * @param regs Programming view of DWC_otg controller.
 132  */
 133 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 134 {
 135         int ret;
 136
 137         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 138         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
 139         if (ret)
 140                 printf("%s: Timeout!\n", __func__);
 141
 142         /* Wait for 3 PHY Clocks */
 143         udelay(1);
 144 }
 145
 146 /*
 147  * Do core a soft reset of the core.  Be careful with this because it
 148  * resets all the internal state machines of the core.
 149  */
 150 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 151 {
 152         int ret;
 153
 154         /* Wait for AHB master IDLE state. */
 155         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
 156         if (ret)
 157                 printf("%s: Timeout!\n", __func__);
 158
 159         /* Core Soft Reset */
 160         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 161         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
 162         if (ret)
 163                 printf("%s: Timeout!\n", __func__);
 164
 165         /*
 166          * Wait for core to come out of reset.
 167          * NOTE: This long sleep is _very_ important, otherwise the core will
 168          *       not stay in host mode after a connector ID change!
 169          */
 170         mdelay(100);
 171 }
 172
 173 /*
 174  * This function initializes the DWC_otg controller registers for
 175  * host mode.
 176  *
 177  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 178  * request queues. Host channels are reset to ensure that they are ready for
 179  * performing transfers.
 180  *
 181  * @param regs Programming view of DWC_otg controller
 182  *
 183  */
 184 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
 185 {
 186         uint32_t nptxfifosize = 0;
 187         uint32_t ptxfifosize = 0;
 188         uint32_t hprt0 = 0;
 189         int i, ret, num_channels;
 190
 191         /* Restart the Phy Clock */
 192         writel(0, &regs->pcgcctl);
 193
 194         /* Initialize Host Configuration Register */
 195         init_fslspclksel(regs);
 196 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 197         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 198 #endif
 199
 200         /* Configure data FIFO sizes */
 201 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 202         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 203                 /* Rx FIFO */
 204                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 205
 206                 /* Non-periodic Tx FIFO */
 207                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 208                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 209                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 210                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 211                 writel(nptxfifosize, &regs->gnptxfsiz);
 212
 213                 /* Periodic Tx FIFO */
 214                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 215                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 216                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 217                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 218                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 219                 writel(ptxfifosize, &regs->hptxfsiz);
 220         }
 221 #endif
 222
 223         /* Clear Host Set HNP Enable in the OTG Control Register */
 224         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 225
 226         /* Make sure the FIFOs are flushed. */
 227         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 228         dwc_otg_flush_rx_fifo(regs);
 229
 230         /* Flush out any leftover queued requests. */
 231         num_channels = readl(&regs->ghwcfg2);
 232         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 233         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 234         num_channels += 1;
 235
 236         for (i = 0; i < num_channels; i++)
 237                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 238                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 239                                 DWC2_HCCHAR_CHDIS);
 240
 241         /* Halt all channels to put them into a known state. */
 242         for (i = 0; i < num_channels; i++) {
 243                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 244                                 DWC2_HCCHAR_EPDIR,
 245                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 246                 ret = wait_for_bit(&regs->hc_regs[i].hcchar,
 247                                    DWC2_HCCHAR_CHEN, 0);
 248                 if (ret)
 249                         printf("%s: Timeout!\n", __func__);
 250         }
 251
 252         /* Turn on the vbus power. */
 253         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 254                 hprt0 = readl(&regs->hprt0);
 255                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 256                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 257                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 258                         hprt0 |= DWC2_HPRT0_PRTPWR;
 259                         writel(hprt0, &regs->hprt0);
 260                 }
 261         }
 262 }
 263
 264 /*
 265  * This function initializes the DWC_otg controller registers and
 266  * prepares the core for device mode or host mode operation.
 267  *
 268  * @param regs Programming view of the DWC_otg controller
 269  */
 270 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
 271 {
 272         uint32_t ahbcfg = 0;
 273         uint32_t usbcfg = 0;
 274         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 275
 276         /* Common Initialization */
 277         usbcfg = readl(&regs->gusbcfg);
 278
 279         /* Program the ULPI External VBUS bit if needed */
 280 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
 281         usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 282 #else
 283         usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 284 #endif
 285
 286         /* Set external TS Dline pulsing */
 287 #ifdef CONFIG_DWC2_TS_DLINE
 288         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 289 #else
 290         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 291 #endif
 292         writel(usbcfg, &regs->gusbcfg);
 293
 294         /* Reset the Controller */
 295         dwc_otg_core_reset(regs);
 296
 297         /*
 298          * This programming sequence needs to happen in FS mode before
 299          * any other programming occurs
 300          */
 301 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 302         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 303         /* If FS mode with FS PHY */
 304         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 305
 306         /* Reset after a PHY select */
 307         dwc_otg_core_reset(regs);
 308
 309         /*
 310          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 311          * Also do this on HNP Dev/Host mode switches (done in dev_init
 312          * and host_init).
 313          */
 314         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 315                 init_fslspclksel(regs);
 316
 317 #ifdef CONFIG_DWC2_I2C_ENABLE
 318         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 319         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 320
 321         /* Program GI2CCTL.I2CEn */
 322         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 323                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 324                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 325         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 326 #endif
 327
 328 #else
 329         /* High speed PHY. */
 330
 331         /*
 332          * HS PHY parameters. These parameters are preserved during
 333          * soft reset so only program the first time. Do a soft reset
 334          * immediately after setting phyif.
 335          */
 336         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 337         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 338
 339         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 340 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 341                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 342 #else
 343                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 344 #endif
 345         } else {        /* UTMI+ interface */
 346 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
 347                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 348 #endif
 349         }
 350
 351         writel(usbcfg, &regs->gusbcfg);
 352
 353         /* Reset after setting the PHY parameters */
 354         dwc_otg_core_reset(regs);
 355 #endif
 356
 357         usbcfg = readl(&regs->gusbcfg);
 358         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 359 #ifdef CONFIG_DWC2_ULPI_FS_LS
 360         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 361         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 362                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 363         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 364                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 365         if (hval == 2 && fval == 1) {
 366                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 367                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 368         }
 369 #endif
 370         writel(usbcfg, &regs->gusbcfg);
 371
 372         /* Program the GAHBCFG Register. */
 373         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 374         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 375                 break;
 376         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 377                 while (brst_sz > 1) {
 378                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 379                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 380                         brst_sz >>= 1;
 381                 }
 382
 383 #ifdef CONFIG_DWC2_DMA_ENABLE
 384                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 385 #endif
 386                 break;
 387
 388         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 389                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 390 #ifdef CONFIG_DWC2_DMA_ENABLE
 391                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 392 #endif
 393                 break;
 394         }
 395
 396         writel(ahbcfg, &regs->gahbcfg);
 397
 398         /* Program the GUSBCFG register for HNP/SRP. */
 399         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
 400
 401 #ifdef CONFIG_DWC2_IC_USB_CAP
 402         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
 403 #endif
 404 }
 405
 406 /*
 407  * Prepares a host channel for transferring packets to/from a specific
 408  * endpoint. The HCCHARn register is set up with the characteristics specified
 409  * in _hc. Host channel interrupts that may need to be serviced while this
 410  * transfer is in progress are enabled.
 411  *
 412  * @param regs Programming view of DWC_otg controller
 413  * @param hc Information needed to initialize the host channel
 414  */
 415 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 416                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 417                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 418 {
 419         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 420         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 421                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 422                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 423                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 424                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 425
 426         if (dev->speed == USB_SPEED_LOW)
 427                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 428
 429         /* Clear old interrupt conditions for this host channel. */
 430         writel(0x3fff, &hc_regs->hcint);
 431
 432         /*
 433          * Program the HCCHARn register with the endpoint characteristics
 434          * for the current transfer.
 435          */
 436         writel(hcchar, &hc_regs->hcchar);
 437
 438         /* Program the HCSPLIT register for SPLITs */
 439         writel(0, &hc_regs->hcsplt);
 440 }
 441
 442 /*
 443  * DWC2 to USB API interface
 444  */
 445 /* Direction: In ; Request: Status */
 446 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 447                                            struct usb_device *dev, void *buffer,
 448                                            int txlen, struct devrequest *cmd)
 449 {
 450         uint32_t hprt0 = 0;
 451         uint32_t port_status = 0;
 452         uint32_t port_change = 0;
 453         int len = 0;
 454         int stat = 0;
 455
 456         switch (cmd->requesttype & ~USB_DIR_IN) {
 457         case 0:
 458                 *(uint16_t *)buffer = cpu_to_le16(1);
 459                 len = 2;
 460                 break;
 461         case USB_RECIP_INTERFACE:
 462         case USB_RECIP_ENDPOINT:
 463                 *(uint16_t *)buffer = cpu_to_le16(0);
 464                 len = 2;
 465                 break;
 466         case USB_TYPE_CLASS:
 467                 *(uint32_t *)buffer = cpu_to_le32(0);
 468                 len = 4;
 469                 break;
 470         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 471                 hprt0 = readl(&regs->hprt0);
 472                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 473                         port_status |= USB_PORT_STAT_CONNECTION;
 474                 if (hprt0 & DWC2_HPRT0_PRTENA)
 475                         port_status |= USB_PORT_STAT_ENABLE;
 476                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 477                         port_status |= USB_PORT_STAT_SUSPEND;
 478                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 479                         port_status |= USB_PORT_STAT_OVERCURRENT;
 480                 if (hprt0 & DWC2_HPRT0_PRTRST)
 481                         port_status |= USB_PORT_STAT_RESET;
 482                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 483                         port_status |= USB_PORT_STAT_POWER;
 484
 485                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 486                         port_status |= USB_PORT_STAT_LOW_SPEED;
 487                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 488                          DWC2_HPRT0_PRTSPD_HIGH)
 489                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 490
 491                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 492                         port_change |= USB_PORT_STAT_C_ENABLE;
 493                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 494                         port_change |= USB_PORT_STAT_C_CONNECTION;
 495                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 496                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 497
 498                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 499                                         (port_change << 16));
 500                 len = 4;
 501                 break;
 502         default:
 503                 puts("unsupported root hub command\n");
 504                 stat = USB_ST_STALLED;
 505         }
 506
 507         dev->act_len = min(len, txlen);
 508         dev->status = stat;
 509
 510         return stat;
 511 }
 512
 513 /* Direction: In ; Request: Descriptor */
 514 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 515                                                void *buffer, int txlen,
 516                                                struct devrequest *cmd)
 517 {
 518         unsigned char data[32];
 519         uint32_t dsc;
 520         int len = 0;
 521         int stat = 0;
 522         uint16_t wValue = cpu_to_le16(cmd->value);
 523         uint16_t wLength = cpu_to_le16(cmd->length);
 524
 525         switch (cmd->requesttype & ~USB_DIR_IN) {
 526         case 0:
 527                 switch (wValue & 0xff00) {
 528                 case 0x0100:    /* device descriptor */
 529                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 530                         memcpy(buffer, root_hub_dev_des, len);
 531                         break;
 532                 case 0x0200:    /* configuration descriptor */
 533                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 534                         memcpy(buffer, root_hub_config_des, len);
 535                         break;
 536                 case 0x0300:    /* string descriptors */
 537                         switch (wValue & 0xff) {
 538                         case 0x00:
 539                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 540                                            (int)wLength);
 541                                 memcpy(buffer, root_hub_str_index0, len);
 542                                 break;
 543                         case 0x01:
 544                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 545                                            (int)wLength);
 546                                 memcpy(buffer, root_hub_str_index1, len);
 547                                 break;
 548                         }
 549                         break;
 550                 default:
 551                         stat = USB_ST_STALLED;
 552                 }
 553                 break;
 554
 555         case USB_TYPE_CLASS:
 556                 /* Root port config, set 1 port and nothing else. */
 557                 dsc = 0x00000001;
 558
 559                 data[0] = 9;            /* min length; */
 560                 data[1] = 0x29;
 561                 data[2] = dsc & RH_A_NDP;
 562                 data[3] = 0;
 563                 if (dsc & RH_A_PSM)
 564                         data[3] |= 0x1;
 565                 if (dsc & RH_A_NOCP)
 566                         data[3] |= 0x10;
 567                 else if (dsc & RH_A_OCPM)
 568                         data[3] |= 0x8;
 569
 570                 /* corresponds to data[4-7] */
 571                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 572                 data[7] = dsc & RH_B_DR;
 573                 if (data[2] < 7) {
 574                         data[8] = 0xff;
 575                 } else {
 576                         data[0] += 2;
 577                         data[8] = (dsc & RH_B_DR) >> 8;
 578                         data[9] = 0xff;
 579                         data[10] = data[9];
 580                 }
 581
 582                 len = min3(txlen, (int)data[0], (int)wLength);
 583                 memcpy(buffer, data, len);
 584                 break;
 585         default:
 586                 puts("unsupported root hub command\n");
 587                 stat = USB_ST_STALLED;
 588         }
 589
 590         dev->act_len = min(len, txlen);
 591         dev->status = stat;
 592
 593         return stat;
 594 }
 595
 596 /* Direction: In ; Request: Configuration */
 597 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 598                                                   void *buffer, int txlen,
 599                                                   struct devrequest *cmd)
 600 {
 601         int len = 0;
 602         int stat = 0;
 603
 604         switch (cmd->requesttype & ~USB_DIR_IN) {
 605         case 0:
 606                 *(uint8_t *)buffer = 0x01;
 607                 len = 1;
 608                 break;
 609         default:
 610                 puts("unsupported root hub command\n");
 611                 stat = USB_ST_STALLED;
 612         }
 613
 614         dev->act_len = min(len, txlen);
 615         dev->status = stat;
 616
 617         return stat;
 618 }
 619
 620 /* Direction: In */
 621 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 622                                     struct usb_device *dev, void *buffer,
 623                                     int txlen, struct devrequest *cmd)
 624 {
 625         switch (cmd->request) {
 626         case USB_REQ_GET_STATUS:
 627                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 628                                                        txlen, cmd);
 629         case USB_REQ_GET_DESCRIPTOR:
 630                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 631                                                            txlen, cmd);
 632         case USB_REQ_GET_CONFIGURATION:
 633                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 634                                                               txlen, cmd);
 635         default:
 636                 puts("unsupported root hub command\n");
 637                 return USB_ST_STALLED;
 638         }
 639 }
 640
 641 /* Direction: Out */
 642 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 643                                      struct usb_device *dev,
 644                                      void *buffer, int txlen,
 645                                      struct devrequest *cmd)
 646 {
 647         struct dwc2_core_regs *regs = priv->regs;
 648         int len = 0;
 649         int stat = 0;
 650         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 651         uint16_t wValue = cpu_to_le16(cmd->value);
 652
 653         switch (bmrtype_breq & ~USB_DIR_IN) {
 654         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 655         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 656                 break;
 657
 658         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 659                 switch (wValue) {
 660                 case USB_PORT_FEAT_C_CONNECTION:
 661                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 662                         break;
 663                 }
 664                 break;
 665
 666         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 667                 switch (wValue) {
 668                 case USB_PORT_FEAT_SUSPEND:
 669                         break;
 670
 671                 case USB_PORT_FEAT_RESET:
 672                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 673                                         DWC2_HPRT0_PRTCONNDET |
 674                                         DWC2_HPRT0_PRTENCHNG |
 675                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 676                                         DWC2_HPRT0_PRTRST);
 677                         mdelay(50);
 678                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 679                         break;
 680
 681                 case USB_PORT_FEAT_POWER:
 682                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 683                                         DWC2_HPRT0_PRTCONNDET |
 684                                         DWC2_HPRT0_PRTENCHNG |
 685                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 686                                         DWC2_HPRT0_PRTRST);
 687                         break;
 688
 689                 case USB_PORT_FEAT_ENABLE:
 690                         break;
 691                 }
 692                 break;
 693         case (USB_REQ_SET_ADDRESS << 8):
 694                 priv->root_hub_devnum = wValue;
 695                 break;
 696         case (USB_REQ_SET_CONFIGURATION << 8):
 697                 break;
 698         default:
 699                 puts("unsupported root hub command\n");
 700                 stat = USB_ST_STALLED;
 701         }
 702
 703         len = min(len, txlen);
 704
 705         dev->act_len = len;
 706         dev->status = stat;
 707
 708         return stat;
 709 }
 710
 711 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 712                                  unsigned long pipe, void *buffer, int txlen,
 713                                  struct devrequest *cmd)
 714 {
 715         int stat = 0;
 716
 717         if (usb_pipeint(pipe)) {
 718                 puts("Root-Hub submit IRQ: NOT implemented\n");
 719                 return 0;
 720         }
 721
 722         if (cmd->requesttype & USB_DIR_IN)
 723                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 724         else
 725                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 726
 727         mdelay(1);
 728
 729         return stat;
 730 }
 731
 732 int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
 733                     bool ignore_ack)
 734 {
 735         uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
 736         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 737         int ret;
 738         uint32_t hcint, hctsiz;
 739
 740         ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
 741         if (ret)
 742                 return ret;
 743
 744         hcint = readl(&hc_regs->hcint);
 745         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 746                 return -EAGAIN;
 747         if (ignore_ack)
 748                 hcint &= ~DWC2_HCINT_ACK;
 749         else
 750                 hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
 751         if (hcint != hcint_comp_hlt_ack) {
 752                 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 753                 return -EINVAL;
 754         }
 755
 756         hctsiz = readl(&hc_regs->hctsiz);
 757         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 758                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 759         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 760
 761         debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
 762
 763         return 0;
 764 }
 765
 766 static int dwc2_eptype[] = {
 767         DWC2_HCCHAR_EPTYPE_ISOC,
 768         DWC2_HCCHAR_EPTYPE_INTR,
 769         DWC2_HCCHAR_EPTYPE_CONTROL,
 770         DWC2_HCCHAR_EPTYPE_BULK,
 771 };
 772
 773 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 774               unsigned long pipe, int *pid, int in, void *buffer, int len,
 775               bool ignore_ack)
 776 {
 777         struct dwc2_core_regs *regs = priv->regs;
 778         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 779         int devnum = usb_pipedevice(pipe);
 780         int ep = usb_pipeendpoint(pipe);
 781         int max = usb_maxpacket(dev, pipe);
 782         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 783         int done = 0;
 784         int ret = 0;
 785         uint32_t sub;
 786         uint32_t xfer_len;
 787         uint32_t num_packets;
 788         int stop_transfer = 0;
 789
 790         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 791               in, len);
 792
 793         do {
 794                 /* Initialize channel */
 795                 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 796                                 eptype, max);
 797
 798                 xfer_len = len - done;
 799                 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 800                         xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
 801                 if (xfer_len > DWC2_DATA_BUF_SIZE)
 802                         xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
 803
 804                 /* Make sure that xfer_len is a multiple of max packet size. */
 805                 if (xfer_len > 0) {
 806                         num_packets = (xfer_len + max - 1) / max;
 807                         if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
 808                                 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
 809                                 xfer_len = num_packets * max;
 810                         }
 811                 } else {
 812                         num_packets = 1;
 813                 }
 814
 815                 if (in)
 816                         xfer_len = num_packets * max;
 817
 818                 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 819                       *pid, xfer_len, num_packets);
 820
 821                 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 822                        (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 823                        (*pid << DWC2_HCTSIZ_PID_OFFSET),
 824                        &hc_regs->hctsiz);
 825
 826                 if (!in && xfer_len) {
 827                         memcpy(priv->aligned_buffer, (char *)buffer + done,
 828                                xfer_len);
 829
 830                         flush_dcache_range((unsigned long)priv->aligned_buffer,
 831                                 (unsigned long)((void *)priv->aligned_buffer +
 832                                 roundup(xfer_len, ARCH_DMA_MINALIGN)));
 833                 }
 834
 835                 writel(phys_to_bus((unsigned long)priv->aligned_buffer),
 836                        &hc_regs->hcdma);
 837
 838                 /* Set host channel enable after all other setup is complete. */
 839                 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 840                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
 841                                 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 842                                 DWC2_HCCHAR_CHEN);
 843
 844                 ret = wait_for_chhltd(regs, &sub, pid, ignore_ack);
 845                 if (ret)
 846                         break;
 847
 848                 if (in) {
 849                         xfer_len -= sub;
 850
 851                         invalidate_dcache_range((unsigned long)priv->aligned_buffer,
 852                                 (unsigned long)((void *)priv->aligned_buffer +
 853                                 roundup(xfer_len, ARCH_DMA_MINALIGN)));
 854
 855                         memcpy(buffer + done, priv->aligned_buffer, xfer_len);
 856                         if (sub)
 857                                 stop_transfer = 1;
 858                 }
 859
 860                 done += xfer_len;
 861
 862         } while ((done < len) && !stop_transfer);
 863
 864         writel(0, &hc_regs->hcintmsk);
 865         writel(0xFFFFFFFF, &hc_regs->hcint);
 866
 867         dev->status = 0;
 868         dev->act_len = done;
 869
 870         return ret;
 871 }
 872
 873 /* U-Boot USB transmission interface */
 874 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 875                      unsigned long pipe, void *buffer, int len)
 876 {
 877         int devnum = usb_pipedevice(pipe);
 878         int ep = usb_pipeendpoint(pipe);
 879
 880         if (devnum == priv->root_hub_devnum) {
 881                 dev->status = 0;
 882                 return -EINVAL;
 883         }
 884
 885         return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
 886                          usb_pipein(pipe), buffer, len, true);
 887 }
 888
 889 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
 890                                unsigned long pipe, void *buffer, int len,
 891                                struct devrequest *setup)
 892 {
 893         int devnum = usb_pipedevice(pipe);
 894         int pid, ret, act_len;
 895         /* For CONTROL endpoint pid should start with DATA1 */
 896         int status_direction;
 897
 898         if (devnum == priv->root_hub_devnum) {
 899                 dev->status = 0;
 900                 dev->speed = USB_SPEED_HIGH;
 901                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
 902                                              setup);
 903         }
 904
 905         pid = DWC2_HC_PID_SETUP;
 906         ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8, true);
 907         if (ret)
 908                 return ret;
 909
 910         if (buffer) {
 911                 pid = DWC2_HC_PID_DATA1;
 912                 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer,
 913                                 len, false);
 914                 if (ret)
 915                         return ret;
 916                 act_len = dev->act_len;
 917         } /* End of DATA stage */
 918         else
 919                 act_len = 0;
 920
 921         /* STATUS stage */
 922         if ((len == 0) || usb_pipeout(pipe))
 923                 status_direction = 1;
 924         else
 925                 status_direction = 0;
 926
 927         pid = DWC2_HC_PID_DATA1;
 928         ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
 929                         priv->status_buffer, 0, false);
 930         if (ret)
 931                 return ret;
 932
 933         dev->act_len = act_len;
 934
 935         return 0;
 936 }
 937
 938 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
 939                     unsigned long pipe, void *buffer, int len, int interval)
 940 {
 941         unsigned long timeout;
 942         int ret;
 943
 944         /* FIXME: what is interval? */
 945
 946         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
 947         for (;;) {
 948                 if (get_timer(0) > timeout) {
 949                         printf("Timeout poll on interrupt endpoint\n");
 950                         return -ETIMEDOUT;
 951                 }
 952                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
 953                 if (ret != -EAGAIN)
 954                         return ret;
 955         }
 956 }
 957
 958 static int dwc2_init_common(struct dwc2_priv *priv)
 959 {
 960         struct dwc2_core_regs *regs = priv->regs;
 961         uint32_t snpsid;
 962         int i, j;
 963
 964         snpsid = readl(&regs->gsnpsid);
 965         printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
 966
 967         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
 968             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
 969                 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
 970                 return -ENODEV;
 971         }
 972
 973         dwc_otg_core_init(regs);
 974         dwc_otg_core_host_init(regs);
 975
 976         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 977                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 978                         DWC2_HPRT0_PRTOVRCURRCHNG,
 979                         DWC2_HPRT0_PRTRST);
 980         mdelay(50);
 981         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
 982                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
 983                      DWC2_HPRT0_PRTRST);
 984
 985         for (i = 0; i < MAX_DEVICE; i++) {
 986                 for (j = 0; j < MAX_ENDPOINT; j++)
 987                         priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
 988         }
 989
 990         return 0;
 991 }
 992
 993 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
 994 {
 995         /* Put everything in reset. */
 996         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 997                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 998                         DWC2_HPRT0_PRTOVRCURRCHNG,
 999                         DWC2_HPRT0_PRTRST);
1000 }
1001
1002 #ifndef CONFIG_DM_USB
1003 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1004                        int len, struct devrequest *setup)
1005 {
1006         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1007 }
1008
1009 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1010                     int len)
1011 {
1012         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1013 }
1014
1015 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1016                    int len, int interval)
1017 {
1018         return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1019 }
1020
1021 /* U-Boot USB control interface */
1022 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1023 {
1024         struct dwc2_priv *priv = &local;
1025
1026         memset(priv, '\0', sizeof(*priv));
1027         priv->root_hub_devnum = 0;
1028         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1029         priv->aligned_buffer = aligned_buffer_addr;
1030         priv->status_buffer = status_buffer_addr;
1031
1032         /* board-dependant init */
1033         if (board_usb_init(index, USB_INIT_HOST))
1034                 return -1;
1035
1036         return dwc2_init_common(priv);
1037 }
1038
1039 int usb_lowlevel_stop(int index)
1040 {
1041         dwc2_uninit_common(local.regs);
1042
1043         return 0;
1044 }
1045 #endif
1046
1047 #ifdef CONFIG_DM_USB
1048 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1049                                    unsigned long pipe, void *buffer, int length,
1050                                    struct devrequest *setup)
1051 {
1052         struct dwc2_priv *priv = dev_get_priv(dev);
1053
1054         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1055               dev->name, udev, udev->dev->name, udev->portnr);
1056
1057         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1058 }
1059
1060 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1061                                 unsigned long pipe, void *buffer, int length)
1062 {
1063         struct dwc2_priv *priv = dev_get_priv(dev);
1064
1065         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1066
1067         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1068 }
1069
1070 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1071                                unsigned long pipe, void *buffer, int length,
1072                                int interval)
1073 {
1074         struct dwc2_priv *priv = dev_get_priv(dev);
1075
1076         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1077
1078         return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1079 }
1080
1081 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1082 {
1083         struct dwc2_priv *priv = dev_get_priv(dev);
1084         fdt_addr_t addr;
1085
1086         addr = dev_get_addr(dev);
1087         if (addr == FDT_ADDR_T_NONE)
1088                 return -EINVAL;
1089         priv->regs = (struct dwc2_core_regs *)addr;
1090
1091         return 0;
1092 }
1093
1094 static int dwc2_usb_probe(struct udevice *dev)
1095 {
1096         struct dwc2_priv *priv = dev_get_priv(dev);
1097
1098         return dwc2_init_common(priv);
1099 }
1100
1101 static int dwc2_usb_remove(struct udevice *dev)
1102 {
1103         struct dwc2_priv *priv = dev_get_priv(dev);
1104
1105         dwc2_uninit_common(priv->regs);
1106
1107         return 0;
1108 }
1109
1110 struct dm_usb_ops dwc2_usb_ops = {
1111         .control = dwc2_submit_control_msg,
1112         .bulk = dwc2_submit_bulk_msg,
1113         .interrupt = dwc2_submit_int_msg,
1114 };
1115
1116 static const struct udevice_id dwc2_usb_ids[] = {
1117         { .compatible = "brcm,bcm2835-usb" },
1118         { .compatible = "snps,dwc2" },
1119         { }
1120 };
1121
1122 U_BOOT_DRIVER(usb_dwc2) = {
1123         .name   = "dwc2_usb",
1124         .id     = UCLASS_USB,
1125         .of_match = dwc2_usb_ids,
1126         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1127         .probe  = dwc2_usb_probe,
1128         .remove = dwc2_usb_remove,
1129         .ops    = &dwc2_usb_ops,
1130         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1131         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1132 };
1133 #endif