2 * SAMSUNG EXYNOS USB HOST EHCI Controller
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * Vivek Gautam <gautam.vivek@samsung.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 #include <asm/arch/cpu.h>
29 #include <asm/arch/ehci.h>
30 #include <asm/arch/system.h>
31 #include <asm/arch/power.h>
32 #include <asm-generic/errno.h>
33 #include <linux/compat.h>
36 /* Declare global data pointer */
37 DECLARE_GLOBAL_DATA_PTR;
40 * Contains pointers to register base addresses
41 * for the usb controller.
44 struct exynos_usb_phy *usb;
45 struct ehci_hccr *hcd;
48 static struct exynos_ehci exynos;
50 static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
56 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI);
58 debug("EHCI: Can't get device node for ehci\n");
63 * Get the base address for EHCI controller from the device node
65 addr = fdtdec_get_addr(blob, node, "reg");
66 if (addr == FDT_ADDR_T_NONE) {
67 debug("Can't get the EHCI register address\n");
71 exynos->hcd = (struct ehci_hccr *)addr;
74 node = fdtdec_next_compatible_subnode(blob, node,
75 COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
77 debug("EHCI: Can't get device node for usb-phy controller\n");
82 * Get the base address for usbphy from the device node
84 exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
86 if (exynos->usb == NULL) {
87 debug("Can't get the usbphy register address\n");
94 /* Setup the EHCI host controller. */
95 static void setup_usb_phy(struct exynos_usb_phy *usb)
97 set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
99 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
101 clrbits_le32(&usb->usbphyctrl0,
102 HOST_CTRL0_FSEL_MASK |
103 HOST_CTRL0_COMMONON_N |
104 /* HOST Phy setting */
105 HOST_CTRL0_PHYSWRST |
106 HOST_CTRL0_PHYSWRSTALL |
108 HOST_CTRL0_FORCESUSPEND |
109 HOST_CTRL0_FORCESLEEP);
111 setbits_le32(&usb->usbphyctrl0,
112 /* Setting up the ref freq */
114 /* HOST Phy setting */
115 HOST_CTRL0_LINKSWRST |
116 HOST_CTRL0_UTMISWRST);
118 clrbits_le32(&usb->usbphyctrl0,
119 HOST_CTRL0_LINKSWRST |
120 HOST_CTRL0_UTMISWRST);
123 /* EHCI Ctrl setting */
124 setbits_le32(&usb->ehcictrl,
125 EHCICTRL_ENAINCRXALIGN |
131 /* Reset the EHCI host controller. */
132 static void reset_usb_phy(struct exynos_usb_phy *usb)
135 setbits_le32(&usb->usbphyctrl0,
136 HOST_CTRL0_PHYSWRST |
137 HOST_CTRL0_PHYSWRSTALL |
139 HOST_CTRL0_FORCESUSPEND |
140 HOST_CTRL0_FORCESLEEP);
142 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
146 * EHCI-initialization
147 * Create the appropriate control structures to manage
148 * a new EHCI host controller.
150 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
152 struct exynos_ehci *ctx = &exynos;
154 if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) {
155 debug("Unable to parse device tree for ehci-exynos\n");
159 setup_usb_phy(ctx->usb);
162 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
163 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
165 debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
166 (uint32_t)*hccr, (uint32_t)*hcor,
167 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
173 * Destroy the appropriate control structures corresponding
174 * the EHCI host controller.
176 int ehci_hcd_stop(int index)
178 struct exynos_ehci *ctx = &exynos;
180 reset_usb_phy(ctx->usb);