2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
6 * Author: Tor Krill tor@excito.com
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <usb/ehci-ci.h>
18 #include <fdt_support.h>
22 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
23 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
26 static void set_txfifothresh(struct usb_ehci *, u32);
27 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
28 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
30 /* Check USB PHY clock valid */
31 static int usb_phy_clk_valid(struct usb_ehci *ehci)
33 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
34 in_be32(&ehci->prictrl))) {
35 printf("USB PHY clock invalid!\n");
43 * Create the appropriate control structures to manage
44 * a new EHCI host controller.
46 * Excerpts from linux ehci fsl driver.
48 int ehci_hcd_init(int index, enum usb_init_type init,
49 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
51 struct usb_ehci *ehci = NULL;
55 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
58 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
61 printf("ERROR: wrong controller index!!\n");
65 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
66 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
67 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
69 return ehci_fsl_init(index, ehci, *hccr, *hcor);
73 * Destroy the appropriate control structures corresponding
74 * the the EHCI host controller.
76 int ehci_hcd_stop(int index)
81 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
82 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
84 const char *phy_type = NULL;
86 char current_usb_controller[5];
87 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
92 if (has_erratum_a007075()) {
94 * A 5ms delay is needed after applying soft-reset to the
95 * controller to let external ULPI phy come out of reset.
96 * This delay needs to be added before re-initializing
97 * the controller after soft-resetting completes
101 memset(current_usb_controller, '\0', 5);
102 snprintf(current_usb_controller, sizeof(current_usb_controller),
105 /* Set to Host mode */
106 setbits_le32(&ehci->usbmode, CM_HOST);
108 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
109 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
112 if (hwconfig_sub(current_usb_controller, "phy_type"))
113 phy_type = hwconfig_subarg(current_usb_controller,
116 phy_type = getenv("usb_phy_type");
119 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
120 /* if none specified assume internal UTMI */
121 strcpy(usb_phy, "utmi");
124 printf("WARNING: USB phy type not defined !!\n");
129 if (!strncmp(phy_type, "utmi", 4)) {
130 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
131 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
133 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
135 udelay(1000); /* delay required for PHY Clk to appear */
137 out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
138 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
141 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
143 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
144 CONTROL_REGISTER_W1C_MASK, USB_EN);
145 udelay(1000); /* delay required for PHY Clk to appear */
146 if (!usb_phy_clk_valid(ehci))
148 out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
151 out_be32(&ehci->prictrl, 0x0000000c);
152 out_be32(&ehci->age_cnt_limit, 0x00000040);
153 out_be32(&ehci->sictrl, 0x00000001);
155 in_le32(&ehci->usbmode);
157 if (has_erratum_a007798())
158 set_txfifothresh(ehci, TXFIFOTHRESH);
160 if (has_erratum_a004477()) {
162 * When reset is issued while any ULPI transaction is ongoing
163 * then it may result to corruption of ULPI Function Control
164 * Register which eventually causes phy clock to enter low
165 * power mode which stops the clock. Thus delay is required
166 * before reset to let ongoing ULPI transaction complete.
174 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
175 * to counter DDR latencies in writing data into Tx buffer.
176 * This prevents Tx buffer from getting underrun
178 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
181 cmd = ehci_readl(&ehci->txfilltuning);
182 cmd &= ~TXFIFO_THRESH_MASK;
183 cmd |= TXFIFO_THRESH(txfifo_thresh);
184 ehci_writel(&ehci->txfilltuning, cmd);