2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
6 * Author: Tor Krill tor@excito.com
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <usb/ehci-ci.h>
18 #include <fdt_support.h>
22 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
23 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
26 static void set_txfifothresh(struct usb_ehci *, u32);
28 /* Check USB PHY clock valid */
29 static int usb_phy_clk_valid(struct usb_ehci *ehci)
31 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
32 in_be32(&ehci->prictrl))) {
33 printf("USB PHY clock invalid!\n");
41 * Create the appropriate control structures to manage
42 * a new EHCI host controller.
44 * Excerpts from linux ehci fsl driver.
46 int ehci_hcd_init(int index, enum usb_init_type init,
47 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
49 struct usb_ehci *ehci = NULL;
50 const char *phy_type = NULL;
52 char current_usb_controller[5];
53 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
58 if (has_erratum_a007075()) {
60 * A 5ms delay is needed after applying soft-reset to the
61 * controller to let external ULPI phy come out of reset.
62 * This delay needs to be added before re-initializing
63 * the controller after soft-resetting completes
67 memset(current_usb_controller, '\0', 5);
68 snprintf(current_usb_controller, sizeof(current_usb_controller),
73 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
76 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
79 printf("ERROR: wrong controller index!!\n");
83 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
84 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
85 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
87 /* Set to Host mode */
88 setbits_le32(&ehci->usbmode, CM_HOST);
90 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
91 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
94 if (hwconfig_sub(current_usb_controller, "phy_type"))
95 phy_type = hwconfig_subarg(current_usb_controller,
98 phy_type = getenv("usb_phy_type");
101 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
102 /* if none specified assume internal UTMI */
103 strcpy(usb_phy, "utmi");
106 printf("WARNING: USB phy type not defined !!\n");
111 if (!strncmp(phy_type, "utmi", 4)) {
112 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
113 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
115 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
117 udelay(1000); /* delay required for PHY Clk to appear */
119 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
120 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
123 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
125 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
126 CONTROL_REGISTER_W1C_MASK, USB_EN);
127 udelay(1000); /* delay required for PHY Clk to appear */
128 if (!usb_phy_clk_valid(ehci))
130 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
133 out_be32(&ehci->prictrl, 0x0000000c);
134 out_be32(&ehci->age_cnt_limit, 0x00000040);
135 out_be32(&ehci->sictrl, 0x00000001);
137 in_le32(&ehci->usbmode);
139 if (has_erratum_a007798())
140 set_txfifothresh(ehci, TXFIFOTHRESH);
142 if (has_erratum_a004477()) {
144 * When reset is issued while any ULPI transaction is ongoing
145 * then it may result to corruption of ULPI Function Control
146 * Register which eventually causes phy clock to enter low
147 * power mode which stops the clock. Thus delay is required
148 * before reset to let ongoing ULPI transaction complete.
156 * Destroy the appropriate control structures corresponding
157 * the the EHCI host controller.
159 int ehci_hcd_stop(int index)
165 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
166 * to counter DDR latencies in writing data into Tx buffer.
167 * This prevents Tx buffer from getting underrun
169 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
172 cmd = ehci_readl(&ehci->txfilltuning);
173 cmd &= ~TXFIFO_THRESH_MASK;
174 cmd |= TXFIFO_THRESH(txfifo_thresh);
175 ehci_writel(&ehci->txfilltuning, cmd);