2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/byteorder.h>
25 #include <asm/unaligned.h>
33 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
34 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
37 static struct ehci_ctrl {
38 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
39 struct ehci_hcor *hcor;
42 struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN)));
43 } ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
45 #define ALIGN_END_ADDR(type, ptr, size) \
46 ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
48 static struct descriptor {
49 struct usb_hub_descriptor hub;
50 struct usb_device_descriptor device;
51 struct usb_linux_config_descriptor config;
52 struct usb_linux_interface_descriptor interface;
53 struct usb_endpoint_descriptor endpoint;
54 } __attribute__ ((packed)) descriptor = {
56 0x8, /* bDescLength */
57 0x29, /* bDescriptorType: hub descriptor */
58 2, /* bNrPorts -- runtime modified */
59 0, /* wHubCharacteristics */
60 10, /* bPwrOn2PwrGood */
61 0, /* bHubCntrCurrent */
62 {}, /* Device removable */
63 {} /* at most 7 ports! XXX */
67 1, /* bDescriptorType: UDESC_DEVICE */
68 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
69 9, /* bDeviceClass: UDCLASS_HUB */
70 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
71 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
72 64, /* bMaxPacketSize: 64 bytes */
73 0x0000, /* idVendor */
74 0x0000, /* idProduct */
75 cpu_to_le16(0x0100), /* bcdDevice */
76 1, /* iManufacturer */
78 0, /* iSerialNumber */
79 1 /* bNumConfigurations: 1 */
83 2, /* bDescriptorType: UDESC_CONFIG */
85 1, /* bNumInterface */
86 1, /* bConfigurationValue */
87 0, /* iConfiguration */
88 0x40, /* bmAttributes: UC_SELF_POWER */
93 4, /* bDescriptorType: UDESC_INTERFACE */
94 0, /* bInterfaceNumber */
95 0, /* bAlternateSetting */
96 1, /* bNumEndpoints */
97 9, /* bInterfaceClass: UICLASS_HUB */
98 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
99 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
104 5, /* bDescriptorType: UDESC_ENDPOINT */
105 0x81, /* bEndpointAddress:
106 * UE_DIR_IN | EHCI_INTR_ENDPT
108 3, /* bmAttributes: UE_INTERRUPT */
109 8, /* wMaxPacketSize */
114 #if defined(CONFIG_EHCI_IS_TDI)
115 #define ehci_is_TDI() (1)
117 #define ehci_is_TDI() (0)
120 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
125 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
126 __attribute__((weak, alias("__ehci_powerup_fixup")));
128 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
132 result = ehci_readl(ptr);
134 if (result == ~(uint32_t)0)
144 static int ehci_reset(int index)
151 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
152 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
153 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
154 ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd,
155 CMD_RESET, 0, 250 * 1000);
157 printf("EHCI fail to reset\n");
162 reg_ptr = (uint32_t *)((u8 *)ehcic[index].hcor + USBMODE);
163 tmp = ehci_readl(reg_ptr);
164 tmp |= USBMODE_CM_HC;
165 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
168 ehci_writel(reg_ptr, tmp);
171 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
172 cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
173 cmd &= ~TXFIFO_THRESH_MASK;
174 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
175 ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd);
181 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
183 uint32_t delta, next;
184 uint32_t addr = (uint32_t)buf;
187 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
188 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
190 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
193 while (idx < QT_BUFFER_CNT) {
194 td->qt_buffer[idx] = cpu_to_hc32(addr);
195 td->qt_buffer_hi[idx] = 0;
196 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
205 if (idx == QT_BUFFER_CNT) {
206 printf("out of buffer pointers (%u bytes left)\n", sz);
213 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
215 #define QH_HIGH_SPEED 2
216 #define QH_FULL_SPEED 0
217 #define QH_LOW_SPEED 1
218 if (speed == USB_SPEED_HIGH)
219 return QH_HIGH_SPEED;
220 if (speed == USB_SPEED_LOW)
222 return QH_FULL_SPEED;
226 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
227 int length, struct devrequest *req)
229 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
233 volatile struct qTD *vtd;
236 uint32_t endpt, maxpacket, token, usbsts;
241 struct ehci_ctrl *ctrl = dev->controller;
243 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
244 buffer, length, req);
246 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
247 req->request, req->request,
248 req->requesttype, req->requesttype,
249 le16_to_cpu(req->value), le16_to_cpu(req->value),
250 le16_to_cpu(req->index));
252 #define PKT_ALIGN 512
254 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
255 * described by a transfer descriptor (the qTD). The qTDs form a linked
256 * list with a queue head (QH).
258 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
259 * have its beginning in a qTD transfer and its end in the following
260 * one, so the qTD transfer lengths have to be chosen accordingly.
262 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
263 * single pages. The first data buffer can start at any offset within a
264 * page (not considering the cache-line alignment issues), while the
265 * following buffers must be page-aligned. There is no alignment
266 * constraint on the size of a qTD transfer.
269 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
271 if (length > 0 || req == NULL) {
273 * Determine the qTD transfer size that will be used for the
274 * data payload (not considering the first qTD transfer, which
275 * may be longer or shorter, and the final one, which may be
278 * In order to keep each packet within a qTD transfer, the qTD
279 * transfer size is aligned to PKT_ALIGN, which is a multiple of
280 * wMaxPacketSize (except in some cases for interrupt transfers,
281 * see comment in submit_int_msg()).
283 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
284 * QT_BUFFER_CNT full pages will be used.
286 int xfr_sz = QT_BUFFER_CNT;
288 * However, if the input buffer is not aligned to PKT_ALIGN, the
289 * qTD transfer size will be one page shorter, and the first qTD
290 * data buffer of each transfer will be page-unaligned.
292 if ((uint32_t)buffer & (PKT_ALIGN - 1))
294 /* Convert the qTD transfer size to bytes. */
295 xfr_sz *= EHCI_PAGE_SIZE;
297 * Approximate by excess the number of qTDs that will be
298 * required for the data payload. The exact formula is way more
299 * complicated and saves at most 2 qTDs, i.e. a total of 128
302 qtd_count += 2 + length / xfr_sz;
305 * Threshold value based on the worst-case total size of the allocated qTDs for
306 * a mass-storage transfer of 65535 blocks of 512 bytes.
308 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
309 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
311 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
313 printf("unable to allocate TDs\n");
317 memset(qh, 0, sizeof(struct QH));
318 memset(qtd, 0, qtd_count * sizeof(*qtd));
320 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
323 * Setup QH (3.6 in ehci-r10.pdf)
325 * qh_link ................. 03-00 H
326 * qh_endpt1 ............... 07-04 H
327 * qh_endpt2 ............... 0B-08 H
329 * qh_overlay.qt_next ...... 13-10 H
330 * - qh_overlay.qt_altnext
332 qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH);
333 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
334 maxpacket = usb_maxpacket(dev, pipe);
335 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
336 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
337 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
338 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
339 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
340 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
341 qh->qh_endpt1 = cpu_to_hc32(endpt);
342 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
343 QH_ENDPT2_HUBADDR(dev->parent->devnum) |
344 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
345 qh->qh_endpt2 = cpu_to_hc32(endpt);
346 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
348 tdp = &qh->qh_overlay.qt_next;
352 * Setup request qTD (3.5 in ehci-r10.pdf)
354 * qt_next ................ 03-00 H
355 * qt_altnext ............. 07-04 H
356 * qt_token ............... 0B-08 H
358 * [ buffer, buffer_hi ] loaded with "req".
360 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
361 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
362 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
363 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
364 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
365 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
366 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
367 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
368 printf("unable to construct SETUP TD\n");
371 /* Update previous qTD! */
372 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
373 tdp = &qtd[qtd_counter++].qt_next;
377 if (length > 0 || req == NULL) {
378 uint8_t *buf_ptr = buffer;
379 int left_length = length;
383 * Determine the size of this qTD transfer. By default,
384 * QT_BUFFER_CNT full pages can be used.
386 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
388 * However, if the input buffer is not page-aligned, the
389 * portion of the first page before the buffer start
390 * offset within that page is unusable.
392 xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
394 * In order to keep each packet within a qTD transfer,
395 * align the qTD transfer size to PKT_ALIGN.
397 xfr_bytes &= ~(PKT_ALIGN - 1);
399 * This transfer may be shorter than the available qTD
400 * transfer size that has just been computed.
402 xfr_bytes = min(xfr_bytes, left_length);
405 * Setup request qTD (3.5 in ehci-r10.pdf)
407 * qt_next ................ 03-00 H
408 * qt_altnext ............. 07-04 H
409 * qt_token ............... 0B-08 H
411 * [ buffer, buffer_hi ] loaded with "buffer".
413 qtd[qtd_counter].qt_next =
414 cpu_to_hc32(QT_NEXT_TERMINATE);
415 qtd[qtd_counter].qt_altnext =
416 cpu_to_hc32(QT_NEXT_TERMINATE);
417 token = QT_TOKEN_DT(toggle) |
418 QT_TOKEN_TOTALBYTES(xfr_bytes) |
419 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
421 QT_TOKEN_PID(usb_pipein(pipe) ?
422 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
423 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
424 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
425 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
427 printf("unable to construct DATA TD\n");
430 /* Update previous qTD! */
431 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
432 tdp = &qtd[qtd_counter++].qt_next;
434 * Data toggle has to be adjusted since the qTD transfer
435 * size is not always an even multiple of
438 if ((xfr_bytes / maxpacket) & 1)
440 buf_ptr += xfr_bytes;
441 left_length -= xfr_bytes;
442 } while (left_length > 0);
447 * Setup request qTD (3.5 in ehci-r10.pdf)
449 * qt_next ................ 03-00 H
450 * qt_altnext ............. 07-04 H
451 * qt_token ............... 0B-08 H
453 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
454 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
455 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
456 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
457 QT_TOKEN_PID(usb_pipein(pipe) ?
458 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
459 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
460 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
461 /* Update previous qTD! */
462 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
463 tdp = &qtd[qtd_counter++].qt_next;
466 ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
469 flush_dcache_range((uint32_t)&ctrl->qh_list,
470 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
471 flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
472 flush_dcache_range((uint32_t)qtd,
473 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
475 /* Set async. queue head pointer. */
476 ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list);
478 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
479 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
481 /* Enable async. schedule. */
482 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
484 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
486 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
489 printf("EHCI fail timeout STS_ASS set\n");
493 /* Wait for TDs to be processed. */
495 vtd = &qtd[qtd_counter - 1];
496 timeout = USB_TIMEOUT_MS(pipe);
498 /* Invalidate dcache */
499 invalidate_dcache_range((uint32_t)&ctrl->qh_list,
500 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
501 invalidate_dcache_range((uint32_t)qh,
502 ALIGN_END_ADDR(struct QH, qh, 1));
503 invalidate_dcache_range((uint32_t)qtd,
504 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
506 token = hc32_to_cpu(vtd->qt_token);
507 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
510 } while (get_timer(ts) < timeout);
513 * Invalidate the memory area occupied by buffer
514 * Don't try to fix the buffer alignment, if it isn't properly
515 * aligned it's upper layer's fault so let invalidate_dcache_range()
516 * vow about it. But we have to fix the length as it's actual
517 * transfer length and can be unaligned. This is potentially
518 * dangerous operation, it's responsibility of the calling
519 * code to make sure enough space is reserved.
521 invalidate_dcache_range((uint32_t)buffer,
522 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
524 /* Check that the TD processing happened */
525 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
526 printf("EHCI timed out on TD - token=%#x\n", token);
528 /* Disable async schedule. */
529 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
531 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
533 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
536 printf("EHCI fail timeout STS_ASS reset\n");
540 token = hc32_to_cpu(qh->qh_overlay.qt_token);
541 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
542 debug("TOKEN=%#x\n", token);
543 switch (QT_TOKEN_GET_STATUS(token) &
544 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
546 toggle = QT_TOKEN_GET_DT(token);
547 usb_settoggle(dev, usb_pipeendpoint(pipe),
548 usb_pipeout(pipe), toggle);
551 case QT_TOKEN_STATUS_HALTED:
552 dev->status = USB_ST_STALLED;
554 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
555 case QT_TOKEN_STATUS_DATBUFERR:
556 dev->status = USB_ST_BUF_ERR;
558 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
559 case QT_TOKEN_STATUS_BABBLEDET:
560 dev->status = USB_ST_BABBLE_DET;
563 dev->status = USB_ST_CRC_ERR;
564 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
565 dev->status |= USB_ST_STALLED;
568 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
571 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
572 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
573 ehci_readl(&ctrl->hcor->or_portsc[0]),
574 ehci_readl(&ctrl->hcor->or_portsc[1]));
578 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
585 static inline int min3(int a, int b, int c)
596 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
597 int length, struct devrequest *req)
604 uint32_t *status_reg;
605 struct ehci_ctrl *ctrl = dev->controller;
607 if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
608 printf("The request port(%d) is not configured\n",
609 le16_to_cpu(req->index) - 1);
612 status_reg = (uint32_t *)&ctrl->hcor->or_portsc[
613 le16_to_cpu(req->index) - 1];
616 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
617 req->request, req->request,
618 req->requesttype, req->requesttype,
619 le16_to_cpu(req->value), le16_to_cpu(req->index));
621 typeReq = req->request | req->requesttype << 8;
624 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
625 switch (le16_to_cpu(req->value) >> 8) {
627 debug("USB_DT_DEVICE request\n");
628 srcptr = &descriptor.device;
629 srclen = descriptor.device.bLength;
632 debug("USB_DT_CONFIG config\n");
633 srcptr = &descriptor.config;
634 srclen = descriptor.config.bLength +
635 descriptor.interface.bLength +
636 descriptor.endpoint.bLength;
639 debug("USB_DT_STRING config\n");
640 switch (le16_to_cpu(req->value) & 0xff) {
641 case 0: /* Language */
646 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
649 case 2: /* Product */
650 srcptr = "\52\3E\0H\0C\0I\0 "
652 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
656 debug("unknown value DT_STRING %x\n",
657 le16_to_cpu(req->value));
662 debug("unknown value %x\n", le16_to_cpu(req->value));
666 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
667 switch (le16_to_cpu(req->value) >> 8) {
669 debug("USB_DT_HUB config\n");
670 srcptr = &descriptor.hub;
671 srclen = descriptor.hub.bLength;
674 debug("unknown value %x\n", le16_to_cpu(req->value));
678 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
679 debug("USB_REQ_SET_ADDRESS\n");
680 ctrl->rootdev = le16_to_cpu(req->value);
682 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
683 debug("USB_REQ_SET_CONFIGURATION\n");
686 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
687 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
692 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
693 memset(tmpbuf, 0, 4);
694 reg = ehci_readl(status_reg);
695 if (reg & EHCI_PS_CS)
696 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
697 if (reg & EHCI_PS_PE)
698 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
699 if (reg & EHCI_PS_SUSP)
700 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
701 if (reg & EHCI_PS_OCA)
702 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
703 if (reg & EHCI_PS_PR)
704 tmpbuf[0] |= USB_PORT_STAT_RESET;
705 if (reg & EHCI_PS_PP)
706 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
709 switch (PORTSC_PSPD(reg)) {
713 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
717 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
721 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
724 if (reg & EHCI_PS_CSC)
725 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
726 if (reg & EHCI_PS_PEC)
727 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
728 if (reg & EHCI_PS_OCC)
729 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
730 if (ctrl->portreset & (1 << le16_to_cpu(req->index)))
731 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
736 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
737 reg = ehci_readl(status_reg);
738 reg &= ~EHCI_PS_CLEAR;
739 switch (le16_to_cpu(req->value)) {
740 case USB_PORT_FEAT_ENABLE:
742 ehci_writel(status_reg, reg);
744 case USB_PORT_FEAT_POWER:
745 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
747 ehci_writel(status_reg, reg);
750 case USB_PORT_FEAT_RESET:
751 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
753 EHCI_PS_IS_LOWSPEED(reg)) {
754 /* Low speed device, give up ownership. */
755 debug("port %d low speed --> companion\n",
758 ehci_writel(status_reg, reg);
765 ehci_writel(status_reg, reg);
767 * caller must wait, then call GetPortStatus
768 * usb 2.0 specification say 50 ms resets on
771 ehci_powerup_fixup(status_reg, ®);
773 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
775 * A host controller must terminate the reset
776 * and stabilize the state of the port within
779 ret = handshake(status_reg, EHCI_PS_PR, 0,
783 1 << le16_to_cpu(req->index);
785 printf("port(%d) reset error\n",
786 le16_to_cpu(req->index) - 1);
790 debug("unknown feature %x\n", le16_to_cpu(req->value));
793 /* unblock posted writes */
794 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
796 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
797 reg = ehci_readl(status_reg);
798 switch (le16_to_cpu(req->value)) {
799 case USB_PORT_FEAT_ENABLE:
802 case USB_PORT_FEAT_C_ENABLE:
803 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
805 case USB_PORT_FEAT_POWER:
806 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
807 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
808 case USB_PORT_FEAT_C_CONNECTION:
809 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
811 case USB_PORT_FEAT_OVER_CURRENT:
812 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
814 case USB_PORT_FEAT_C_RESET:
815 ctrl->portreset &= ~(1 << le16_to_cpu(req->index));
818 debug("unknown feature %x\n", le16_to_cpu(req->value));
821 ehci_writel(status_reg, reg);
822 /* unblock posted write */
823 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
826 debug("Unknown request\n");
831 len = min3(srclen, le16_to_cpu(req->length), length);
832 if (srcptr != NULL && len > 0)
833 memcpy(buffer, srcptr, len);
842 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
843 req->requesttype, req->request, le16_to_cpu(req->value),
844 le16_to_cpu(req->index), le16_to_cpu(req->length));
847 dev->status = USB_ST_STALLED;
851 int usb_lowlevel_stop(int index)
853 return ehci_hcd_stop(index);
856 int usb_lowlevel_init(int index, void **controller)
862 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
865 /* EHCI spec section 4.1 */
866 if (ehci_reset(index))
869 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
870 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
874 qh_list = &ehcic[index].qh_list;
876 /* Set head of reclaim list */
877 memset(qh_list, 0, sizeof(*qh_list));
878 qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
879 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
880 QH_ENDPT1_EPS(USB_SPEED_HIGH));
881 qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
882 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
883 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
884 qh_list->qh_overlay.qt_token =
885 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
887 reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
888 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
889 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
890 /* Port Indicators */
891 if (HCS_INDICATOR(reg))
892 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
893 | 0x80, &descriptor.hub.wHubCharacteristics);
894 /* Port Power Control */
896 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
897 | 0x01, &descriptor.hub.wHubCharacteristics);
899 /* Start the host controller. */
900 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
902 * Philips, Intel, and maybe others need CMD_RUN before the
903 * root hub will detect new devices (why?); NEC doesn't
905 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
907 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
909 /* take control over the ports */
910 cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
912 ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
913 /* unblock posted write */
914 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
916 reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
917 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
919 ehcic[index].rootdev = 0;
921 *controller = &ehcic[index];
926 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
930 if (usb_pipetype(pipe) != PIPE_BULK) {
931 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
934 return ehci_submit_async(dev, pipe, buffer, length, NULL);
938 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
939 int length, struct devrequest *setup)
941 struct ehci_ctrl *ctrl = dev->controller;
943 if (usb_pipetype(pipe) != PIPE_CONTROL) {
944 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
948 if (usb_pipedevice(pipe) == ctrl->rootdev) {
950 dev->speed = USB_SPEED_HIGH;
951 return ehci_submit_root(dev, pipe, buffer, length, setup);
953 return ehci_submit_async(dev, pipe, buffer, length, setup);
957 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
958 int length, int interval)
960 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
961 dev, pipe, buffer, length, interval);
964 * Interrupt transfers requiring several transactions are not supported
965 * because bInterval is ignored.
967 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
968 * <= PKT_ALIGN if several qTDs are required, while the USB
969 * specification does not constrain this for interrupt transfers. That
970 * means that ehci_submit_async() would support interrupt transfers
971 * requiring several transactions only as long as the transfer size does
972 * not require more than a single qTD.
974 if (length > usb_maxpacket(dev, pipe)) {
975 printf("%s: Interrupt transfers requiring several transactions "
976 "are not supported.\n", __func__);
979 return ehci_submit_async(dev, pipe, buffer, length, NULL);