2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/byteorder.h>
27 #include <asm/unaligned.h>
32 #include <linux/compiler.h>
36 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
37 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
41 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
42 * Let's time out after 8 to have a little safety margin on top of that.
44 #define HCHALT_TIMEOUT (8 * 1000)
47 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
50 #define ALIGN_END_ADDR(type, ptr, size) \
51 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
53 static struct descriptor {
54 struct usb_hub_descriptor hub;
55 struct usb_device_descriptor device;
56 struct usb_linux_config_descriptor config;
57 struct usb_linux_interface_descriptor interface;
58 struct usb_endpoint_descriptor endpoint;
59 } __attribute__ ((packed)) descriptor = {
61 0x8, /* bDescLength */
62 0x29, /* bDescriptorType: hub descriptor */
63 2, /* bNrPorts -- runtime modified */
64 0, /* wHubCharacteristics */
65 10, /* bPwrOn2PwrGood */
66 0, /* bHubCntrCurrent */
67 {}, /* Device removable */
68 {} /* at most 7 ports! XXX */
72 1, /* bDescriptorType: UDESC_DEVICE */
73 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
74 9, /* bDeviceClass: UDCLASS_HUB */
75 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
76 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
77 64, /* bMaxPacketSize: 64 bytes */
78 0x0000, /* idVendor */
79 0x0000, /* idProduct */
80 cpu_to_le16(0x0100), /* bcdDevice */
81 1, /* iManufacturer */
83 0, /* iSerialNumber */
84 1 /* bNumConfigurations: 1 */
88 2, /* bDescriptorType: UDESC_CONFIG */
90 1, /* bNumInterface */
91 1, /* bConfigurationValue */
92 0, /* iConfiguration */
93 0x40, /* bmAttributes: UC_SELF_POWER */
98 4, /* bDescriptorType: UDESC_INTERFACE */
99 0, /* bInterfaceNumber */
100 0, /* bAlternateSetting */
101 1, /* bNumEndpoints */
102 9, /* bInterfaceClass: UICLASS_HUB */
103 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
104 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
109 5, /* bDescriptorType: UDESC_ENDPOINT */
110 0x81, /* bEndpointAddress:
111 * UE_DIR_IN | EHCI_INTR_ENDPT
113 3, /* bmAttributes: UE_INTERRUPT */
114 8, /* wMaxPacketSize */
119 #if defined(CONFIG_EHCI_IS_TDI)
120 #define ehci_is_TDI() (1)
122 #define ehci_is_TDI() (0)
125 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
128 return dev_get_priv(usb_get_bus(udev->dev));
130 return udev->controller;
134 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
136 return PORTSC_PSPD(reg);
139 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
144 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
145 tmp = ehci_readl(reg_ptr);
146 tmp |= USBMODE_CM_HC;
147 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
150 ehci_writel(reg_ptr, tmp);
153 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
159 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
161 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
162 /* Printing the message would cause a scan failure! */
163 debug("The request port(%u) is not configured\n", port);
167 return (uint32_t *)&ctrl->hcor->or_portsc[port];
170 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
174 result = ehci_readl(ptr);
176 if (result == ~(uint32_t)0)
186 static int ehci_reset(struct ehci_ctrl *ctrl)
191 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
192 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
193 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
194 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
195 CMD_RESET, 0, 250 * 1000);
197 printf("EHCI fail to reset\n");
202 ctrl->ops.set_usb_mode(ctrl);
204 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
205 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
206 cmd &= ~TXFIFO_THRESH_MASK;
207 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
208 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
214 static int ehci_shutdown(struct ehci_ctrl *ctrl)
219 if (!ctrl || !ctrl->hcor)
222 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
223 cmd &= ~(CMD_PSE | CMD_ASE);
224 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
225 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
229 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
230 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
232 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
236 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
237 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
242 puts("EHCI failed to shut down host controller.\n");
247 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
249 uint32_t delta, next;
250 uint32_t addr = (unsigned long)buf;
253 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
254 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
256 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
259 while (idx < QT_BUFFER_CNT) {
260 td->qt_buffer[idx] = cpu_to_hc32(addr);
261 td->qt_buffer_hi[idx] = 0;
262 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
271 if (idx == QT_BUFFER_CNT) {
272 printf("out of buffer pointers (%zu bytes left)\n", sz);
279 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
281 #define QH_HIGH_SPEED 2
282 #define QH_FULL_SPEED 0
283 #define QH_LOW_SPEED 1
284 if (speed == USB_SPEED_HIGH)
285 return QH_HIGH_SPEED;
286 if (speed == USB_SPEED_LOW)
288 return QH_FULL_SPEED;
291 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
294 struct usb_device *ttdev;
297 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
301 * For full / low speed devices we need to get the devnum and portnr of
302 * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs
303 * in the tree before that one!
307 * When called from usb-uclass.c: usb_scan_device() udev->dev points
308 * to the parent udevice, not the actual udevice belonging to the
309 * udev as the device is not instantiated yet. So when searching
310 * for the first usb-2 parent start with udev->dev not
311 * udev->dev->parent .
313 struct udevice *parent;
314 struct usb_device *uparent;
318 uparent = dev_get_parentdata(parent);
320 while (uparent->speed != USB_SPEED_HIGH) {
321 struct udevice *dev = parent;
323 if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
324 printf("ehci: Error cannot find high speed parent of usb-1 device\n");
328 ttdev = dev_get_parentdata(dev);
329 parent = dev->parent;
330 uparent = dev_get_parentdata(parent);
332 parent_devnum = uparent->devnum;
335 while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH)
336 ttdev = ttdev->parent;
339 parent_devnum = ttdev->parent->devnum;
342 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) |
343 QH_ENDPT2_HUBADDR(parent_devnum));
347 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
348 int length, struct devrequest *req)
350 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
354 volatile struct qTD *vtd;
357 uint32_t endpt, maxpacket, token, usbsts;
362 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
364 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
365 buffer, length, req);
367 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
368 req->request, req->request,
369 req->requesttype, req->requesttype,
370 le16_to_cpu(req->value), le16_to_cpu(req->value),
371 le16_to_cpu(req->index));
373 #define PKT_ALIGN 512
375 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
376 * described by a transfer descriptor (the qTD). The qTDs form a linked
377 * list with a queue head (QH).
379 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
380 * have its beginning in a qTD transfer and its end in the following
381 * one, so the qTD transfer lengths have to be chosen accordingly.
383 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
384 * single pages. The first data buffer can start at any offset within a
385 * page (not considering the cache-line alignment issues), while the
386 * following buffers must be page-aligned. There is no alignment
387 * constraint on the size of a qTD transfer.
390 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
392 if (length > 0 || req == NULL) {
394 * Determine the qTD transfer size that will be used for the
395 * data payload (not considering the first qTD transfer, which
396 * may be longer or shorter, and the final one, which may be
399 * In order to keep each packet within a qTD transfer, the qTD
400 * transfer size is aligned to PKT_ALIGN, which is a multiple of
401 * wMaxPacketSize (except in some cases for interrupt transfers,
402 * see comment in submit_int_msg()).
404 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
405 * QT_BUFFER_CNT full pages will be used.
407 int xfr_sz = QT_BUFFER_CNT;
409 * However, if the input buffer is not aligned to PKT_ALIGN, the
410 * qTD transfer size will be one page shorter, and the first qTD
411 * data buffer of each transfer will be page-unaligned.
413 if ((unsigned long)buffer & (PKT_ALIGN - 1))
415 /* Convert the qTD transfer size to bytes. */
416 xfr_sz *= EHCI_PAGE_SIZE;
418 * Approximate by excess the number of qTDs that will be
419 * required for the data payload. The exact formula is way more
420 * complicated and saves at most 2 qTDs, i.e. a total of 128
423 qtd_count += 2 + length / xfr_sz;
426 * Threshold value based on the worst-case total size of the allocated qTDs for
427 * a mass-storage transfer of 65535 blocks of 512 bytes.
429 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
430 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
432 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
434 printf("unable to allocate TDs\n");
438 memset(qh, 0, sizeof(struct QH));
439 memset(qtd, 0, qtd_count * sizeof(*qtd));
441 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
444 * Setup QH (3.6 in ehci-r10.pdf)
446 * qh_link ................. 03-00 H
447 * qh_endpt1 ............... 07-04 H
448 * qh_endpt2 ............... 0B-08 H
450 * qh_overlay.qt_next ...... 13-10 H
451 * - qh_overlay.qt_altnext
453 qh->qh_link = cpu_to_hc32((unsigned long)&ctrl->qh_list | QH_LINK_TYPE_QH);
454 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
455 maxpacket = usb_maxpacket(dev, pipe);
456 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
457 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
458 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
459 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
460 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
461 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
462 qh->qh_endpt1 = cpu_to_hc32(endpt);
463 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
464 qh->qh_endpt2 = cpu_to_hc32(endpt);
465 ehci_update_endpt2_dev_n_port(dev, qh);
466 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
467 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
469 tdp = &qh->qh_overlay.qt_next;
473 * Setup request qTD (3.5 in ehci-r10.pdf)
475 * qt_next ................ 03-00 H
476 * qt_altnext ............. 07-04 H
477 * qt_token ............... 0B-08 H
479 * [ buffer, buffer_hi ] loaded with "req".
481 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
482 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
483 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
484 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
485 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
486 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
487 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
488 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
489 printf("unable to construct SETUP TD\n");
492 /* Update previous qTD! */
493 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
494 tdp = &qtd[qtd_counter++].qt_next;
498 if (length > 0 || req == NULL) {
499 uint8_t *buf_ptr = buffer;
500 int left_length = length;
504 * Determine the size of this qTD transfer. By default,
505 * QT_BUFFER_CNT full pages can be used.
507 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
509 * However, if the input buffer is not page-aligned, the
510 * portion of the first page before the buffer start
511 * offset within that page is unusable.
513 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
515 * In order to keep each packet within a qTD transfer,
516 * align the qTD transfer size to PKT_ALIGN.
518 xfr_bytes &= ~(PKT_ALIGN - 1);
520 * This transfer may be shorter than the available qTD
521 * transfer size that has just been computed.
523 xfr_bytes = min(xfr_bytes, left_length);
526 * Setup request qTD (3.5 in ehci-r10.pdf)
528 * qt_next ................ 03-00 H
529 * qt_altnext ............. 07-04 H
530 * qt_token ............... 0B-08 H
532 * [ buffer, buffer_hi ] loaded with "buffer".
534 qtd[qtd_counter].qt_next =
535 cpu_to_hc32(QT_NEXT_TERMINATE);
536 qtd[qtd_counter].qt_altnext =
537 cpu_to_hc32(QT_NEXT_TERMINATE);
538 token = QT_TOKEN_DT(toggle) |
539 QT_TOKEN_TOTALBYTES(xfr_bytes) |
540 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
542 QT_TOKEN_PID(usb_pipein(pipe) ?
543 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
544 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
545 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
546 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
548 printf("unable to construct DATA TD\n");
551 /* Update previous qTD! */
552 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
553 tdp = &qtd[qtd_counter++].qt_next;
555 * Data toggle has to be adjusted since the qTD transfer
556 * size is not always an even multiple of
559 if ((xfr_bytes / maxpacket) & 1)
561 buf_ptr += xfr_bytes;
562 left_length -= xfr_bytes;
563 } while (left_length > 0);
568 * Setup request qTD (3.5 in ehci-r10.pdf)
570 * qt_next ................ 03-00 H
571 * qt_altnext ............. 07-04 H
572 * qt_token ............... 0B-08 H
574 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
575 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
576 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
577 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
578 QT_TOKEN_PID(usb_pipein(pipe) ?
579 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
580 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
581 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
582 /* Update previous qTD! */
583 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
584 tdp = &qtd[qtd_counter++].qt_next;
587 ctrl->qh_list.qh_link = cpu_to_hc32((unsigned long)qh | QH_LINK_TYPE_QH);
590 flush_dcache_range((unsigned long)&ctrl->qh_list,
591 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
592 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
593 flush_dcache_range((unsigned long)qtd,
594 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
596 /* Set async. queue head pointer. */
597 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)&ctrl->qh_list);
599 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
600 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
602 /* Enable async. schedule. */
603 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
605 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
607 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
610 printf("EHCI fail timeout STS_ASS set\n");
614 /* Wait for TDs to be processed. */
616 vtd = &qtd[qtd_counter - 1];
617 timeout = USB_TIMEOUT_MS(pipe);
619 /* Invalidate dcache */
620 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
621 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
622 invalidate_dcache_range((unsigned long)qh,
623 ALIGN_END_ADDR(struct QH, qh, 1));
624 invalidate_dcache_range((unsigned long)qtd,
625 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
627 token = hc32_to_cpu(vtd->qt_token);
628 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
631 } while (get_timer(ts) < timeout);
634 * Invalidate the memory area occupied by buffer
635 * Don't try to fix the buffer alignment, if it isn't properly
636 * aligned it's upper layer's fault so let invalidate_dcache_range()
637 * vow about it. But we have to fix the length as it's actual
638 * transfer length and can be unaligned. This is potentially
639 * dangerous operation, it's responsibility of the calling
640 * code to make sure enough space is reserved.
642 invalidate_dcache_range((unsigned long)buffer,
643 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
645 /* Check that the TD processing happened */
646 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
647 printf("EHCI timed out on TD - token=%#x\n", token);
649 /* Disable async schedule. */
650 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
652 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
654 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
657 printf("EHCI fail timeout STS_ASS reset\n");
661 token = hc32_to_cpu(qh->qh_overlay.qt_token);
662 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
663 debug("TOKEN=%#x\n", token);
664 switch (QT_TOKEN_GET_STATUS(token) &
665 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
667 toggle = QT_TOKEN_GET_DT(token);
668 usb_settoggle(dev, usb_pipeendpoint(pipe),
669 usb_pipeout(pipe), toggle);
672 case QT_TOKEN_STATUS_HALTED:
673 dev->status = USB_ST_STALLED;
675 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
676 case QT_TOKEN_STATUS_DATBUFERR:
677 dev->status = USB_ST_BUF_ERR;
679 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
680 case QT_TOKEN_STATUS_BABBLEDET:
681 dev->status = USB_ST_BABBLE_DET;
684 dev->status = USB_ST_CRC_ERR;
685 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
686 dev->status |= USB_ST_STALLED;
689 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
692 #ifndef CONFIG_USB_EHCI_FARADAY
693 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
694 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
695 ehci_readl(&ctrl->hcor->or_portsc[0]),
696 ehci_readl(&ctrl->hcor->or_portsc[1]));
701 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
708 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
709 void *buffer, int length, struct devrequest *req)
716 uint32_t *status_reg;
717 int port = le16_to_cpu(req->index) & 0xff;
718 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
722 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
723 req->request, req->request,
724 req->requesttype, req->requesttype,
725 le16_to_cpu(req->value), le16_to_cpu(req->index));
727 typeReq = req->request | req->requesttype << 8;
730 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
731 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
732 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
733 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
743 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
744 switch (le16_to_cpu(req->value) >> 8) {
746 debug("USB_DT_DEVICE request\n");
747 srcptr = &descriptor.device;
748 srclen = descriptor.device.bLength;
751 debug("USB_DT_CONFIG config\n");
752 srcptr = &descriptor.config;
753 srclen = descriptor.config.bLength +
754 descriptor.interface.bLength +
755 descriptor.endpoint.bLength;
758 debug("USB_DT_STRING config\n");
759 switch (le16_to_cpu(req->value) & 0xff) {
760 case 0: /* Language */
765 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
768 case 2: /* Product */
769 srcptr = "\52\3E\0H\0C\0I\0 "
771 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
775 debug("unknown value DT_STRING %x\n",
776 le16_to_cpu(req->value));
781 debug("unknown value %x\n", le16_to_cpu(req->value));
785 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
786 switch (le16_to_cpu(req->value) >> 8) {
788 debug("USB_DT_HUB config\n");
789 srcptr = &descriptor.hub;
790 srclen = descriptor.hub.bLength;
793 debug("unknown value %x\n", le16_to_cpu(req->value));
797 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
798 debug("USB_REQ_SET_ADDRESS\n");
799 ctrl->rootdev = le16_to_cpu(req->value);
801 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
802 debug("USB_REQ_SET_CONFIGURATION\n");
805 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
806 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
811 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
812 memset(tmpbuf, 0, 4);
813 reg = ehci_readl(status_reg);
814 if (reg & EHCI_PS_CS)
815 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
816 if (reg & EHCI_PS_PE)
817 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
818 if (reg & EHCI_PS_SUSP)
819 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
820 if (reg & EHCI_PS_OCA)
821 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
822 if (reg & EHCI_PS_PR)
823 tmpbuf[0] |= USB_PORT_STAT_RESET;
824 if (reg & EHCI_PS_PP)
825 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
828 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
832 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
836 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
840 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
843 if (reg & EHCI_PS_CSC)
844 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
845 if (reg & EHCI_PS_PEC)
846 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
847 if (reg & EHCI_PS_OCC)
848 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
849 if (ctrl->portreset & (1 << port))
850 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
855 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
856 reg = ehci_readl(status_reg);
857 reg &= ~EHCI_PS_CLEAR;
858 switch (le16_to_cpu(req->value)) {
859 case USB_PORT_FEAT_ENABLE:
861 ehci_writel(status_reg, reg);
863 case USB_PORT_FEAT_POWER:
864 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
866 ehci_writel(status_reg, reg);
869 case USB_PORT_FEAT_RESET:
870 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
872 EHCI_PS_IS_LOWSPEED(reg)) {
873 /* Low speed device, give up ownership. */
874 debug("port %d low speed --> companion\n",
877 ehci_writel(status_reg, reg);
884 ehci_writel(status_reg, reg);
886 * caller must wait, then call GetPortStatus
887 * usb 2.0 specification say 50 ms resets on
890 ctrl->ops.powerup_fixup(ctrl, status_reg, ®);
892 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
894 * A host controller must terminate the reset
895 * and stabilize the state of the port within
898 ret = handshake(status_reg, EHCI_PS_PR, 0,
901 reg = ehci_readl(status_reg);
902 if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
903 == EHCI_PS_CS && !ehci_is_TDI()) {
904 debug("port %d full speed --> companion\n", port - 1);
905 reg &= ~EHCI_PS_CLEAR;
907 ehci_writel(status_reg, reg);
910 ctrl->portreset |= 1 << port;
913 printf("port(%d) reset error\n",
918 case USB_PORT_FEAT_TEST:
921 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
922 ehci_writel(status_reg, reg);
925 debug("unknown feature %x\n", le16_to_cpu(req->value));
928 /* unblock posted writes */
929 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
931 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
932 reg = ehci_readl(status_reg);
933 reg &= ~EHCI_PS_CLEAR;
934 switch (le16_to_cpu(req->value)) {
935 case USB_PORT_FEAT_ENABLE:
938 case USB_PORT_FEAT_C_ENABLE:
941 case USB_PORT_FEAT_POWER:
942 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
945 case USB_PORT_FEAT_C_CONNECTION:
948 case USB_PORT_FEAT_OVER_CURRENT:
951 case USB_PORT_FEAT_C_RESET:
952 ctrl->portreset &= ~(1 << port);
955 debug("unknown feature %x\n", le16_to_cpu(req->value));
958 ehci_writel(status_reg, reg);
959 /* unblock posted write */
960 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
963 debug("Unknown request\n");
968 len = min3(srclen, (int)le16_to_cpu(req->length), length);
969 if (srcptr != NULL && len > 0)
970 memcpy(buffer, srcptr, len);
979 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
980 req->requesttype, req->request, le16_to_cpu(req->value),
981 le16_to_cpu(req->index), le16_to_cpu(req->length));
984 dev->status = USB_ST_STALLED;
988 const struct ehci_ops default_ehci_ops = {
989 .set_usb_mode = ehci_set_usbmode,
990 .get_port_speed = ehci_get_port_speed,
991 .powerup_fixup = ehci_powerup_fixup,
992 .get_portsc_register = ehci_get_portsc_register,
995 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
998 ctrl->ops = default_ehci_ops;
1001 if (!ctrl->ops.set_usb_mode)
1002 ctrl->ops.set_usb_mode = ehci_set_usbmode;
1003 if (!ctrl->ops.get_port_speed)
1004 ctrl->ops.get_port_speed = ehci_get_port_speed;
1005 if (!ctrl->ops.powerup_fixup)
1006 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
1007 if (!ctrl->ops.get_portsc_register)
1008 ctrl->ops.get_portsc_register =
1009 ehci_get_portsc_register;
1013 #ifndef CONFIG_DM_USB
1014 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
1016 struct ehci_ctrl *ctrl = &ehcic[index];
1019 ehci_setup_ops(ctrl, ops);
1022 void *ehci_get_controller_priv(int index)
1024 return ehcic[index].priv;
1028 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
1031 struct QH *periodic;
1036 /* Set the high address word (aka segment) for 64-bit controller */
1037 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1038 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1040 qh_list = &ctrl->qh_list;
1042 /* Set head of reclaim list */
1043 memset(qh_list, 0, sizeof(*qh_list));
1044 qh_list->qh_link = cpu_to_hc32((unsigned long)qh_list | QH_LINK_TYPE_QH);
1045 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1046 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1047 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1048 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1049 qh_list->qh_overlay.qt_token =
1050 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1052 flush_dcache_range((unsigned long)qh_list,
1053 ALIGN_END_ADDR(struct QH, qh_list, 1));
1055 /* Set async. queue head pointer. */
1056 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)qh_list);
1059 * Set up periodic list
1060 * Step 1: Parent QH for all periodic transfers.
1062 ctrl->periodic_schedules = 0;
1063 periodic = &ctrl->periodic_queue;
1064 memset(periodic, 0, sizeof(*periodic));
1065 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1066 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1067 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1069 flush_dcache_range((unsigned long)periodic,
1070 ALIGN_END_ADDR(struct QH, periodic, 1));
1073 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1074 * In particular, device specifications on polling frequency
1075 * are disregarded. Keyboards seem to send NAK/NYet reliably
1076 * when polled with an empty buffer.
1078 * Split Transactions will be spread across microframes using
1079 * S-mask and C-mask.
1081 if (ctrl->periodic_list == NULL)
1082 ctrl->periodic_list = memalign(4096, 1024 * 4);
1084 if (!ctrl->periodic_list)
1086 for (i = 0; i < 1024; i++) {
1087 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1091 flush_dcache_range((unsigned long)ctrl->periodic_list,
1092 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1095 /* Set periodic list base address */
1096 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1097 (unsigned long)ctrl->periodic_list);
1099 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1100 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1101 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1102 /* Port Indicators */
1103 if (HCS_INDICATOR(reg))
1104 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1105 | 0x80, &descriptor.hub.wHubCharacteristics);
1106 /* Port Power Control */
1108 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1109 | 0x01, &descriptor.hub.wHubCharacteristics);
1111 /* Start the host controller. */
1112 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1114 * Philips, Intel, and maybe others need CMD_RUN before the
1115 * root hub will detect new devices (why?); NEC doesn't
1117 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1119 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1121 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1122 /* take control over the ports */
1123 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1125 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1128 /* unblock posted write */
1129 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1131 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1132 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1137 #ifndef CONFIG_DM_USB
1138 int usb_lowlevel_stop(int index)
1140 ehci_shutdown(&ehcic[index]);
1141 return ehci_hcd_stop(index);
1144 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1146 struct ehci_ctrl *ctrl = &ehcic[index];
1151 * Set ops to default_ehci_ops, ehci_hcd_init should call
1152 * ehci_set_controller_priv to change any of these function pointers.
1154 ctrl->ops = default_ehci_ops;
1156 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1159 if (init == USB_INIT_DEVICE)
1162 /* EHCI spec section 4.1 */
1163 if (ehci_reset(ctrl))
1166 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1167 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1171 #ifdef CONFIG_USB_EHCI_FARADAY
1172 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1174 rc = ehci_common_init(ctrl, tweaks);
1180 *controller = &ehcic[index];
1185 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1186 void *buffer, int length)
1189 if (usb_pipetype(pipe) != PIPE_BULK) {
1190 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1193 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1196 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1197 void *buffer, int length,
1198 struct devrequest *setup)
1200 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1202 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1203 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1207 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1209 dev->speed = USB_SPEED_HIGH;
1210 return ehci_submit_root(dev, pipe, buffer, length, setup);
1212 return ehci_submit_async(dev, pipe, buffer, length, setup);
1224 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1227 enable_periodic(struct ehci_ctrl *ctrl)
1230 struct ehci_hcor *hcor = ctrl->hcor;
1233 cmd = ehci_readl(&hcor->or_usbcmd);
1235 ehci_writel(&hcor->or_usbcmd, cmd);
1237 ret = handshake((uint32_t *)&hcor->or_usbsts,
1238 STS_PSS, STS_PSS, 100 * 1000);
1240 printf("EHCI failed: timeout when enabling periodic list\n");
1248 disable_periodic(struct ehci_ctrl *ctrl)
1251 struct ehci_hcor *hcor = ctrl->hcor;
1254 cmd = ehci_readl(&hcor->or_usbcmd);
1256 ehci_writel(&hcor->or_usbcmd, cmd);
1258 ret = handshake((uint32_t *)&hcor->or_usbsts,
1259 STS_PSS, 0, 100 * 1000);
1261 printf("EHCI failed: timeout when disabling periodic list\n");
1267 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1268 unsigned long pipe, int queuesize, int elementsize,
1269 void *buffer, int interval)
1271 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1272 struct int_queue *result = NULL;
1276 * Interrupt transfers requiring several transactions are not supported
1277 * because bInterval is ignored.
1279 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1280 * <= PKT_ALIGN if several qTDs are required, while the USB
1281 * specification does not constrain this for interrupt transfers. That
1282 * means that ehci_submit_async() would support interrupt transfers
1283 * requiring several transactions only as long as the transfer size does
1284 * not require more than a single qTD.
1286 if (elementsize > usb_maxpacket(dev, pipe)) {
1287 printf("%s: xfers requiring several transactions are not supported.\n",
1292 debug("Enter create_int_queue\n");
1293 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1294 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1298 /* limit to 4 full pages worth of data -
1299 * we can safely fit them in a single TD,
1300 * no matter the alignment
1302 if (elementsize >= 16384) {
1303 debug("too large elements for interrupt transfers\n");
1307 result = malloc(sizeof(*result));
1309 debug("ehci intr queue: out of memory\n");
1312 result->elementsize = elementsize;
1313 result->pipe = pipe;
1314 result->first = memalign(USB_DMA_MINALIGN,
1315 sizeof(struct QH) * queuesize);
1316 if (!result->first) {
1317 debug("ehci intr queue: out of memory\n");
1320 result->current = result->first;
1321 result->last = result->first + queuesize - 1;
1322 result->tds = memalign(USB_DMA_MINALIGN,
1323 sizeof(struct qTD) * queuesize);
1325 debug("ehci intr queue: out of memory\n");
1328 memset(result->first, 0, sizeof(struct QH) * queuesize);
1329 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1331 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1333 for (i = 0; i < queuesize; i++) {
1334 struct QH *qh = result->first + i;
1335 struct qTD *td = result->tds + i;
1336 void **buf = &qh->buffer;
1338 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1339 if (i == queuesize - 1)
1340 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1342 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1343 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1345 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1346 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1348 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1349 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1350 (usb_pipedevice(pipe) << 0));
1351 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1352 (1 << 0)); /* S-mask: microframe 0 */
1353 if (dev->speed == USB_SPEED_LOW ||
1354 dev->speed == USB_SPEED_FULL) {
1355 /* C-mask: microframes 2-4 */
1356 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1358 ehci_update_endpt2_dev_n_port(dev, qh);
1360 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1361 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1362 debug("communication direction is '%s'\n",
1363 usb_pipein(pipe) ? "in" : "out");
1364 td->qt_token = cpu_to_hc32(
1365 QT_TOKEN_DT(toggle) |
1366 (elementsize << 16) |
1367 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1370 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1372 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1374 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1376 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1378 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1380 *buf = buffer + i * elementsize;
1384 flush_dcache_range((unsigned long)buffer,
1385 ALIGN_END_ADDR(char, buffer,
1386 queuesize * elementsize));
1387 flush_dcache_range((unsigned long)result->first,
1388 ALIGN_END_ADDR(struct QH, result->first,
1390 flush_dcache_range((unsigned long)result->tds,
1391 ALIGN_END_ADDR(struct qTD, result->tds,
1394 if (ctrl->periodic_schedules > 0) {
1395 if (disable_periodic(ctrl) < 0) {
1396 debug("FATAL: periodic should never fail, but did");
1401 /* hook up to periodic list */
1402 struct QH *list = &ctrl->periodic_queue;
1403 result->last->qh_link = list->qh_link;
1404 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1406 flush_dcache_range((unsigned long)result->last,
1407 ALIGN_END_ADDR(struct QH, result->last, 1));
1408 flush_dcache_range((unsigned long)list,
1409 ALIGN_END_ADDR(struct QH, list, 1));
1411 if (enable_periodic(ctrl) < 0) {
1412 debug("FATAL: periodic should never fail, but did");
1415 ctrl->periodic_schedules++;
1417 debug("Exit create_int_queue\n");
1424 free(result->first);
1431 static void *_ehci_poll_int_queue(struct usb_device *dev,
1432 struct int_queue *queue)
1434 struct QH *cur = queue->current;
1436 uint32_t token, toggle;
1437 unsigned long pipe = queue->pipe;
1439 /* depleted queue */
1441 debug("Exit poll_int_queue with completed queue\n");
1445 cur_td = &queue->tds[queue->current - queue->first];
1446 invalidate_dcache_range((unsigned long)cur_td,
1447 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1448 token = hc32_to_cpu(cur_td->qt_token);
1449 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1450 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1454 toggle = QT_TOKEN_GET_DT(token);
1455 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1457 if (!(cur->qh_link & QH_LINK_TERMINATE))
1460 queue->current = NULL;
1462 invalidate_dcache_range((unsigned long)cur->buffer,
1463 ALIGN_END_ADDR(char, cur->buffer,
1464 queue->elementsize));
1466 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1467 token, cur, queue->first);
1471 /* Do not free buffers associated with QHs, they're owned by someone else */
1472 static int _ehci_destroy_int_queue(struct usb_device *dev,
1473 struct int_queue *queue)
1475 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1477 unsigned long timeout;
1479 if (disable_periodic(ctrl) < 0) {
1480 debug("FATAL: periodic should never fail, but did");
1483 ctrl->periodic_schedules--;
1485 struct QH *cur = &ctrl->periodic_queue;
1486 timeout = get_timer(0) + 500; /* abort after 500ms */
1487 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1488 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1489 if (NEXT_QH(cur) == queue->first) {
1490 debug("found candidate. removing from chain\n");
1491 cur->qh_link = queue->last->qh_link;
1492 flush_dcache_range((unsigned long)cur,
1493 ALIGN_END_ADDR(struct QH, cur, 1));
1498 if (get_timer(0) > timeout) {
1499 printf("Timeout destroying interrupt endpoint queue\n");
1505 if (ctrl->periodic_schedules > 0) {
1506 result = enable_periodic(ctrl);
1508 debug("FATAL: periodic should never fail, but did");
1519 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1520 void *buffer, int length, int interval)
1523 struct int_queue *queue;
1524 unsigned long timeout;
1525 int result = 0, ret;
1527 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1528 dev, pipe, buffer, length, interval);
1530 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1534 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1535 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1536 if (get_timer(0) > timeout) {
1537 printf("Timeout poll on interrupt endpoint\n");
1538 result = -ETIMEDOUT;
1542 if (backbuffer != buffer) {
1543 debug("got wrong buffer back (%p instead of %p)\n",
1544 backbuffer, buffer);
1548 ret = _ehci_destroy_int_queue(dev, queue);
1552 /* everything worked out fine */
1556 #ifndef CONFIG_DM_USB
1557 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1558 void *buffer, int length)
1560 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1563 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1564 int length, struct devrequest *setup)
1566 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1569 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1570 void *buffer, int length, int interval)
1572 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
1575 struct int_queue *create_int_queue(struct usb_device *dev,
1576 unsigned long pipe, int queuesize, int elementsize,
1577 void *buffer, int interval)
1579 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1583 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1585 return _ehci_poll_int_queue(dev, queue);
1588 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1590 return _ehci_destroy_int_queue(dev, queue);
1594 #ifdef CONFIG_DM_USB
1595 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1596 unsigned long pipe, void *buffer, int length,
1597 struct devrequest *setup)
1599 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1600 dev->name, udev, udev->dev->name, udev->portnr);
1602 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1605 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1606 unsigned long pipe, void *buffer, int length)
1608 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1609 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1612 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1613 unsigned long pipe, void *buffer, int length,
1616 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1617 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
1620 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1621 struct usb_device *udev, unsigned long pipe, int queuesize,
1622 int elementsize, void *buffer, int interval)
1624 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1625 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1629 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1630 struct int_queue *queue)
1632 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1633 return _ehci_poll_int_queue(udev, queue);
1636 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1637 struct int_queue *queue)
1639 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1640 return _ehci_destroy_int_queue(udev, queue);
1643 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1644 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1645 uint tweaks, enum usb_init_type init)
1647 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1648 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1651 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1652 dev->name, ctrl, hccr, hcor, init);
1654 priv->desc_before_addr = true;
1656 ehci_setup_ops(ctrl, ops);
1661 if (init == USB_INIT_DEVICE)
1663 ret = ehci_reset(ctrl);
1667 ret = ehci_common_init(ctrl, tweaks);
1674 debug("%s: failed, ret=%d\n", __func__, ret);
1678 int ehci_deregister(struct udevice *dev)
1680 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1682 ehci_shutdown(ctrl);
1687 struct dm_usb_ops ehci_usb_ops = {
1688 .control = ehci_submit_control_msg,
1689 .bulk = ehci_submit_bulk_msg,
1690 .interrupt = ehci_submit_int_msg,
1691 .create_int_queue = ehci_create_int_queue,
1692 .poll_int_queue = ehci_poll_int_queue,
1693 .destroy_int_queue = ehci_destroy_int_queue,