2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/byteorder.h>
25 #include <asm/unaligned.h>
33 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
34 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
37 static struct ehci_ctrl {
38 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
39 struct ehci_hcor *hcor;
42 struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN)));
43 } ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
45 #define ALIGN_END_ADDR(type, ptr, size) \
46 ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
48 static struct descriptor {
49 struct usb_hub_descriptor hub;
50 struct usb_device_descriptor device;
51 struct usb_linux_config_descriptor config;
52 struct usb_linux_interface_descriptor interface;
53 struct usb_endpoint_descriptor endpoint;
54 } __attribute__ ((packed)) descriptor = {
56 0x8, /* bDescLength */
57 0x29, /* bDescriptorType: hub descriptor */
58 2, /* bNrPorts -- runtime modified */
59 0, /* wHubCharacteristics */
60 10, /* bPwrOn2PwrGood */
61 0, /* bHubCntrCurrent */
62 {}, /* Device removable */
63 {} /* at most 7 ports! XXX */
67 1, /* bDescriptorType: UDESC_DEVICE */
68 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
69 9, /* bDeviceClass: UDCLASS_HUB */
70 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
71 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
72 64, /* bMaxPacketSize: 64 bytes */
73 0x0000, /* idVendor */
74 0x0000, /* idProduct */
75 cpu_to_le16(0x0100), /* bcdDevice */
76 1, /* iManufacturer */
78 0, /* iSerialNumber */
79 1 /* bNumConfigurations: 1 */
83 2, /* bDescriptorType: UDESC_CONFIG */
85 1, /* bNumInterface */
86 1, /* bConfigurationValue */
87 0, /* iConfiguration */
88 0x40, /* bmAttributes: UC_SELF_POWER */
93 4, /* bDescriptorType: UDESC_INTERFACE */
94 0, /* bInterfaceNumber */
95 0, /* bAlternateSetting */
96 1, /* bNumEndpoints */
97 9, /* bInterfaceClass: UICLASS_HUB */
98 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
99 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
104 5, /* bDescriptorType: UDESC_ENDPOINT */
105 0x81, /* bEndpointAddress:
106 * UE_DIR_IN | EHCI_INTR_ENDPT
108 3, /* bmAttributes: UE_INTERRUPT */
109 8, /* wMaxPacketSize */
114 #if defined(CONFIG_EHCI_IS_TDI)
115 #define ehci_is_TDI() (1)
117 #define ehci_is_TDI() (0)
120 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
125 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
126 __attribute__((weak, alias("__ehci_powerup_fixup")));
128 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
132 result = ehci_readl(ptr);
134 if (result == ~(uint32_t)0)
144 static int ehci_reset(int index)
151 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
152 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
153 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
154 ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd,
155 CMD_RESET, 0, 250 * 1000);
157 printf("EHCI fail to reset\n");
162 reg_ptr = (uint32_t *)((u8 *)ehcic[index].hcor + USBMODE);
163 tmp = ehci_readl(reg_ptr);
164 tmp |= USBMODE_CM_HC;
165 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
168 ehci_writel(reg_ptr, tmp);
171 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
172 cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
173 cmd &= ~TXFIFO_THRESH_MASK;
174 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
175 ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd);
181 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
183 uint32_t delta, next;
184 uint32_t addr = (uint32_t)buf;
187 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
188 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
190 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
193 while (idx < QT_BUFFER_CNT) {
194 td->qt_buffer[idx] = cpu_to_hc32(addr);
195 td->qt_buffer_hi[idx] = 0;
196 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
205 if (idx == QT_BUFFER_CNT) {
206 printf("out of buffer pointers (%u bytes left)\n", sz);
214 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
215 int length, struct devrequest *req)
217 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
221 volatile struct qTD *vtd;
224 uint32_t endpt, maxpacket, token, usbsts;
229 struct ehci_ctrl *ctrl = dev->controller;
231 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
232 buffer, length, req);
234 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
235 req->request, req->request,
236 req->requesttype, req->requesttype,
237 le16_to_cpu(req->value), le16_to_cpu(req->value),
238 le16_to_cpu(req->index));
240 #define PKT_ALIGN 512
242 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
243 * described by a transfer descriptor (the qTD). The qTDs form a linked
244 * list with a queue head (QH).
246 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
247 * have its beginning in a qTD transfer and its end in the following
248 * one, so the qTD transfer lengths have to be chosen accordingly.
250 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
251 * single pages. The first data buffer can start at any offset within a
252 * page (not considering the cache-line alignment issues), while the
253 * following buffers must be page-aligned. There is no alignment
254 * constraint on the size of a qTD transfer.
257 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
259 if (length > 0 || req == NULL) {
261 * Determine the qTD transfer size that will be used for the
262 * data payload (not considering the first qTD transfer, which
263 * may be longer or shorter, and the final one, which may be
266 * In order to keep each packet within a qTD transfer, the qTD
267 * transfer size is aligned to PKT_ALIGN, which is a multiple of
268 * wMaxPacketSize (except in some cases for interrupt transfers,
269 * see comment in submit_int_msg()).
271 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
272 * QT_BUFFER_CNT full pages will be used.
274 int xfr_sz = QT_BUFFER_CNT;
276 * However, if the input buffer is not aligned to PKT_ALIGN, the
277 * qTD transfer size will be one page shorter, and the first qTD
278 * data buffer of each transfer will be page-unaligned.
280 if ((uint32_t)buffer & (PKT_ALIGN - 1))
282 /* Convert the qTD transfer size to bytes. */
283 xfr_sz *= EHCI_PAGE_SIZE;
285 * Approximate by excess the number of qTDs that will be
286 * required for the data payload. The exact formula is way more
287 * complicated and saves at most 2 qTDs, i.e. a total of 128
290 qtd_count += 2 + length / xfr_sz;
293 * Threshold value based on the worst-case total size of the allocated qTDs for
294 * a mass-storage transfer of 65535 blocks of 512 bytes.
296 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
297 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
299 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
301 printf("unable to allocate TDs\n");
305 memset(qh, 0, sizeof(struct QH));
306 memset(qtd, 0, qtd_count * sizeof(*qtd));
308 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
311 * Setup QH (3.6 in ehci-r10.pdf)
313 * qh_link ................. 03-00 H
314 * qh_endpt1 ............... 07-04 H
315 * qh_endpt2 ............... 0B-08 H
317 * qh_overlay.qt_next ...... 13-10 H
318 * - qh_overlay.qt_altnext
320 qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH);
321 c = usb_pipespeed(pipe) != USB_SPEED_HIGH && !usb_pipeendpoint(pipe);
322 maxpacket = usb_maxpacket(dev, pipe);
323 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
324 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
325 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
326 QH_ENDPT1_EPS(usb_pipespeed(pipe)) |
327 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
328 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
329 qh->qh_endpt1 = cpu_to_hc32(endpt);
330 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
331 QH_ENDPT2_HUBADDR(dev->parent->devnum) |
332 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
333 qh->qh_endpt2 = cpu_to_hc32(endpt);
334 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
336 tdp = &qh->qh_overlay.qt_next;
340 * Setup request qTD (3.5 in ehci-r10.pdf)
342 * qt_next ................ 03-00 H
343 * qt_altnext ............. 07-04 H
344 * qt_token ............... 0B-08 H
346 * [ buffer, buffer_hi ] loaded with "req".
348 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
349 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
350 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
351 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
352 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
353 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
354 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
355 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
356 printf("unable to construct SETUP TD\n");
359 /* Update previous qTD! */
360 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
361 tdp = &qtd[qtd_counter++].qt_next;
365 if (length > 0 || req == NULL) {
366 uint8_t *buf_ptr = buffer;
367 int left_length = length;
371 * Determine the size of this qTD transfer. By default,
372 * QT_BUFFER_CNT full pages can be used.
374 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
376 * However, if the input buffer is not page-aligned, the
377 * portion of the first page before the buffer start
378 * offset within that page is unusable.
380 xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
382 * In order to keep each packet within a qTD transfer,
383 * align the qTD transfer size to PKT_ALIGN.
385 xfr_bytes &= ~(PKT_ALIGN - 1);
387 * This transfer may be shorter than the available qTD
388 * transfer size that has just been computed.
390 xfr_bytes = min(xfr_bytes, left_length);
393 * Setup request qTD (3.5 in ehci-r10.pdf)
395 * qt_next ................ 03-00 H
396 * qt_altnext ............. 07-04 H
397 * qt_token ............... 0B-08 H
399 * [ buffer, buffer_hi ] loaded with "buffer".
401 qtd[qtd_counter].qt_next =
402 cpu_to_hc32(QT_NEXT_TERMINATE);
403 qtd[qtd_counter].qt_altnext =
404 cpu_to_hc32(QT_NEXT_TERMINATE);
405 token = QT_TOKEN_DT(toggle) |
406 QT_TOKEN_TOTALBYTES(xfr_bytes) |
407 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
409 QT_TOKEN_PID(usb_pipein(pipe) ?
410 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
411 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
412 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
413 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
415 printf("unable to construct DATA TD\n");
418 /* Update previous qTD! */
419 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
420 tdp = &qtd[qtd_counter++].qt_next;
422 * Data toggle has to be adjusted since the qTD transfer
423 * size is not always an even multiple of
426 if ((xfr_bytes / maxpacket) & 1)
428 buf_ptr += xfr_bytes;
429 left_length -= xfr_bytes;
430 } while (left_length > 0);
435 * Setup request qTD (3.5 in ehci-r10.pdf)
437 * qt_next ................ 03-00 H
438 * qt_altnext ............. 07-04 H
439 * qt_token ............... 0B-08 H
441 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
442 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
443 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
444 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
445 QT_TOKEN_PID(usb_pipein(pipe) ?
446 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
447 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
448 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
449 /* Update previous qTD! */
450 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
451 tdp = &qtd[qtd_counter++].qt_next;
454 ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
457 flush_dcache_range((uint32_t)&ctrl->qh_list,
458 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
459 flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
460 flush_dcache_range((uint32_t)qtd,
461 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
463 /* Set async. queue head pointer. */
464 ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list);
466 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
467 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
469 /* Enable async. schedule. */
470 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
472 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
474 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
477 printf("EHCI fail timeout STS_ASS set\n");
481 /* Wait for TDs to be processed. */
483 vtd = &qtd[qtd_counter - 1];
484 timeout = USB_TIMEOUT_MS(pipe);
486 /* Invalidate dcache */
487 invalidate_dcache_range((uint32_t)&ctrl->qh_list,
488 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
489 invalidate_dcache_range((uint32_t)qh,
490 ALIGN_END_ADDR(struct QH, qh, 1));
491 invalidate_dcache_range((uint32_t)qtd,
492 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
494 token = hc32_to_cpu(vtd->qt_token);
495 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
498 } while (get_timer(ts) < timeout);
501 * Invalidate the memory area occupied by buffer
502 * Don't try to fix the buffer alignment, if it isn't properly
503 * aligned it's upper layer's fault so let invalidate_dcache_range()
504 * vow about it. But we have to fix the length as it's actual
505 * transfer length and can be unaligned. This is potentially
506 * dangerous operation, it's responsibility of the calling
507 * code to make sure enough space is reserved.
509 invalidate_dcache_range((uint32_t)buffer,
510 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
512 /* Check that the TD processing happened */
513 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
514 printf("EHCI timed out on TD - token=%#x\n", token);
516 /* Disable async schedule. */
517 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
519 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
521 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
524 printf("EHCI fail timeout STS_ASS reset\n");
528 token = hc32_to_cpu(qh->qh_overlay.qt_token);
529 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
530 debug("TOKEN=%#x\n", token);
531 switch (QT_TOKEN_GET_STATUS(token) &
532 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
534 toggle = QT_TOKEN_GET_DT(token);
535 usb_settoggle(dev, usb_pipeendpoint(pipe),
536 usb_pipeout(pipe), toggle);
539 case QT_TOKEN_STATUS_HALTED:
540 dev->status = USB_ST_STALLED;
542 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
543 case QT_TOKEN_STATUS_DATBUFERR:
544 dev->status = USB_ST_BUF_ERR;
546 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
547 case QT_TOKEN_STATUS_BABBLEDET:
548 dev->status = USB_ST_BABBLE_DET;
551 dev->status = USB_ST_CRC_ERR;
552 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
553 dev->status |= USB_ST_STALLED;
556 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
559 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
560 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
561 ehci_readl(&ctrl->hcor->or_portsc[0]),
562 ehci_readl(&ctrl->hcor->or_portsc[1]));
566 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
573 static inline int min3(int a, int b, int c)
584 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
585 int length, struct devrequest *req)
592 uint32_t *status_reg;
593 struct ehci_ctrl *ctrl = dev->controller;
595 if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
596 printf("The request port(%d) is not configured\n",
597 le16_to_cpu(req->index) - 1);
600 status_reg = (uint32_t *)&ctrl->hcor->or_portsc[
601 le16_to_cpu(req->index) - 1];
604 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
605 req->request, req->request,
606 req->requesttype, req->requesttype,
607 le16_to_cpu(req->value), le16_to_cpu(req->index));
609 typeReq = req->request | req->requesttype << 8;
612 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
613 switch (le16_to_cpu(req->value) >> 8) {
615 debug("USB_DT_DEVICE request\n");
616 srcptr = &descriptor.device;
617 srclen = descriptor.device.bLength;
620 debug("USB_DT_CONFIG config\n");
621 srcptr = &descriptor.config;
622 srclen = descriptor.config.bLength +
623 descriptor.interface.bLength +
624 descriptor.endpoint.bLength;
627 debug("USB_DT_STRING config\n");
628 switch (le16_to_cpu(req->value) & 0xff) {
629 case 0: /* Language */
634 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
637 case 2: /* Product */
638 srcptr = "\52\3E\0H\0C\0I\0 "
640 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
644 debug("unknown value DT_STRING %x\n",
645 le16_to_cpu(req->value));
650 debug("unknown value %x\n", le16_to_cpu(req->value));
654 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
655 switch (le16_to_cpu(req->value) >> 8) {
657 debug("USB_DT_HUB config\n");
658 srcptr = &descriptor.hub;
659 srclen = descriptor.hub.bLength;
662 debug("unknown value %x\n", le16_to_cpu(req->value));
666 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
667 debug("USB_REQ_SET_ADDRESS\n");
668 ctrl->rootdev = le16_to_cpu(req->value);
670 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
671 debug("USB_REQ_SET_CONFIGURATION\n");
674 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
675 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
680 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
681 memset(tmpbuf, 0, 4);
682 reg = ehci_readl(status_reg);
683 if (reg & EHCI_PS_CS)
684 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
685 if (reg & EHCI_PS_PE)
686 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
687 if (reg & EHCI_PS_SUSP)
688 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
689 if (reg & EHCI_PS_OCA)
690 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
691 if (reg & EHCI_PS_PR)
692 tmpbuf[0] |= USB_PORT_STAT_RESET;
693 if (reg & EHCI_PS_PP)
694 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
697 switch (PORTSC_PSPD(reg)) {
701 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
705 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
709 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
712 if (reg & EHCI_PS_CSC)
713 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
714 if (reg & EHCI_PS_PEC)
715 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
716 if (reg & EHCI_PS_OCC)
717 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
718 if (ctrl->portreset & (1 << le16_to_cpu(req->index)))
719 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
724 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
725 reg = ehci_readl(status_reg);
726 reg &= ~EHCI_PS_CLEAR;
727 switch (le16_to_cpu(req->value)) {
728 case USB_PORT_FEAT_ENABLE:
730 ehci_writel(status_reg, reg);
732 case USB_PORT_FEAT_POWER:
733 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
735 ehci_writel(status_reg, reg);
738 case USB_PORT_FEAT_RESET:
739 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
741 EHCI_PS_IS_LOWSPEED(reg)) {
742 /* Low speed device, give up ownership. */
743 debug("port %d low speed --> companion\n",
746 ehci_writel(status_reg, reg);
753 ehci_writel(status_reg, reg);
755 * caller must wait, then call GetPortStatus
756 * usb 2.0 specification say 50 ms resets on
759 ehci_powerup_fixup(status_reg, ®);
761 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
763 * A host controller must terminate the reset
764 * and stabilize the state of the port within
767 ret = handshake(status_reg, EHCI_PS_PR, 0,
771 1 << le16_to_cpu(req->index);
773 printf("port(%d) reset error\n",
774 le16_to_cpu(req->index) - 1);
778 debug("unknown feature %x\n", le16_to_cpu(req->value));
781 /* unblock posted writes */
782 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
784 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
785 reg = ehci_readl(status_reg);
786 switch (le16_to_cpu(req->value)) {
787 case USB_PORT_FEAT_ENABLE:
790 case USB_PORT_FEAT_C_ENABLE:
791 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
793 case USB_PORT_FEAT_POWER:
794 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
795 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
796 case USB_PORT_FEAT_C_CONNECTION:
797 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
799 case USB_PORT_FEAT_OVER_CURRENT:
800 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
802 case USB_PORT_FEAT_C_RESET:
803 ctrl->portreset &= ~(1 << le16_to_cpu(req->index));
806 debug("unknown feature %x\n", le16_to_cpu(req->value));
809 ehci_writel(status_reg, reg);
810 /* unblock posted write */
811 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
814 debug("Unknown request\n");
819 len = min3(srclen, le16_to_cpu(req->length), length);
820 if (srcptr != NULL && len > 0)
821 memcpy(buffer, srcptr, len);
830 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
831 req->requesttype, req->request, le16_to_cpu(req->value),
832 le16_to_cpu(req->index), le16_to_cpu(req->length));
835 dev->status = USB_ST_STALLED;
839 int usb_lowlevel_stop(int index)
841 return ehci_hcd_stop(index);
844 int usb_lowlevel_init(int index, void **controller)
850 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
853 /* EHCI spec section 4.1 */
854 if (ehci_reset(index))
857 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
858 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
862 qh_list = &ehcic[index].qh_list;
864 /* Set head of reclaim list */
865 memset(qh_list, 0, sizeof(*qh_list));
866 qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
867 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
868 QH_ENDPT1_EPS(USB_SPEED_HIGH));
869 qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
870 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
871 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
872 qh_list->qh_overlay.qt_token =
873 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
875 reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
876 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
877 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
878 /* Port Indicators */
879 if (HCS_INDICATOR(reg))
880 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
881 | 0x80, &descriptor.hub.wHubCharacteristics);
882 /* Port Power Control */
884 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
885 | 0x01, &descriptor.hub.wHubCharacteristics);
887 /* Start the host controller. */
888 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
890 * Philips, Intel, and maybe others need CMD_RUN before the
891 * root hub will detect new devices (why?); NEC doesn't
893 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
895 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
897 /* take control over the ports */
898 cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
900 ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
901 /* unblock posted write */
902 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
904 reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
905 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
907 ehcic[index].rootdev = 0;
909 *controller = &ehcic[index];
914 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
918 if (usb_pipetype(pipe) != PIPE_BULK) {
919 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
922 return ehci_submit_async(dev, pipe, buffer, length, NULL);
926 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
927 int length, struct devrequest *setup)
929 struct ehci_ctrl *ctrl = dev->controller;
931 if (usb_pipetype(pipe) != PIPE_CONTROL) {
932 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
936 if (usb_pipedevice(pipe) == ctrl->rootdev) {
938 dev->speed = USB_SPEED_HIGH;
939 return ehci_submit_root(dev, pipe, buffer, length, setup);
941 return ehci_submit_async(dev, pipe, buffer, length, setup);
945 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
946 int length, int interval)
948 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
949 dev, pipe, buffer, length, interval);
952 * Interrupt transfers requiring several transactions are not supported
953 * because bInterval is ignored.
955 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
956 * <= PKT_ALIGN if several qTDs are required, while the USB
957 * specification does not constrain this for interrupt transfers. That
958 * means that ehci_submit_async() would support interrupt transfers
959 * requiring several transactions only as long as the transfer size does
960 * not require more than a single qTD.
962 if (length > usb_maxpacket(dev, pipe)) {
963 printf("%s: Interrupt transfers requiring several transactions "
964 "are not supported.\n", __func__);
967 return ehci_submit_async(dev, pipe, buffer, length, NULL);