2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/byteorder.h>
27 #include <asm/unaligned.h>
32 #include <linux/compiler.h>
36 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
37 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
41 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
42 * Let's time out after 8 to have a little safety margin on top of that.
44 #define HCHALT_TIMEOUT (8 * 1000)
47 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
50 #define ALIGN_END_ADDR(type, ptr, size) \
51 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
53 static struct descriptor {
54 struct usb_hub_descriptor hub;
55 struct usb_device_descriptor device;
56 struct usb_linux_config_descriptor config;
57 struct usb_linux_interface_descriptor interface;
58 struct usb_endpoint_descriptor endpoint;
59 } __attribute__ ((packed)) descriptor = {
61 0x8, /* bDescLength */
62 0x29, /* bDescriptorType: hub descriptor */
63 2, /* bNrPorts -- runtime modified */
64 0, /* wHubCharacteristics */
65 10, /* bPwrOn2PwrGood */
66 0, /* bHubCntrCurrent */
67 {}, /* Device removable */
68 {} /* at most 7 ports! XXX */
72 1, /* bDescriptorType: UDESC_DEVICE */
73 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
74 9, /* bDeviceClass: UDCLASS_HUB */
75 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
76 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
77 64, /* bMaxPacketSize: 64 bytes */
78 0x0000, /* idVendor */
79 0x0000, /* idProduct */
80 cpu_to_le16(0x0100), /* bcdDevice */
81 1, /* iManufacturer */
83 0, /* iSerialNumber */
84 1 /* bNumConfigurations: 1 */
88 2, /* bDescriptorType: UDESC_CONFIG */
90 1, /* bNumInterface */
91 1, /* bConfigurationValue */
92 0, /* iConfiguration */
93 0x40, /* bmAttributes: UC_SELF_POWER */
98 4, /* bDescriptorType: UDESC_INTERFACE */
99 0, /* bInterfaceNumber */
100 0, /* bAlternateSetting */
101 1, /* bNumEndpoints */
102 9, /* bInterfaceClass: UICLASS_HUB */
103 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
104 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
109 5, /* bDescriptorType: UDESC_ENDPOINT */
110 0x81, /* bEndpointAddress:
111 * UE_DIR_IN | EHCI_INTR_ENDPT
113 3, /* bmAttributes: UE_INTERRUPT */
114 8, /* wMaxPacketSize */
119 #if defined(CONFIG_EHCI_IS_TDI)
120 #define ehci_is_TDI() (1)
122 #define ehci_is_TDI() (0)
125 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
128 return dev_get_priv(usb_get_bus(udev->dev));
130 return udev->controller;
134 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
136 return PORTSC_PSPD(reg);
139 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
144 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
145 tmp = ehci_readl(reg_ptr);
146 tmp |= USBMODE_CM_HC;
147 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
150 ehci_writel(reg_ptr, tmp);
153 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
159 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
161 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
162 /* Printing the message would cause a scan failure! */
163 debug("The request port(%u) is not configured\n", port);
167 return (uint32_t *)&ctrl->hcor->or_portsc[port];
170 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
174 result = ehci_readl(ptr);
176 if (result == ~(uint32_t)0)
186 static int ehci_reset(struct ehci_ctrl *ctrl)
191 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
192 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
193 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
194 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
195 CMD_RESET, 0, 250 * 1000);
197 printf("EHCI fail to reset\n");
202 ctrl->ops.set_usb_mode(ctrl);
204 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
205 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
206 cmd &= ~TXFIFO_THRESH_MASK;
207 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
208 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
214 static int ehci_shutdown(struct ehci_ctrl *ctrl)
219 if (!ctrl || !ctrl->hcor)
222 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
223 cmd &= ~(CMD_PSE | CMD_ASE);
224 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
225 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
229 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
230 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
232 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
236 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
237 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
242 puts("EHCI failed to shut down host controller.\n");
247 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
249 uint32_t delta, next;
250 uint32_t addr = (unsigned long)buf;
253 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
254 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
256 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
259 while (idx < QT_BUFFER_CNT) {
260 td->qt_buffer[idx] = cpu_to_hc32(addr);
261 td->qt_buffer_hi[idx] = 0;
262 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
271 if (idx == QT_BUFFER_CNT) {
272 printf("out of buffer pointers (%zu bytes left)\n", sz);
279 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
281 #define QH_HIGH_SPEED 2
282 #define QH_FULL_SPEED 0
283 #define QH_LOW_SPEED 1
284 if (speed == USB_SPEED_HIGH)
285 return QH_HIGH_SPEED;
286 if (speed == USB_SPEED_LOW)
288 return QH_FULL_SPEED;
291 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
294 struct usb_device *ttdev;
297 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
301 * For full / low speed devices we need to get the devnum and portnr of
302 * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs
303 * in the tree before that one!
306 struct udevice *parent;
308 for (ttdev = udev; ; ) {
309 struct udevice *dev = ttdev->dev;
312 device_get_uclass_id(dev->parent) == UCLASS_USB_HUB)
313 parent = dev->parent;
318 ttdev = dev_get_parentdata(parent);
319 if (!ttdev->speed != USB_SPEED_HIGH)
322 parent_devnum = ttdev->devnum;
325 while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH)
326 ttdev = ttdev->parent;
329 parent_devnum = ttdev->parent->devnum;
332 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) |
333 QH_ENDPT2_HUBADDR(parent_devnum));
337 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
338 int length, struct devrequest *req)
340 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
344 volatile struct qTD *vtd;
347 uint32_t endpt, maxpacket, token, usbsts;
352 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
354 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
355 buffer, length, req);
357 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
358 req->request, req->request,
359 req->requesttype, req->requesttype,
360 le16_to_cpu(req->value), le16_to_cpu(req->value),
361 le16_to_cpu(req->index));
363 #define PKT_ALIGN 512
365 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
366 * described by a transfer descriptor (the qTD). The qTDs form a linked
367 * list with a queue head (QH).
369 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
370 * have its beginning in a qTD transfer and its end in the following
371 * one, so the qTD transfer lengths have to be chosen accordingly.
373 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
374 * single pages. The first data buffer can start at any offset within a
375 * page (not considering the cache-line alignment issues), while the
376 * following buffers must be page-aligned. There is no alignment
377 * constraint on the size of a qTD transfer.
380 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
382 if (length > 0 || req == NULL) {
384 * Determine the qTD transfer size that will be used for the
385 * data payload (not considering the first qTD transfer, which
386 * may be longer or shorter, and the final one, which may be
389 * In order to keep each packet within a qTD transfer, the qTD
390 * transfer size is aligned to PKT_ALIGN, which is a multiple of
391 * wMaxPacketSize (except in some cases for interrupt transfers,
392 * see comment in submit_int_msg()).
394 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
395 * QT_BUFFER_CNT full pages will be used.
397 int xfr_sz = QT_BUFFER_CNT;
399 * However, if the input buffer is not aligned to PKT_ALIGN, the
400 * qTD transfer size will be one page shorter, and the first qTD
401 * data buffer of each transfer will be page-unaligned.
403 if ((unsigned long)buffer & (PKT_ALIGN - 1))
405 /* Convert the qTD transfer size to bytes. */
406 xfr_sz *= EHCI_PAGE_SIZE;
408 * Approximate by excess the number of qTDs that will be
409 * required for the data payload. The exact formula is way more
410 * complicated and saves at most 2 qTDs, i.e. a total of 128
413 qtd_count += 2 + length / xfr_sz;
416 * Threshold value based on the worst-case total size of the allocated qTDs for
417 * a mass-storage transfer of 65535 blocks of 512 bytes.
419 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
420 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
422 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
424 printf("unable to allocate TDs\n");
428 memset(qh, 0, sizeof(struct QH));
429 memset(qtd, 0, qtd_count * sizeof(*qtd));
431 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
434 * Setup QH (3.6 in ehci-r10.pdf)
436 * qh_link ................. 03-00 H
437 * qh_endpt1 ............... 07-04 H
438 * qh_endpt2 ............... 0B-08 H
440 * qh_overlay.qt_next ...... 13-10 H
441 * - qh_overlay.qt_altnext
443 qh->qh_link = cpu_to_hc32((unsigned long)&ctrl->qh_list | QH_LINK_TYPE_QH);
444 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
445 maxpacket = usb_maxpacket(dev, pipe);
446 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
447 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
448 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
449 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
450 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
451 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
452 qh->qh_endpt1 = cpu_to_hc32(endpt);
453 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
454 qh->qh_endpt2 = cpu_to_hc32(endpt);
455 ehci_update_endpt2_dev_n_port(dev, qh);
456 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
457 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
459 tdp = &qh->qh_overlay.qt_next;
463 * Setup request qTD (3.5 in ehci-r10.pdf)
465 * qt_next ................ 03-00 H
466 * qt_altnext ............. 07-04 H
467 * qt_token ............... 0B-08 H
469 * [ buffer, buffer_hi ] loaded with "req".
471 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
472 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
473 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
474 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
475 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
476 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
477 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
478 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
479 printf("unable to construct SETUP TD\n");
482 /* Update previous qTD! */
483 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
484 tdp = &qtd[qtd_counter++].qt_next;
488 if (length > 0 || req == NULL) {
489 uint8_t *buf_ptr = buffer;
490 int left_length = length;
494 * Determine the size of this qTD transfer. By default,
495 * QT_BUFFER_CNT full pages can be used.
497 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
499 * However, if the input buffer is not page-aligned, the
500 * portion of the first page before the buffer start
501 * offset within that page is unusable.
503 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
505 * In order to keep each packet within a qTD transfer,
506 * align the qTD transfer size to PKT_ALIGN.
508 xfr_bytes &= ~(PKT_ALIGN - 1);
510 * This transfer may be shorter than the available qTD
511 * transfer size that has just been computed.
513 xfr_bytes = min(xfr_bytes, left_length);
516 * Setup request qTD (3.5 in ehci-r10.pdf)
518 * qt_next ................ 03-00 H
519 * qt_altnext ............. 07-04 H
520 * qt_token ............... 0B-08 H
522 * [ buffer, buffer_hi ] loaded with "buffer".
524 qtd[qtd_counter].qt_next =
525 cpu_to_hc32(QT_NEXT_TERMINATE);
526 qtd[qtd_counter].qt_altnext =
527 cpu_to_hc32(QT_NEXT_TERMINATE);
528 token = QT_TOKEN_DT(toggle) |
529 QT_TOKEN_TOTALBYTES(xfr_bytes) |
530 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
532 QT_TOKEN_PID(usb_pipein(pipe) ?
533 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
534 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
535 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
536 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
538 printf("unable to construct DATA TD\n");
541 /* Update previous qTD! */
542 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
543 tdp = &qtd[qtd_counter++].qt_next;
545 * Data toggle has to be adjusted since the qTD transfer
546 * size is not always an even multiple of
549 if ((xfr_bytes / maxpacket) & 1)
551 buf_ptr += xfr_bytes;
552 left_length -= xfr_bytes;
553 } while (left_length > 0);
558 * Setup request qTD (3.5 in ehci-r10.pdf)
560 * qt_next ................ 03-00 H
561 * qt_altnext ............. 07-04 H
562 * qt_token ............... 0B-08 H
564 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
565 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
566 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
567 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
568 QT_TOKEN_PID(usb_pipein(pipe) ?
569 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
570 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
571 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
572 /* Update previous qTD! */
573 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
574 tdp = &qtd[qtd_counter++].qt_next;
577 ctrl->qh_list.qh_link = cpu_to_hc32((unsigned long)qh | QH_LINK_TYPE_QH);
580 flush_dcache_range((unsigned long)&ctrl->qh_list,
581 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
582 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
583 flush_dcache_range((unsigned long)qtd,
584 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
586 /* Set async. queue head pointer. */
587 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)&ctrl->qh_list);
589 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
590 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
592 /* Enable async. schedule. */
593 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
595 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
597 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
600 printf("EHCI fail timeout STS_ASS set\n");
604 /* Wait for TDs to be processed. */
606 vtd = &qtd[qtd_counter - 1];
607 timeout = USB_TIMEOUT_MS(pipe);
609 /* Invalidate dcache */
610 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
611 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
612 invalidate_dcache_range((unsigned long)qh,
613 ALIGN_END_ADDR(struct QH, qh, 1));
614 invalidate_dcache_range((unsigned long)qtd,
615 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
617 token = hc32_to_cpu(vtd->qt_token);
618 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
621 } while (get_timer(ts) < timeout);
624 * Invalidate the memory area occupied by buffer
625 * Don't try to fix the buffer alignment, if it isn't properly
626 * aligned it's upper layer's fault so let invalidate_dcache_range()
627 * vow about it. But we have to fix the length as it's actual
628 * transfer length and can be unaligned. This is potentially
629 * dangerous operation, it's responsibility of the calling
630 * code to make sure enough space is reserved.
632 invalidate_dcache_range((unsigned long)buffer,
633 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
635 /* Check that the TD processing happened */
636 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
637 printf("EHCI timed out on TD - token=%#x\n", token);
639 /* Disable async schedule. */
640 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
642 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
644 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
647 printf("EHCI fail timeout STS_ASS reset\n");
651 token = hc32_to_cpu(qh->qh_overlay.qt_token);
652 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
653 debug("TOKEN=%#x\n", token);
654 switch (QT_TOKEN_GET_STATUS(token) &
655 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
657 toggle = QT_TOKEN_GET_DT(token);
658 usb_settoggle(dev, usb_pipeendpoint(pipe),
659 usb_pipeout(pipe), toggle);
662 case QT_TOKEN_STATUS_HALTED:
663 dev->status = USB_ST_STALLED;
665 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
666 case QT_TOKEN_STATUS_DATBUFERR:
667 dev->status = USB_ST_BUF_ERR;
669 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
670 case QT_TOKEN_STATUS_BABBLEDET:
671 dev->status = USB_ST_BABBLE_DET;
674 dev->status = USB_ST_CRC_ERR;
675 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
676 dev->status |= USB_ST_STALLED;
679 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
682 #ifndef CONFIG_USB_EHCI_FARADAY
683 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
684 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
685 ehci_readl(&ctrl->hcor->or_portsc[0]),
686 ehci_readl(&ctrl->hcor->or_portsc[1]));
691 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
698 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
699 void *buffer, int length, struct devrequest *req)
706 uint32_t *status_reg;
707 int port = le16_to_cpu(req->index) & 0xff;
708 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
712 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
713 req->request, req->request,
714 req->requesttype, req->requesttype,
715 le16_to_cpu(req->value), le16_to_cpu(req->index));
717 typeReq = req->request | req->requesttype << 8;
720 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
721 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
722 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
723 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
733 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
734 switch (le16_to_cpu(req->value) >> 8) {
736 debug("USB_DT_DEVICE request\n");
737 srcptr = &descriptor.device;
738 srclen = descriptor.device.bLength;
741 debug("USB_DT_CONFIG config\n");
742 srcptr = &descriptor.config;
743 srclen = descriptor.config.bLength +
744 descriptor.interface.bLength +
745 descriptor.endpoint.bLength;
748 debug("USB_DT_STRING config\n");
749 switch (le16_to_cpu(req->value) & 0xff) {
750 case 0: /* Language */
755 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
758 case 2: /* Product */
759 srcptr = "\52\3E\0H\0C\0I\0 "
761 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
765 debug("unknown value DT_STRING %x\n",
766 le16_to_cpu(req->value));
771 debug("unknown value %x\n", le16_to_cpu(req->value));
775 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
776 switch (le16_to_cpu(req->value) >> 8) {
778 debug("USB_DT_HUB config\n");
779 srcptr = &descriptor.hub;
780 srclen = descriptor.hub.bLength;
783 debug("unknown value %x\n", le16_to_cpu(req->value));
787 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
788 debug("USB_REQ_SET_ADDRESS\n");
789 ctrl->rootdev = le16_to_cpu(req->value);
791 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
792 debug("USB_REQ_SET_CONFIGURATION\n");
795 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
796 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
801 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
802 memset(tmpbuf, 0, 4);
803 reg = ehci_readl(status_reg);
804 if (reg & EHCI_PS_CS)
805 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
806 if (reg & EHCI_PS_PE)
807 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
808 if (reg & EHCI_PS_SUSP)
809 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
810 if (reg & EHCI_PS_OCA)
811 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
812 if (reg & EHCI_PS_PR)
813 tmpbuf[0] |= USB_PORT_STAT_RESET;
814 if (reg & EHCI_PS_PP)
815 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
818 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
822 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
826 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
830 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
833 if (reg & EHCI_PS_CSC)
834 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
835 if (reg & EHCI_PS_PEC)
836 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
837 if (reg & EHCI_PS_OCC)
838 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
839 if (ctrl->portreset & (1 << port))
840 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
845 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
846 reg = ehci_readl(status_reg);
847 reg &= ~EHCI_PS_CLEAR;
848 switch (le16_to_cpu(req->value)) {
849 case USB_PORT_FEAT_ENABLE:
851 ehci_writel(status_reg, reg);
853 case USB_PORT_FEAT_POWER:
854 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
856 ehci_writel(status_reg, reg);
859 case USB_PORT_FEAT_RESET:
860 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
862 EHCI_PS_IS_LOWSPEED(reg)) {
863 /* Low speed device, give up ownership. */
864 debug("port %d low speed --> companion\n",
867 ehci_writel(status_reg, reg);
874 ehci_writel(status_reg, reg);
876 * caller must wait, then call GetPortStatus
877 * usb 2.0 specification say 50 ms resets on
880 ctrl->ops.powerup_fixup(ctrl, status_reg, ®);
882 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
884 * A host controller must terminate the reset
885 * and stabilize the state of the port within
888 ret = handshake(status_reg, EHCI_PS_PR, 0,
891 ctrl->portreset |= 1 << port;
893 printf("port(%d) reset error\n",
897 case USB_PORT_FEAT_TEST:
900 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
901 ehci_writel(status_reg, reg);
904 debug("unknown feature %x\n", le16_to_cpu(req->value));
907 /* unblock posted writes */
908 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
910 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
911 reg = ehci_readl(status_reg);
912 reg &= ~EHCI_PS_CLEAR;
913 switch (le16_to_cpu(req->value)) {
914 case USB_PORT_FEAT_ENABLE:
917 case USB_PORT_FEAT_C_ENABLE:
920 case USB_PORT_FEAT_POWER:
921 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
924 case USB_PORT_FEAT_C_CONNECTION:
927 case USB_PORT_FEAT_OVER_CURRENT:
930 case USB_PORT_FEAT_C_RESET:
931 ctrl->portreset &= ~(1 << port);
934 debug("unknown feature %x\n", le16_to_cpu(req->value));
937 ehci_writel(status_reg, reg);
938 /* unblock posted write */
939 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
942 debug("Unknown request\n");
947 len = min3(srclen, (int)le16_to_cpu(req->length), length);
948 if (srcptr != NULL && len > 0)
949 memcpy(buffer, srcptr, len);
958 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
959 req->requesttype, req->request, le16_to_cpu(req->value),
960 le16_to_cpu(req->index), le16_to_cpu(req->length));
963 dev->status = USB_ST_STALLED;
967 const struct ehci_ops default_ehci_ops = {
968 .set_usb_mode = ehci_set_usbmode,
969 .get_port_speed = ehci_get_port_speed,
970 .powerup_fixup = ehci_powerup_fixup,
971 .get_portsc_register = ehci_get_portsc_register,
974 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
977 ctrl->ops = default_ehci_ops;
980 if (!ctrl->ops.set_usb_mode)
981 ctrl->ops.set_usb_mode = ehci_set_usbmode;
982 if (!ctrl->ops.get_port_speed)
983 ctrl->ops.get_port_speed = ehci_get_port_speed;
984 if (!ctrl->ops.powerup_fixup)
985 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
986 if (!ctrl->ops.get_portsc_register)
987 ctrl->ops.get_portsc_register =
988 ehci_get_portsc_register;
992 #ifndef CONFIG_DM_USB
993 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
995 struct ehci_ctrl *ctrl = &ehcic[index];
998 ehci_setup_ops(ctrl, ops);
1001 void *ehci_get_controller_priv(int index)
1003 return ehcic[index].priv;
1007 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
1010 struct QH *periodic;
1015 /* Set the high address word (aka segment) for 64-bit controller */
1016 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1017 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1019 qh_list = &ctrl->qh_list;
1021 /* Set head of reclaim list */
1022 memset(qh_list, 0, sizeof(*qh_list));
1023 qh_list->qh_link = cpu_to_hc32((unsigned long)qh_list | QH_LINK_TYPE_QH);
1024 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1025 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1026 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1027 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1028 qh_list->qh_overlay.qt_token =
1029 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1031 flush_dcache_range((unsigned long)qh_list,
1032 ALIGN_END_ADDR(struct QH, qh_list, 1));
1034 /* Set async. queue head pointer. */
1035 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)qh_list);
1038 * Set up periodic list
1039 * Step 1: Parent QH for all periodic transfers.
1041 ctrl->periodic_schedules = 0;
1042 periodic = &ctrl->periodic_queue;
1043 memset(periodic, 0, sizeof(*periodic));
1044 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1045 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1046 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1048 flush_dcache_range((unsigned long)periodic,
1049 ALIGN_END_ADDR(struct QH, periodic, 1));
1052 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1053 * In particular, device specifications on polling frequency
1054 * are disregarded. Keyboards seem to send NAK/NYet reliably
1055 * when polled with an empty buffer.
1057 * Split Transactions will be spread across microframes using
1058 * S-mask and C-mask.
1060 if (ctrl->periodic_list == NULL)
1061 ctrl->periodic_list = memalign(4096, 1024 * 4);
1063 if (!ctrl->periodic_list)
1065 for (i = 0; i < 1024; i++) {
1066 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1070 flush_dcache_range((unsigned long)ctrl->periodic_list,
1071 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1074 /* Set periodic list base address */
1075 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1076 (unsigned long)ctrl->periodic_list);
1078 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1079 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1080 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1081 /* Port Indicators */
1082 if (HCS_INDICATOR(reg))
1083 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1084 | 0x80, &descriptor.hub.wHubCharacteristics);
1085 /* Port Power Control */
1087 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1088 | 0x01, &descriptor.hub.wHubCharacteristics);
1090 /* Start the host controller. */
1091 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1093 * Philips, Intel, and maybe others need CMD_RUN before the
1094 * root hub will detect new devices (why?); NEC doesn't
1096 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1098 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1100 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1101 /* take control over the ports */
1102 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1104 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1107 /* unblock posted write */
1108 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1110 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1111 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1116 #ifndef CONFIG_DM_USB
1117 int usb_lowlevel_stop(int index)
1119 ehci_shutdown(&ehcic[index]);
1120 return ehci_hcd_stop(index);
1123 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1125 struct ehci_ctrl *ctrl = &ehcic[index];
1130 * Set ops to default_ehci_ops, ehci_hcd_init should call
1131 * ehci_set_controller_priv to change any of these function pointers.
1133 ctrl->ops = default_ehci_ops;
1135 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1138 if (init == USB_INIT_DEVICE)
1141 /* EHCI spec section 4.1 */
1142 if (ehci_reset(ctrl))
1145 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1146 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1150 #ifdef CONFIG_USB_EHCI_FARADAY
1151 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1153 rc = ehci_common_init(ctrl, tweaks);
1159 *controller = &ehcic[index];
1164 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1165 void *buffer, int length)
1168 if (usb_pipetype(pipe) != PIPE_BULK) {
1169 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1172 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1175 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1176 void *buffer, int length,
1177 struct devrequest *setup)
1179 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1181 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1182 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1186 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1188 dev->speed = USB_SPEED_HIGH;
1189 return ehci_submit_root(dev, pipe, buffer, length, setup);
1191 return ehci_submit_async(dev, pipe, buffer, length, setup);
1202 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1205 enable_periodic(struct ehci_ctrl *ctrl)
1208 struct ehci_hcor *hcor = ctrl->hcor;
1211 cmd = ehci_readl(&hcor->or_usbcmd);
1213 ehci_writel(&hcor->or_usbcmd, cmd);
1215 ret = handshake((uint32_t *)&hcor->or_usbsts,
1216 STS_PSS, STS_PSS, 100 * 1000);
1218 printf("EHCI failed: timeout when enabling periodic list\n");
1226 disable_periodic(struct ehci_ctrl *ctrl)
1229 struct ehci_hcor *hcor = ctrl->hcor;
1232 cmd = ehci_readl(&hcor->or_usbcmd);
1234 ehci_writel(&hcor->or_usbcmd, cmd);
1236 ret = handshake((uint32_t *)&hcor->or_usbsts,
1237 STS_PSS, 0, 100 * 1000);
1239 printf("EHCI failed: timeout when disabling periodic list\n");
1246 create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
1247 int elementsize, void *buffer, int interval)
1249 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1250 struct int_queue *result = NULL;
1254 * Interrupt transfers requiring several transactions are not supported
1255 * because bInterval is ignored.
1257 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1258 * <= PKT_ALIGN if several qTDs are required, while the USB
1259 * specification does not constrain this for interrupt transfers. That
1260 * means that ehci_submit_async() would support interrupt transfers
1261 * requiring several transactions only as long as the transfer size does
1262 * not require more than a single qTD.
1264 if (elementsize > usb_maxpacket(dev, pipe)) {
1265 printf("%s: xfers requiring several transactions are not supported.\n",
1270 debug("Enter create_int_queue\n");
1271 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1272 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1276 /* limit to 4 full pages worth of data -
1277 * we can safely fit them in a single TD,
1278 * no matter the alignment
1280 if (elementsize >= 16384) {
1281 debug("too large elements for interrupt transfers\n");
1285 result = malloc(sizeof(*result));
1287 debug("ehci intr queue: out of memory\n");
1290 result->elementsize = elementsize;
1291 result->first = memalign(USB_DMA_MINALIGN,
1292 sizeof(struct QH) * queuesize);
1293 if (!result->first) {
1294 debug("ehci intr queue: out of memory\n");
1297 result->current = result->first;
1298 result->last = result->first + queuesize - 1;
1299 result->tds = memalign(USB_DMA_MINALIGN,
1300 sizeof(struct qTD) * queuesize);
1302 debug("ehci intr queue: out of memory\n");
1305 memset(result->first, 0, sizeof(struct QH) * queuesize);
1306 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1308 for (i = 0; i < queuesize; i++) {
1309 struct QH *qh = result->first + i;
1310 struct qTD *td = result->tds + i;
1311 void **buf = &qh->buffer;
1313 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1314 if (i == queuesize - 1)
1315 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1317 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1318 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1320 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1321 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1323 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1324 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1325 (usb_pipedevice(pipe) << 0));
1326 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1327 (1 << 0)); /* S-mask: microframe 0 */
1328 if (dev->speed == USB_SPEED_LOW ||
1329 dev->speed == USB_SPEED_FULL) {
1330 /* C-mask: microframes 2-4 */
1331 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1333 ehci_update_endpt2_dev_n_port(dev, qh);
1335 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1336 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1337 debug("communication direction is '%s'\n",
1338 usb_pipein(pipe) ? "in" : "out");
1339 td->qt_token = cpu_to_hc32((elementsize << 16) |
1340 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1343 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1345 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1347 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1349 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1351 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1353 *buf = buffer + i * elementsize;
1356 flush_dcache_range((unsigned long)buffer,
1357 ALIGN_END_ADDR(char, buffer,
1358 queuesize * elementsize));
1359 flush_dcache_range((unsigned long)result->first,
1360 ALIGN_END_ADDR(struct QH, result->first,
1362 flush_dcache_range((unsigned long)result->tds,
1363 ALIGN_END_ADDR(struct qTD, result->tds,
1366 if (ctrl->periodic_schedules > 0) {
1367 if (disable_periodic(ctrl) < 0) {
1368 debug("FATAL: periodic should never fail, but did");
1373 /* hook up to periodic list */
1374 struct QH *list = &ctrl->periodic_queue;
1375 result->last->qh_link = list->qh_link;
1376 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1378 flush_dcache_range((unsigned long)result->last,
1379 ALIGN_END_ADDR(struct QH, result->last, 1));
1380 flush_dcache_range((unsigned long)list,
1381 ALIGN_END_ADDR(struct QH, list, 1));
1383 if (enable_periodic(ctrl) < 0) {
1384 debug("FATAL: periodic should never fail, but did");
1387 ctrl->periodic_schedules++;
1389 debug("Exit create_int_queue\n");
1396 free(result->first);
1403 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1405 struct QH *cur = queue->current;
1408 /* depleted queue */
1410 debug("Exit poll_int_queue with completed queue\n");
1414 cur_td = &queue->tds[queue->current - queue->first];
1415 invalidate_dcache_range((unsigned long)cur_td,
1416 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1417 if (QT_TOKEN_GET_STATUS(hc32_to_cpu(cur_td->qt_token)) &
1418 QT_TOKEN_STATUS_ACTIVE) {
1419 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n",
1420 hc32_to_cpu(cur_td->qt_token));
1423 if (!(cur->qh_link & QH_LINK_TERMINATE))
1426 queue->current = NULL;
1428 invalidate_dcache_range((unsigned long)cur->buffer,
1429 ALIGN_END_ADDR(char, cur->buffer,
1430 queue->elementsize));
1432 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1433 hc32_to_cpu(cur_td->qt_token), cur, queue->first);
1437 /* Do not free buffers associated with QHs, they're owned by someone else */
1439 destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1441 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1443 unsigned long timeout;
1445 if (disable_periodic(ctrl) < 0) {
1446 debug("FATAL: periodic should never fail, but did");
1449 ctrl->periodic_schedules--;
1451 struct QH *cur = &ctrl->periodic_queue;
1452 timeout = get_timer(0) + 500; /* abort after 500ms */
1453 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1454 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1455 if (NEXT_QH(cur) == queue->first) {
1456 debug("found candidate. removing from chain\n");
1457 cur->qh_link = queue->last->qh_link;
1458 flush_dcache_range((unsigned long)cur,
1459 ALIGN_END_ADDR(struct QH, cur, 1));
1464 if (get_timer(0) > timeout) {
1465 printf("Timeout destroying interrupt endpoint queue\n");
1471 if (ctrl->periodic_schedules > 0) {
1472 result = enable_periodic(ctrl);
1474 debug("FATAL: periodic should never fail, but did");
1485 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1486 void *buffer, int length, int interval)
1489 struct int_queue *queue;
1490 unsigned long timeout;
1491 int result = 0, ret;
1493 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1494 dev, pipe, buffer, length, interval);
1496 queue = create_int_queue(dev, pipe, 1, length, buffer, interval);
1500 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1501 while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
1502 if (get_timer(0) > timeout) {
1503 printf("Timeout poll on interrupt endpoint\n");
1504 result = -ETIMEDOUT;
1508 if (backbuffer != buffer) {
1509 debug("got wrong buffer back (%p instead of %p)\n",
1510 backbuffer, buffer);
1514 ret = destroy_int_queue(dev, queue);
1518 /* everything worked out fine */
1522 #ifndef CONFIG_DM_USB
1523 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1524 void *buffer, int length)
1526 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1529 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1530 int length, struct devrequest *setup)
1532 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1535 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1536 void *buffer, int length, int interval)
1538 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
1542 #ifdef CONFIG_DM_USB
1543 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1544 unsigned long pipe, void *buffer, int length,
1545 struct devrequest *setup)
1547 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1548 dev->name, udev, udev->dev->name, udev->portnr);
1550 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1553 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1554 unsigned long pipe, void *buffer, int length)
1556 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1557 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1560 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1561 unsigned long pipe, void *buffer, int length,
1564 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1565 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
1568 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1569 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1570 uint tweaks, enum usb_init_type init)
1572 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1575 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1576 dev->name, ctrl, hccr, hcor, init);
1578 ehci_setup_ops(ctrl, ops);
1583 if (init == USB_INIT_DEVICE)
1585 ret = ehci_reset(ctrl);
1589 ret = ehci_common_init(ctrl, tweaks);
1596 debug("%s: failed, ret=%d\n", __func__, ret);
1600 int ehci_deregister(struct udevice *dev)
1602 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1604 ehci_shutdown(ctrl);
1609 struct dm_usb_ops ehci_usb_ops = {
1610 .control = ehci_submit_control_msg,
1611 .bulk = ehci_submit_bulk_msg,
1612 .interrupt = ehci_submit_int_msg,