2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * SPDX-License-Identifier: GPL-2.0
13 #include <asm/byteorder.h>
14 #include <asm/unaligned.h>
20 #include <linux/compiler.h>
24 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
25 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
29 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
30 * Let's time out after 8 to have a little safety margin on top of that.
32 #define HCHALT_TIMEOUT (8 * 1000)
35 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
38 #define ALIGN_END_ADDR(type, ptr, size) \
39 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
41 static struct descriptor {
42 struct usb_hub_descriptor hub;
43 struct usb_device_descriptor device;
44 struct usb_linux_config_descriptor config;
45 struct usb_linux_interface_descriptor interface;
46 struct usb_endpoint_descriptor endpoint;
47 } __attribute__ ((packed)) descriptor = {
49 0x8, /* bDescLength */
50 0x29, /* bDescriptorType: hub descriptor */
51 2, /* bNrPorts -- runtime modified */
52 0, /* wHubCharacteristics */
53 10, /* bPwrOn2PwrGood */
54 0, /* bHubCntrCurrent */
55 { /* Device removable */
56 } /* at most 7 ports! XXX */
60 1, /* bDescriptorType: UDESC_DEVICE */
61 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
62 9, /* bDeviceClass: UDCLASS_HUB */
63 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
64 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
65 64, /* bMaxPacketSize: 64 bytes */
66 0x0000, /* idVendor */
67 0x0000, /* idProduct */
68 cpu_to_le16(0x0100), /* bcdDevice */
69 1, /* iManufacturer */
71 0, /* iSerialNumber */
72 1 /* bNumConfigurations: 1 */
76 2, /* bDescriptorType: UDESC_CONFIG */
78 1, /* bNumInterface */
79 1, /* bConfigurationValue */
80 0, /* iConfiguration */
81 0x40, /* bmAttributes: UC_SELF_POWER */
86 4, /* bDescriptorType: UDESC_INTERFACE */
87 0, /* bInterfaceNumber */
88 0, /* bAlternateSetting */
89 1, /* bNumEndpoints */
90 9, /* bInterfaceClass: UICLASS_HUB */
91 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
92 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
97 5, /* bDescriptorType: UDESC_ENDPOINT */
98 0x81, /* bEndpointAddress:
99 * UE_DIR_IN | EHCI_INTR_ENDPT
101 3, /* bmAttributes: UE_INTERRUPT */
102 8, /* wMaxPacketSize */
107 #if defined(CONFIG_EHCI_IS_TDI)
108 #define ehci_is_TDI() (1)
110 #define ehci_is_TDI() (0)
113 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
116 return dev_get_priv(usb_get_bus(udev->dev));
118 return udev->controller;
122 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
124 return PORTSC_PSPD(reg);
127 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
132 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
133 tmp = ehci_readl(reg_ptr);
134 tmp |= USBMODE_CM_HC;
135 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
140 ehci_writel(reg_ptr, tmp);
143 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
149 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
151 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
153 if (port < 0 || port >= max_ports) {
154 /* Printing the message would cause a scan failure! */
155 debug("The request port(%u) exceeds maximum port number\n",
160 return (uint32_t *)&ctrl->hcor->or_portsc[port];
163 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
167 result = ehci_readl(ptr);
169 if (result == ~(uint32_t)0)
179 static int ehci_reset(struct ehci_ctrl *ctrl)
184 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
185 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
186 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
187 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
188 CMD_RESET, 0, 250 * 1000);
190 printf("EHCI fail to reset\n");
195 ctrl->ops.set_usb_mode(ctrl);
197 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
198 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
199 cmd &= ~TXFIFO_THRESH_MASK;
200 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
201 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
207 static int ehci_shutdown(struct ehci_ctrl *ctrl)
211 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
213 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
214 /* If not run, directly return */
215 if (!(cmd & CMD_RUN))
217 cmd &= ~(CMD_PSE | CMD_ASE);
218 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
219 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
223 for (i = 0; i < max_ports; i++) {
224 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
226 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
230 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
231 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
236 puts("EHCI failed to shut down host controller.\n");
241 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
243 uint32_t delta, next;
244 unsigned long addr = (unsigned long)buf;
247 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
248 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
250 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
253 while (idx < QT_BUFFER_CNT) {
254 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
255 td->qt_buffer_hi[idx] = 0;
256 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
265 if (idx == QT_BUFFER_CNT) {
266 printf("out of buffer pointers (%zu bytes left)\n", sz);
273 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
275 #define QH_HIGH_SPEED 2
276 #define QH_FULL_SPEED 0
277 #define QH_LOW_SPEED 1
278 if (speed == USB_SPEED_HIGH)
279 return QH_HIGH_SPEED;
280 if (speed == USB_SPEED_LOW)
282 return QH_FULL_SPEED;
285 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
291 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
294 usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
296 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
297 QH_ENDPT2_HUBADDR(hubaddr));
301 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
302 int length, struct devrequest *req)
304 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
308 volatile struct qTD *vtd;
311 uint32_t endpt, maxpacket, token, usbsts;
316 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
318 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
319 buffer, length, req);
321 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
322 req->request, req->request,
323 req->requesttype, req->requesttype,
324 le16_to_cpu(req->value), le16_to_cpu(req->value),
325 le16_to_cpu(req->index));
327 #define PKT_ALIGN 512
329 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
330 * described by a transfer descriptor (the qTD). The qTDs form a linked
331 * list with a queue head (QH).
333 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
334 * have its beginning in a qTD transfer and its end in the following
335 * one, so the qTD transfer lengths have to be chosen accordingly.
337 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
338 * single pages. The first data buffer can start at any offset within a
339 * page (not considering the cache-line alignment issues), while the
340 * following buffers must be page-aligned. There is no alignment
341 * constraint on the size of a qTD transfer.
344 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
346 if (length > 0 || req == NULL) {
348 * Determine the qTD transfer size that will be used for the
349 * data payload (not considering the first qTD transfer, which
350 * may be longer or shorter, and the final one, which may be
353 * In order to keep each packet within a qTD transfer, the qTD
354 * transfer size is aligned to PKT_ALIGN, which is a multiple of
355 * wMaxPacketSize (except in some cases for interrupt transfers,
356 * see comment in submit_int_msg()).
358 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
359 * QT_BUFFER_CNT full pages will be used.
361 int xfr_sz = QT_BUFFER_CNT;
363 * However, if the input buffer is not aligned to PKT_ALIGN, the
364 * qTD transfer size will be one page shorter, and the first qTD
365 * data buffer of each transfer will be page-unaligned.
367 if ((unsigned long)buffer & (PKT_ALIGN - 1))
369 /* Convert the qTD transfer size to bytes. */
370 xfr_sz *= EHCI_PAGE_SIZE;
372 * Approximate by excess the number of qTDs that will be
373 * required for the data payload. The exact formula is way more
374 * complicated and saves at most 2 qTDs, i.e. a total of 128
377 qtd_count += 2 + length / xfr_sz;
380 * Threshold value based on the worst-case total size of the allocated qTDs for
381 * a mass-storage transfer of 65535 blocks of 512 bytes.
383 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
384 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
386 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
388 printf("unable to allocate TDs\n");
392 memset(qh, 0, sizeof(struct QH));
393 memset(qtd, 0, qtd_count * sizeof(*qtd));
395 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
398 * Setup QH (3.6 in ehci-r10.pdf)
400 * qh_link ................. 03-00 H
401 * qh_endpt1 ............... 07-04 H
402 * qh_endpt2 ............... 0B-08 H
404 * qh_overlay.qt_next ...... 13-10 H
405 * - qh_overlay.qt_altnext
407 qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
408 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
409 maxpacket = usb_maxpacket(dev, pipe);
410 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
411 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
412 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
413 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
414 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
415 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
416 qh->qh_endpt1 = cpu_to_hc32(endpt);
417 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
418 qh->qh_endpt2 = cpu_to_hc32(endpt);
419 ehci_update_endpt2_dev_n_port(dev, qh);
420 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
421 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
423 tdp = &qh->qh_overlay.qt_next;
426 * Setup request qTD (3.5 in ehci-r10.pdf)
428 * qt_next ................ 03-00 H
429 * qt_altnext ............. 07-04 H
430 * qt_token ............... 0B-08 H
432 * [ buffer, buffer_hi ] loaded with "req".
434 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
435 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
436 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
437 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
438 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
439 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
440 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
441 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
442 printf("unable to construct SETUP TD\n");
445 /* Update previous qTD! */
446 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
447 tdp = &qtd[qtd_counter++].qt_next;
451 if (length > 0 || req == NULL) {
452 uint8_t *buf_ptr = buffer;
453 int left_length = length;
457 * Determine the size of this qTD transfer. By default,
458 * QT_BUFFER_CNT full pages can be used.
460 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
462 * However, if the input buffer is not page-aligned, the
463 * portion of the first page before the buffer start
464 * offset within that page is unusable.
466 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
468 * In order to keep each packet within a qTD transfer,
469 * align the qTD transfer size to PKT_ALIGN.
471 xfr_bytes &= ~(PKT_ALIGN - 1);
473 * This transfer may be shorter than the available qTD
474 * transfer size that has just been computed.
476 xfr_bytes = min(xfr_bytes, left_length);
479 * Setup request qTD (3.5 in ehci-r10.pdf)
481 * qt_next ................ 03-00 H
482 * qt_altnext ............. 07-04 H
483 * qt_token ............... 0B-08 H
485 * [ buffer, buffer_hi ] loaded with "buffer".
487 qtd[qtd_counter].qt_next =
488 cpu_to_hc32(QT_NEXT_TERMINATE);
489 qtd[qtd_counter].qt_altnext =
490 cpu_to_hc32(QT_NEXT_TERMINATE);
491 token = QT_TOKEN_DT(toggle) |
492 QT_TOKEN_TOTALBYTES(xfr_bytes) |
493 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
495 QT_TOKEN_PID(usb_pipein(pipe) ?
496 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
497 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
498 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
499 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
501 printf("unable to construct DATA TD\n");
504 /* Update previous qTD! */
505 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
506 tdp = &qtd[qtd_counter++].qt_next;
508 * Data toggle has to be adjusted since the qTD transfer
509 * size is not always an even multiple of
512 if ((xfr_bytes / maxpacket) & 1)
514 buf_ptr += xfr_bytes;
515 left_length -= xfr_bytes;
516 } while (left_length > 0);
521 * Setup request qTD (3.5 in ehci-r10.pdf)
523 * qt_next ................ 03-00 H
524 * qt_altnext ............. 07-04 H
525 * qt_token ............... 0B-08 H
527 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
528 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
529 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
530 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
531 QT_TOKEN_PID(usb_pipein(pipe) ?
532 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
533 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
534 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
535 /* Update previous qTD! */
536 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
537 tdp = &qtd[qtd_counter++].qt_next;
540 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
543 flush_dcache_range((unsigned long)&ctrl->qh_list,
544 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
545 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
546 flush_dcache_range((unsigned long)qtd,
547 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
549 /* Set async. queue head pointer. */
550 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(&ctrl->qh_list));
552 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
553 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
555 /* Enable async. schedule. */
556 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
558 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
560 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
563 printf("EHCI fail timeout STS_ASS set\n");
567 /* Wait for TDs to be processed. */
569 vtd = &qtd[qtd_counter - 1];
570 timeout = USB_TIMEOUT_MS(pipe);
572 /* Invalidate dcache */
573 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
574 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
575 invalidate_dcache_range((unsigned long)qh,
576 ALIGN_END_ADDR(struct QH, qh, 1));
577 invalidate_dcache_range((unsigned long)qtd,
578 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
580 token = hc32_to_cpu(vtd->qt_token);
581 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
584 } while (get_timer(ts) < timeout);
587 * Invalidate the memory area occupied by buffer
588 * Don't try to fix the buffer alignment, if it isn't properly
589 * aligned it's upper layer's fault so let invalidate_dcache_range()
590 * vow about it. But we have to fix the length as it's actual
591 * transfer length and can be unaligned. This is potentially
592 * dangerous operation, it's responsibility of the calling
593 * code to make sure enough space is reserved.
595 invalidate_dcache_range((unsigned long)buffer,
596 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
598 /* Check that the TD processing happened */
599 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
600 printf("EHCI timed out on TD - token=%#x\n", token);
602 /* Disable async schedule. */
603 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
605 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
607 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
610 printf("EHCI fail timeout STS_ASS reset\n");
614 token = hc32_to_cpu(qh->qh_overlay.qt_token);
615 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
616 debug("TOKEN=%#x\n", token);
617 switch (QT_TOKEN_GET_STATUS(token) &
618 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
620 toggle = QT_TOKEN_GET_DT(token);
621 usb_settoggle(dev, usb_pipeendpoint(pipe),
622 usb_pipeout(pipe), toggle);
625 case QT_TOKEN_STATUS_HALTED:
626 dev->status = USB_ST_STALLED;
628 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
629 case QT_TOKEN_STATUS_DATBUFERR:
630 dev->status = USB_ST_BUF_ERR;
632 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
633 case QT_TOKEN_STATUS_BABBLEDET:
634 dev->status = USB_ST_BABBLE_DET;
637 dev->status = USB_ST_CRC_ERR;
638 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
639 dev->status |= USB_ST_STALLED;
642 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
645 #ifndef CONFIG_USB_EHCI_FARADAY
646 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
647 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
648 ehci_readl(&ctrl->hcor->or_portsc[0]),
649 ehci_readl(&ctrl->hcor->or_portsc[1]));
654 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
661 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
662 void *buffer, int length, struct devrequest *req)
669 uint32_t *status_reg;
670 int port = le16_to_cpu(req->index) & 0xff;
671 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
675 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
676 req->request, req->request,
677 req->requesttype, req->requesttype,
678 le16_to_cpu(req->value), le16_to_cpu(req->index));
680 typeReq = req->request | req->requesttype << 8;
683 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
684 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
685 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
686 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
696 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
697 switch (le16_to_cpu(req->value) >> 8) {
699 debug("USB_DT_DEVICE request\n");
700 srcptr = &descriptor.device;
701 srclen = descriptor.device.bLength;
704 debug("USB_DT_CONFIG config\n");
705 srcptr = &descriptor.config;
706 srclen = descriptor.config.bLength +
707 descriptor.interface.bLength +
708 descriptor.endpoint.bLength;
711 debug("USB_DT_STRING config\n");
712 switch (le16_to_cpu(req->value) & 0xff) {
713 case 0: /* Language */
718 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
721 case 2: /* Product */
722 srcptr = "\52\3E\0H\0C\0I\0 "
724 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
728 debug("unknown value DT_STRING %x\n",
729 le16_to_cpu(req->value));
734 debug("unknown value %x\n", le16_to_cpu(req->value));
738 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
739 switch (le16_to_cpu(req->value) >> 8) {
741 debug("USB_DT_HUB config\n");
742 srcptr = &descriptor.hub;
743 srclen = descriptor.hub.bLength;
746 debug("unknown value %x\n", le16_to_cpu(req->value));
750 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
751 debug("USB_REQ_SET_ADDRESS\n");
752 ctrl->rootdev = le16_to_cpu(req->value);
754 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
755 debug("USB_REQ_SET_CONFIGURATION\n");
758 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
759 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
764 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
765 memset(tmpbuf, 0, 4);
766 reg = ehci_readl(status_reg);
767 if (reg & EHCI_PS_CS)
768 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
769 if (reg & EHCI_PS_PE)
770 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
771 if (reg & EHCI_PS_SUSP)
772 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
773 if (reg & EHCI_PS_OCA)
774 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
775 if (reg & EHCI_PS_PR)
776 tmpbuf[0] |= USB_PORT_STAT_RESET;
777 if (reg & EHCI_PS_PP)
778 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
781 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
785 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
789 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
793 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
796 if (reg & EHCI_PS_CSC)
797 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
798 if (reg & EHCI_PS_PEC)
799 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
800 if (reg & EHCI_PS_OCC)
801 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
802 if (ctrl->portreset & (1 << port))
803 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
808 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
809 reg = ehci_readl(status_reg);
810 reg &= ~EHCI_PS_CLEAR;
811 switch (le16_to_cpu(req->value)) {
812 case USB_PORT_FEAT_ENABLE:
814 ehci_writel(status_reg, reg);
816 case USB_PORT_FEAT_POWER:
817 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
819 ehci_writel(status_reg, reg);
822 case USB_PORT_FEAT_RESET:
823 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
825 EHCI_PS_IS_LOWSPEED(reg)) {
826 /* Low speed device, give up ownership. */
827 debug("port %d low speed --> companion\n",
830 ehci_writel(status_reg, reg);
837 ehci_writel(status_reg, reg);
839 * caller must wait, then call GetPortStatus
840 * usb 2.0 specification say 50 ms resets on
843 ctrl->ops.powerup_fixup(ctrl, status_reg, ®);
845 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
847 * A host controller must terminate the reset
848 * and stabilize the state of the port within
851 ret = handshake(status_reg, EHCI_PS_PR, 0,
854 reg = ehci_readl(status_reg);
855 if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
856 == EHCI_PS_CS && !ehci_is_TDI()) {
857 debug("port %d full speed --> companion\n", port - 1);
858 reg &= ~EHCI_PS_CLEAR;
860 ehci_writel(status_reg, reg);
863 ctrl->portreset |= 1 << port;
866 printf("port(%d) reset error\n",
871 case USB_PORT_FEAT_TEST:
874 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
875 ehci_writel(status_reg, reg);
878 debug("unknown feature %x\n", le16_to_cpu(req->value));
881 /* unblock posted writes */
882 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
884 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
885 reg = ehci_readl(status_reg);
886 reg &= ~EHCI_PS_CLEAR;
887 switch (le16_to_cpu(req->value)) {
888 case USB_PORT_FEAT_ENABLE:
891 case USB_PORT_FEAT_C_ENABLE:
894 case USB_PORT_FEAT_POWER:
895 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
898 case USB_PORT_FEAT_C_CONNECTION:
901 case USB_PORT_FEAT_OVER_CURRENT:
904 case USB_PORT_FEAT_C_RESET:
905 ctrl->portreset &= ~(1 << port);
908 debug("unknown feature %x\n", le16_to_cpu(req->value));
911 ehci_writel(status_reg, reg);
912 /* unblock posted write */
913 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
916 debug("Unknown request\n");
921 len = min3(srclen, (int)le16_to_cpu(req->length), length);
922 if (srcptr != NULL && len > 0)
923 memcpy(buffer, srcptr, len);
932 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
933 req->requesttype, req->request, le16_to_cpu(req->value),
934 le16_to_cpu(req->index), le16_to_cpu(req->length));
937 dev->status = USB_ST_STALLED;
941 static const struct ehci_ops default_ehci_ops = {
942 .set_usb_mode = ehci_set_usbmode,
943 .get_port_speed = ehci_get_port_speed,
944 .powerup_fixup = ehci_powerup_fixup,
945 .get_portsc_register = ehci_get_portsc_register,
948 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
951 ctrl->ops = default_ehci_ops;
954 if (!ctrl->ops.set_usb_mode)
955 ctrl->ops.set_usb_mode = ehci_set_usbmode;
956 if (!ctrl->ops.get_port_speed)
957 ctrl->ops.get_port_speed = ehci_get_port_speed;
958 if (!ctrl->ops.powerup_fixup)
959 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
960 if (!ctrl->ops.get_portsc_register)
961 ctrl->ops.get_portsc_register =
962 ehci_get_portsc_register;
966 #ifndef CONFIG_DM_USB
967 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
969 struct ehci_ctrl *ctrl = &ehcic[index];
972 ehci_setup_ops(ctrl, ops);
975 void *ehci_get_controller_priv(int index)
977 return ehcic[index].priv;
981 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
989 /* Set the high address word (aka segment) for 64-bit controller */
990 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
991 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
993 qh_list = &ctrl->qh_list;
995 /* Set head of reclaim list */
996 memset(qh_list, 0, sizeof(*qh_list));
997 qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
998 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
999 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1000 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1001 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1002 qh_list->qh_overlay.qt_token =
1003 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1005 flush_dcache_range((unsigned long)qh_list,
1006 ALIGN_END_ADDR(struct QH, qh_list, 1));
1008 /* Set async. queue head pointer. */
1009 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
1012 * Set up periodic list
1013 * Step 1: Parent QH for all periodic transfers.
1015 ctrl->periodic_schedules = 0;
1016 periodic = &ctrl->periodic_queue;
1017 memset(periodic, 0, sizeof(*periodic));
1018 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1019 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1020 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1022 flush_dcache_range((unsigned long)periodic,
1023 ALIGN_END_ADDR(struct QH, periodic, 1));
1026 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1027 * In particular, device specifications on polling frequency
1028 * are disregarded. Keyboards seem to send NAK/NYet reliably
1029 * when polled with an empty buffer.
1031 * Split Transactions will be spread across microframes using
1032 * S-mask and C-mask.
1034 if (ctrl->periodic_list == NULL)
1035 ctrl->periodic_list = memalign(4096, 1024 * 4);
1037 if (!ctrl->periodic_list)
1039 for (i = 0; i < 1024; i++) {
1040 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1044 flush_dcache_range((unsigned long)ctrl->periodic_list,
1045 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1048 /* Set periodic list base address */
1049 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1050 (unsigned long)ctrl->periodic_list);
1052 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1053 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1054 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1055 /* Port Indicators */
1056 if (HCS_INDICATOR(reg))
1057 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1058 | 0x80, &descriptor.hub.wHubCharacteristics);
1059 /* Port Power Control */
1061 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1062 | 0x01, &descriptor.hub.wHubCharacteristics);
1064 /* Start the host controller. */
1065 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1067 * Philips, Intel, and maybe others need CMD_RUN before the
1068 * root hub will detect new devices (why?); NEC doesn't
1070 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1072 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1074 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1075 /* take control over the ports */
1076 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1078 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1081 /* unblock posted write */
1082 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1084 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1085 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1090 #ifndef CONFIG_DM_USB
1091 int usb_lowlevel_stop(int index)
1093 ehci_shutdown(&ehcic[index]);
1094 return ehci_hcd_stop(index);
1097 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1099 struct ehci_ctrl *ctrl = &ehcic[index];
1104 * Set ops to default_ehci_ops, ehci_hcd_init should call
1105 * ehci_set_controller_priv to change any of these function pointers.
1107 ctrl->ops = default_ehci_ops;
1109 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1112 if (!ctrl->hccr || !ctrl->hcor)
1114 if (init == USB_INIT_DEVICE)
1117 /* EHCI spec section 4.1 */
1118 if (ehci_reset(ctrl))
1121 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1122 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1126 #ifdef CONFIG_USB_EHCI_FARADAY
1127 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1129 rc = ehci_common_init(ctrl, tweaks);
1135 *controller = &ehcic[index];
1140 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1141 void *buffer, int length)
1144 if (usb_pipetype(pipe) != PIPE_BULK) {
1145 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1148 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1151 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1152 void *buffer, int length,
1153 struct devrequest *setup)
1155 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1157 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1158 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1162 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1164 dev->speed = USB_SPEED_HIGH;
1165 return ehci_submit_root(dev, pipe, buffer, length, setup);
1167 return ehci_submit_async(dev, pipe, buffer, length, setup);
1179 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1182 enable_periodic(struct ehci_ctrl *ctrl)
1185 struct ehci_hcor *hcor = ctrl->hcor;
1188 cmd = ehci_readl(&hcor->or_usbcmd);
1190 ehci_writel(&hcor->or_usbcmd, cmd);
1192 ret = handshake((uint32_t *)&hcor->or_usbsts,
1193 STS_PSS, STS_PSS, 100 * 1000);
1195 printf("EHCI failed: timeout when enabling periodic list\n");
1203 disable_periodic(struct ehci_ctrl *ctrl)
1206 struct ehci_hcor *hcor = ctrl->hcor;
1209 cmd = ehci_readl(&hcor->or_usbcmd);
1211 ehci_writel(&hcor->or_usbcmd, cmd);
1213 ret = handshake((uint32_t *)&hcor->or_usbsts,
1214 STS_PSS, 0, 100 * 1000);
1216 printf("EHCI failed: timeout when disabling periodic list\n");
1222 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1223 unsigned long pipe, int queuesize, int elementsize,
1224 void *buffer, int interval)
1226 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1227 struct int_queue *result = NULL;
1231 * Interrupt transfers requiring several transactions are not supported
1232 * because bInterval is ignored.
1234 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1235 * <= PKT_ALIGN if several qTDs are required, while the USB
1236 * specification does not constrain this for interrupt transfers. That
1237 * means that ehci_submit_async() would support interrupt transfers
1238 * requiring several transactions only as long as the transfer size does
1239 * not require more than a single qTD.
1241 if (elementsize > usb_maxpacket(dev, pipe)) {
1242 printf("%s: xfers requiring several transactions are not supported.\n",
1247 debug("Enter create_int_queue\n");
1248 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1249 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1253 /* limit to 4 full pages worth of data -
1254 * we can safely fit them in a single TD,
1255 * no matter the alignment
1257 if (elementsize >= 16384) {
1258 debug("too large elements for interrupt transfers\n");
1262 result = malloc(sizeof(*result));
1264 debug("ehci intr queue: out of memory\n");
1267 result->elementsize = elementsize;
1268 result->pipe = pipe;
1269 result->first = memalign(USB_DMA_MINALIGN,
1270 sizeof(struct QH) * queuesize);
1271 if (!result->first) {
1272 debug("ehci intr queue: out of memory\n");
1275 result->current = result->first;
1276 result->last = result->first + queuesize - 1;
1277 result->tds = memalign(USB_DMA_MINALIGN,
1278 sizeof(struct qTD) * queuesize);
1280 debug("ehci intr queue: out of memory\n");
1283 memset(result->first, 0, sizeof(struct QH) * queuesize);
1284 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1286 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1288 for (i = 0; i < queuesize; i++) {
1289 struct QH *qh = result->first + i;
1290 struct qTD *td = result->tds + i;
1291 void **buf = &qh->buffer;
1293 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1294 if (i == queuesize - 1)
1295 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1297 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1298 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1300 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1301 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1303 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1304 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1305 (usb_pipedevice(pipe) << 0));
1306 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1307 (1 << 0)); /* S-mask: microframe 0 */
1308 if (dev->speed == USB_SPEED_LOW ||
1309 dev->speed == USB_SPEED_FULL) {
1310 /* C-mask: microframes 2-4 */
1311 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1313 ehci_update_endpt2_dev_n_port(dev, qh);
1315 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1316 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1317 debug("communication direction is '%s'\n",
1318 usb_pipein(pipe) ? "in" : "out");
1319 td->qt_token = cpu_to_hc32(
1320 QT_TOKEN_DT(toggle) |
1321 (elementsize << 16) |
1322 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1325 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1327 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1329 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1331 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1333 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1335 *buf = buffer + i * elementsize;
1339 flush_dcache_range((unsigned long)buffer,
1340 ALIGN_END_ADDR(char, buffer,
1341 queuesize * elementsize));
1342 flush_dcache_range((unsigned long)result->first,
1343 ALIGN_END_ADDR(struct QH, result->first,
1345 flush_dcache_range((unsigned long)result->tds,
1346 ALIGN_END_ADDR(struct qTD, result->tds,
1349 if (ctrl->periodic_schedules > 0) {
1350 if (disable_periodic(ctrl) < 0) {
1351 debug("FATAL: periodic should never fail, but did");
1356 /* hook up to periodic list */
1357 struct QH *list = &ctrl->periodic_queue;
1358 result->last->qh_link = list->qh_link;
1359 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1361 flush_dcache_range((unsigned long)result->last,
1362 ALIGN_END_ADDR(struct QH, result->last, 1));
1363 flush_dcache_range((unsigned long)list,
1364 ALIGN_END_ADDR(struct QH, list, 1));
1366 if (enable_periodic(ctrl) < 0) {
1367 debug("FATAL: periodic should never fail, but did");
1370 ctrl->periodic_schedules++;
1372 debug("Exit create_int_queue\n");
1379 free(result->first);
1386 static void *_ehci_poll_int_queue(struct usb_device *dev,
1387 struct int_queue *queue)
1389 struct QH *cur = queue->current;
1391 uint32_t token, toggle;
1392 unsigned long pipe = queue->pipe;
1394 /* depleted queue */
1396 debug("Exit poll_int_queue with completed queue\n");
1400 cur_td = &queue->tds[queue->current - queue->first];
1401 invalidate_dcache_range((unsigned long)cur_td,
1402 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1403 token = hc32_to_cpu(cur_td->qt_token);
1404 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1405 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1409 toggle = QT_TOKEN_GET_DT(token);
1410 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1412 if (!(cur->qh_link & QH_LINK_TERMINATE))
1415 queue->current = NULL;
1417 invalidate_dcache_range((unsigned long)cur->buffer,
1418 ALIGN_END_ADDR(char, cur->buffer,
1419 queue->elementsize));
1421 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1422 token, cur, queue->first);
1426 /* Do not free buffers associated with QHs, they're owned by someone else */
1427 static int _ehci_destroy_int_queue(struct usb_device *dev,
1428 struct int_queue *queue)
1430 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1432 unsigned long timeout;
1434 if (disable_periodic(ctrl) < 0) {
1435 debug("FATAL: periodic should never fail, but did");
1438 ctrl->periodic_schedules--;
1440 struct QH *cur = &ctrl->periodic_queue;
1441 timeout = get_timer(0) + 500; /* abort after 500ms */
1442 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1443 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1444 if (NEXT_QH(cur) == queue->first) {
1445 debug("found candidate. removing from chain\n");
1446 cur->qh_link = queue->last->qh_link;
1447 flush_dcache_range((unsigned long)cur,
1448 ALIGN_END_ADDR(struct QH, cur, 1));
1453 if (get_timer(0) > timeout) {
1454 printf("Timeout destroying interrupt endpoint queue\n");
1460 if (ctrl->periodic_schedules > 0) {
1461 result = enable_periodic(ctrl);
1463 debug("FATAL: periodic should never fail, but did");
1474 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1475 void *buffer, int length, int interval)
1478 struct int_queue *queue;
1479 unsigned long timeout;
1480 int result = 0, ret;
1482 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1483 dev, pipe, buffer, length, interval);
1485 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1489 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1490 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1491 if (get_timer(0) > timeout) {
1492 printf("Timeout poll on interrupt endpoint\n");
1493 result = -ETIMEDOUT;
1497 if (backbuffer != buffer) {
1498 debug("got wrong buffer back (%p instead of %p)\n",
1499 backbuffer, buffer);
1503 ret = _ehci_destroy_int_queue(dev, queue);
1507 /* everything worked out fine */
1511 #ifndef CONFIG_DM_USB
1512 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1513 void *buffer, int length)
1515 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1518 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1519 int length, struct devrequest *setup)
1521 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1524 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1525 void *buffer, int length, int interval)
1527 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
1530 struct int_queue *create_int_queue(struct usb_device *dev,
1531 unsigned long pipe, int queuesize, int elementsize,
1532 void *buffer, int interval)
1534 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1538 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1540 return _ehci_poll_int_queue(dev, queue);
1543 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1545 return _ehci_destroy_int_queue(dev, queue);
1549 #ifdef CONFIG_DM_USB
1550 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1551 unsigned long pipe, void *buffer, int length,
1552 struct devrequest *setup)
1554 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1555 dev->name, udev, udev->dev->name, udev->portnr);
1557 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1560 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1561 unsigned long pipe, void *buffer, int length)
1563 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1564 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1567 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1568 unsigned long pipe, void *buffer, int length,
1571 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1572 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
1575 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1576 struct usb_device *udev, unsigned long pipe, int queuesize,
1577 int elementsize, void *buffer, int interval)
1579 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1580 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1584 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1585 struct int_queue *queue)
1587 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1588 return _ehci_poll_int_queue(udev, queue);
1591 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1592 struct int_queue *queue)
1594 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1595 return _ehci_destroy_int_queue(udev, queue);
1598 static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size)
1601 * EHCD can handle any transfer length as long as there is enough
1602 * free heap space left, hence set the theoretical max number here.
1609 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1610 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1611 uint tweaks, enum usb_init_type init)
1613 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1614 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1617 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1618 dev->name, ctrl, hccr, hcor, init);
1620 if (!ctrl || !hccr || !hcor)
1623 priv->desc_before_addr = true;
1625 ehci_setup_ops(ctrl, ops);
1631 if (ctrl->init == USB_INIT_DEVICE)
1634 ret = ehci_reset(ctrl);
1638 if (ctrl->ops.init_after_reset) {
1639 ret = ctrl->ops.init_after_reset(ctrl);
1644 ret = ehci_common_init(ctrl, tweaks);
1651 debug("%s: failed, ret=%d\n", __func__, ret);
1655 int ehci_deregister(struct udevice *dev)
1657 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1659 if (ctrl->init == USB_INIT_DEVICE)
1662 ehci_shutdown(ctrl);
1667 struct dm_usb_ops ehci_usb_ops = {
1668 .control = ehci_submit_control_msg,
1669 .bulk = ehci_submit_bulk_msg,
1670 .interrupt = ehci_submit_int_msg,
1671 .create_int_queue = ehci_create_int_queue,
1672 .poll_int_queue = ehci_poll_int_queue,
1673 .destroy_int_queue = ehci_destroy_int_queue,
1674 .get_max_xfer_size = ehci_get_max_xfer_size,