3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/mbus.h>
14 #include <asm/arch/cpu.h>
16 #if defined(CONFIG_KIRKWOOD)
17 #include <asm/arch/soc.h>
18 #elif defined(CONFIG_ORION5X)
19 #include <asm/arch/orion5x.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
25 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
26 #define USB_TARGET_DRAM 0x0
29 * USB 2.0 Bridge Address Decoding registers setup
31 #ifdef CONFIG_ARMADA_XP
33 #define MVUSB0_BASE MVEBU_USB20_BASE
36 * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
37 * to the common mvebu archticture including the mbus setup, this
38 * will be the only function needed to configure the access windows
40 static void usb_brg_adrdec_setup(void)
42 const struct mbus_dram_target_info *dram;
45 dram = mvebu_mbus_dram_info();
47 for (i = 0; i < 4; i++) {
48 writel(0, MVUSB0_BASE + USB_WINDOW_CTRL(i));
49 writel(0, MVUSB0_BASE + USB_WINDOW_BASE(i));
52 for (i = 0; i < dram->num_cs; i++) {
53 const struct mbus_dram_window *cs = dram->cs + i;
55 /* Write size, attributes and target id to control register */
56 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
57 (dram->mbus_dram_target_id << 4) | 1,
58 MVUSB0_BASE + USB_WINDOW_CTRL(i));
60 /* Write base address to base register */
61 writel(cs->base, MVUSB0_BASE + USB_WINDOW_BASE(i));
65 static void usb_brg_adrdec_setup(void)
68 u32 size, base, attrib;
70 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
72 /* Enable DRAM bank */
75 attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
78 attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
81 attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
84 attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
87 /* invalide bank, disable access */
92 size = gd->bd->bi_dram[i].size;
93 base = gd->bd->bi_dram[i].start;
94 if ((size) && (attrib))
95 writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
96 attrib, MVCPU_WIN_ENABLE),
97 MVUSB0_BASE + USB_WINDOW_CTRL(i));
99 writel(MVCPU_WIN_DISABLE,
100 MVUSB0_BASE + USB_WINDOW_CTRL(i));
102 writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
108 * Create the appropriate control structures to manage
109 * a new EHCI host controller.
111 int ehci_hcd_init(int index, enum usb_init_type init,
112 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
114 usb_brg_adrdec_setup();
116 *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
117 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
118 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
120 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
121 (uint32_t)*hccr, (uint32_t)*hcor,
122 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
128 * Destroy the appropriate control structures corresponding
129 * the the EHCI host controller.
131 int ehci_hcd_stop(int index)