3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
29 #include "ehci-core.h"
30 #include <asm/arch/cpu.h>
32 #if defined(CONFIG_KIRKWOOD)
33 #include <asm/arch/kirkwood.h>
34 #elif defined(CONFIG_ORION5X)
35 #include <asm/arch/orion5x.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 #define rdl(off) readl(MVUSB0_BASE + (off))
41 #define wrl(off, val) writel((val), MVUSB0_BASE + (off))
43 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
44 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
45 #define USB_TARGET_DRAM 0x0
48 * USB 2.0 Bridge Address Decoding registers setup
50 static void usb_brg_adrdec_setup(void)
53 u32 size, base, attrib;
55 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
57 /* Enable DRAM bank */
60 attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
63 attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
66 attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
69 attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
72 /* invalide bank, disable access */
77 size = gd->bd->bi_dram[i].size;
78 base = gd->bd->bi_dram[i].start;
79 if ((size) && (attrib))
80 wrl(USB_WINDOW_CTRL(i),
81 MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
82 attrib, MVCPU_WIN_ENABLE));
84 wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
86 wrl(USB_WINDOW_BASE(i), base);
91 * Create the appropriate control structures to manage
92 * a new EHCI host controller.
94 int ehci_hcd_init(void)
96 usb_brg_adrdec_setup();
98 hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
99 hcor = (struct ehci_hcor *)((uint32_t) hccr
100 + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
102 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
103 (uint32_t)hccr, (uint32_t)hcor,
104 (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
110 * Destroy the appropriate control structures corresponding
111 * the the EHCI host controller.
113 int ehci_hcd_stop(void)