3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/mbus.h>
14 #include <asm/arch/cpu.h>
17 #if defined(CONFIG_KIRKWOOD)
18 #include <asm/arch/soc.h>
19 #elif defined(CONFIG_ORION5X)
20 #include <asm/arch/orion5x.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
26 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
27 #define USB_TARGET_DRAM 0x0
30 * USB 2.0 Bridge Address Decoding registers setup
34 struct ehci_mvebu_priv {
35 struct ehci_ctrl ehci;
40 * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
41 * to the common mvebu archticture including the mbus setup, this
42 * will be the only function needed to configure the access windows
44 static void usb_brg_adrdec_setup(u32 base)
46 const struct mbus_dram_target_info *dram;
49 dram = mvebu_mbus_dram_info();
51 for (i = 0; i < 4; i++) {
52 writel(0, base + USB_WINDOW_CTRL(i));
53 writel(0, base + USB_WINDOW_BASE(i));
56 for (i = 0; i < dram->num_cs; i++) {
57 const struct mbus_dram_window *cs = dram->cs + i;
59 /* Write size, attributes and target id to control register */
60 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
61 (dram->mbus_dram_target_id << 4) | 1,
62 base + USB_WINDOW_CTRL(i));
64 /* Write base address to base register */
65 writel(cs->base, base + USB_WINDOW_BASE(i));
69 static int ehci_mvebu_probe(struct udevice *dev)
71 struct ehci_mvebu_priv *priv = dev_get_priv(dev);
72 struct ehci_hccr *hccr;
73 struct ehci_hcor *hcor;
76 * Get the base address for EHCI controller from the device node
78 priv->hcd_base = dev_get_addr(dev);
79 if (priv->hcd_base == FDT_ADDR_T_NONE) {
80 debug("Can't get the EHCI register base address\n");
84 usb_brg_adrdec_setup(priv->hcd_base);
86 hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
87 hcor = (struct ehci_hcor *)
88 ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
90 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
92 (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
94 return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
97 static const struct udevice_id ehci_usb_ids[] = {
98 { .compatible = "marvell,orion-ehci", },
102 U_BOOT_DRIVER(ehci_mvebu) = {
103 .name = "ehci_mvebu",
105 .of_match = ehci_usb_ids,
106 .probe = ehci_mvebu_probe,
107 .remove = ehci_deregister,
108 .ops = &ehci_usb_ops,
109 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
110 .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv),
111 .flags = DM_FLAG_ALLOC_PRIV_DMA,
115 #define MVUSB_BASE(port) MVUSB0_BASE
117 static void usb_brg_adrdec_setup(int index)
120 u32 size, base, attrib;
122 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
124 /* Enable DRAM bank */
127 attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
130 attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
133 attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
136 attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
139 /* invalide bank, disable access */
144 size = gd->bd->bi_dram[i].size;
145 base = gd->bd->bi_dram[i].start;
146 if ((size) && (attrib))
147 writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
148 attrib, MVCPU_WIN_ENABLE),
149 MVUSB0_BASE + USB_WINDOW_CTRL(i));
151 writel(MVCPU_WIN_DISABLE,
152 MVUSB0_BASE + USB_WINDOW_CTRL(i));
154 writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
159 * Create the appropriate control structures to manage
160 * a new EHCI host controller.
162 int ehci_hcd_init(int index, enum usb_init_type init,
163 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
165 usb_brg_adrdec_setup(index);
167 *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
168 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
169 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
171 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
172 (uint32_t)*hccr, (uint32_t)*hcor,
173 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
179 * Destroy the appropriate control structures corresponding
180 * the the EHCI host controller.
182 int ehci_hcd_stop(int index)
187 #endif /* CONFIG_DM_USB */