2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
13 #include <usb/ehci-ci.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/imx-common/iomux-v3.h>
21 #define USB_OTGREGS_OFFSET 0x000
22 #define USB_H1REGS_OFFSET 0x200
23 #define USB_H2REGS_OFFSET 0x400
24 #define USB_H3REGS_OFFSET 0x600
25 #define USB_OTHERREGS_OFFSET 0x800
27 #define USB_H1_CTRL_OFFSET 0x04
29 #define USBPHY_CTRL 0x00000030
30 #define USBPHY_CTRL_SET 0x00000034
31 #define USBPHY_CTRL_CLR 0x00000038
32 #define USBPHY_CTRL_TOG 0x0000003c
34 #define USBPHY_PWD 0x00000000
35 #define USBPHY_CTRL_SFTRST 0x80000000
36 #define USBPHY_CTRL_CLKGATE 0x40000000
37 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
38 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
39 #define USBPHY_CTRL_OTG_ID 0x08000000
41 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
42 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
44 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
45 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
46 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
47 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
49 #define USBNC_OFFSET 0x200
50 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
51 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
52 #define UCTRL_PM (1 << 9) /* OTG Power Mask */
53 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
54 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
57 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
58 #define UCMD_RESET (1 << 1) /* controller reset */
60 #if defined(CONFIG_MX6)
61 static const unsigned phy_bases[] = {
66 static void usb_internal_phy_clock_gate(int index, int on)
68 void __iomem *phy_reg;
70 if (index >= ARRAY_SIZE(phy_bases))
73 phy_reg = (void __iomem *)phy_bases[index];
74 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
75 writel(USBPHY_CTRL_CLKGATE, phy_reg);
78 static void usb_power_config(int index)
80 struct anatop_regs __iomem *anatop =
81 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
82 void __iomem *chrg_detect;
83 void __iomem *pll_480_ctrl_clr;
84 void __iomem *pll_480_ctrl_set;
88 chrg_detect = &anatop->usb1_chrg_detect;
89 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
90 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
93 chrg_detect = &anatop->usb2_chrg_detect;
94 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
95 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
101 * Some phy and power's special controls
102 * 1. The external charger detector needs to be disabled
103 * or the signal at DP will be poor
104 * 2. The PLL's power and output to usb
105 * is totally controlled by IC, so the Software only needs
106 * to enable them at initializtion.
108 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
109 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
112 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
115 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
116 ANADIG_USB2_PLL_480_CTRL_POWER |
117 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
121 /* Return 0 : host node, <>0 : device mode */
122 static int usb_phy_enable(int index, struct usb_ehci *ehci)
124 void __iomem *phy_reg;
125 void __iomem *phy_ctrl;
126 void __iomem *usb_cmd;
129 if (index >= ARRAY_SIZE(phy_bases))
132 phy_reg = (void __iomem *)phy_bases[index];
133 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
134 usb_cmd = (void __iomem *)&ehci->usbcmd;
136 /* Stop then Reset */
137 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
138 ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000,
143 setbits_le32(usb_cmd, UCMD_RESET);
144 ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false);
148 /* Reset USBPHY module */
149 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
152 /* Remove CLKGATE and SFTRST */
153 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
156 /* Power up the PHY */
157 writel(0, phy_reg + USBPHY_PWD);
158 /* enable FS/LS device */
159 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
160 USBPHY_CTRL_ENUTMILEVEL3);
165 int usb_phy_mode(int port)
167 void __iomem *phy_reg;
168 void __iomem *phy_ctrl;
171 phy_reg = (void __iomem *)phy_bases[port];
172 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
174 val = readl(phy_ctrl);
176 if (val & USBPHY_CTRL_OTG_ID)
177 return USB_INIT_DEVICE;
179 return USB_INIT_HOST;
182 /* Base address for this IP block is 0x02184800 */
184 u32 ctrl[4]; /* otg/host1-3 */
190 #elif defined(CONFIG_MX7)
205 static void usb_power_config(int index)
207 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
208 (0x10000 * index) + USBNC_OFFSET);
209 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
212 * Clear the ACAENB to enable usb_otg_id detection,
213 * otherwise it is the ACA detection enabled.
215 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
218 int usb_phy_mode(int port)
220 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
221 (0x10000 * port) + USBNC_OFFSET);
222 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
227 if (val & USBNC_PHYSTATUS_ID_DIG)
228 return USB_INIT_DEVICE;
230 return USB_INIT_HOST;
234 static void usb_oc_config(int index)
236 #if defined(CONFIG_MX6)
237 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
238 USB_OTHERREGS_OFFSET);
239 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
240 #elif defined(CONFIG_MX7)
241 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
242 (0x10000 * index) + USBNC_OFFSET);
243 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
246 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
247 /* mx6qarm2 seems to required a different setting*/
248 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
250 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
253 #if defined(CONFIG_MX6)
254 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
255 #elif defined(CONFIG_MX7)
256 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
261 * board_usb_phy_mode - override usb phy mode
262 * @port: usb host/otg port
264 * Target board specific, override usb_phy_mode.
265 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
266 * left disconnected in this case usb_phy_mode will not be able to identify
267 * the phy mode that usb port is used.
268 * Machine file overrides board_usb_phy_mode.
270 * Return: USB_INIT_DEVICE or USB_INIT_HOST
272 int __weak board_usb_phy_mode(int port)
274 return usb_phy_mode(port);
278 * board_ehci_hcd_init - set usb vbus voltage
279 * @port: usb otg port
281 * Target board specific, setup iomux pad to setup supply vbus voltage
282 * for usb otg port. Machine board file overrides board_ehci_hcd_init
286 int __weak board_ehci_hcd_init(int port)
292 * board_ehci_power - enables/disables usb vbus voltage
293 * @port: usb otg port
294 * @on: on/off vbus voltage
296 * Enables/disables supply vbus voltage for usb otg port.
297 * Machine board file overrides board_ehci_power
301 int __weak board_ehci_power(int port, int on)
306 int ehci_hcd_init(int index, enum usb_init_type init,
307 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
309 enum usb_init_type type;
310 #if defined(CONFIG_MX6)
311 u32 controller_spacing = 0x200;
312 #elif defined(CONFIG_MX7)
313 u32 controller_spacing = 0x10000;
315 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
316 (controller_spacing * index));
321 enable_usboh3_clk(1);
324 /* Do board specific initialization */
325 ret = board_ehci_hcd_init(index);
329 usb_power_config(index);
330 usb_oc_config(index);
332 #if defined(CONFIG_MX6)
333 usb_internal_phy_clock_gate(index, 1);
334 usb_phy_enable(index, ehci);
336 type = board_usb_phy_mode(index);
338 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
339 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
340 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
342 if ((type == init) || (type == USB_INIT_DEVICE))
343 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
346 if (type == USB_INIT_DEVICE)
349 setbits_le32(&ehci->usbmode, CM_HOST);
350 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
351 setbits_le32(&ehci->portsc, USB_EN);
358 int ehci_hcd_stop(int index)