2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 #include <linux/compiler.h>
20 #include <usb/ehci-fsl.h>
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/imx-common/iomux-v3.h>
28 #define USB_OTGREGS_OFFSET 0x000
29 #define USB_H1REGS_OFFSET 0x200
30 #define USB_H2REGS_OFFSET 0x400
31 #define USB_H3REGS_OFFSET 0x600
32 #define USB_OTHERREGS_OFFSET 0x800
34 #define USB_H1_CTRL_OFFSET 0x04
36 #define USBPHY_CTRL 0x00000030
37 #define USBPHY_CTRL_SET 0x00000034
38 #define USBPHY_CTRL_CLR 0x00000038
39 #define USBPHY_CTRL_TOG 0x0000003c
41 #define USBPHY_PWD 0x00000000
42 #define USBPHY_CTRL_SFTRST 0x80000000
43 #define USBPHY_CTRL_CLKGATE 0x40000000
44 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
45 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
47 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
48 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
50 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
51 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
52 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
53 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
56 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
57 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
60 #define UH1_USBCMD_OFFSET 0x140
61 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
62 #define UCMD_RESET (1 << 1) /* controller reset */
64 static void usbh1_internal_phy_clock_gate(int on)
66 void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
68 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
69 __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
72 static void usbh1_power_config(void)
74 struct anatop_regs __iomem *anatop =
75 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
77 * Some phy and power's special controls for host1
78 * 1. The external charger detector needs to be disabled
79 * or the signal at DP will be poor
80 * 2. The PLL's power and output to usb for host 1
81 * is totally controlled by IC, so the Software only needs
82 * to enable them at initializtion.
84 __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
85 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
86 &anatop->usb2_chrg_detect);
88 __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
89 &anatop->usb2_pll_480_ctrl_clr);
91 __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
92 ANADIG_USB2_PLL_480_CTRL_POWER |
93 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
94 &anatop->usb2_pll_480_ctrl_set);
97 static int usbh1_phy_enable(void)
99 void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
100 void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
101 void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR +
106 /* Stop then Reset */
107 val = __raw_readl(usb_cmd);
108 val &= ~UCMD_RUN_STOP;
109 __raw_writel(val, usb_cmd);
110 while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
113 val = __raw_readl(usb_cmd);
115 __raw_writel(val, usb_cmd);
116 while (__raw_readl(usb_cmd) & UCMD_RESET)
119 /* Reset USBPHY module */
120 val = __raw_readl(phy_ctrl);
121 val |= USBPHY_CTRL_SFTRST;
122 __raw_writel(val, phy_ctrl);
125 /* Remove CLKGATE and SFTRST */
126 val = __raw_readl(phy_ctrl);
127 val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
128 __raw_writel(val, phy_ctrl);
131 /* Power up the PHY */
132 __raw_writel(0, phy_reg + USBPHY_PWD);
133 /* enable FS/LS device */
134 val = __raw_readl(phy_reg + USBPHY_CTRL);
135 val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
136 __raw_writel(val, phy_reg + USBPHY_CTRL);
141 static void usbh1_oc_config(void)
143 void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
144 void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
147 val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
148 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
149 /* mx6qarm2 seems to required a different setting*/
150 val &= ~UCTRL_OVER_CUR_POL;
152 val |= UCTRL_OVER_CUR_POL;
154 __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
156 val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
157 val |= UCTRL_OVER_CUR_DIS;
158 __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
161 int __weak board_ehci_hcd_init(int port)
166 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
168 struct usb_ehci *ehci;
170 enable_usboh3_clk(1);
173 /* Do board specific initialization */
174 board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
176 #if CONFIG_MXC_USB_PORT == 1
178 usbh1_power_config();
180 usbh1_internal_phy_clock_gate(1);
183 #error "MXC USB port not yet supported"
186 ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
187 (0x200 * CONFIG_MXC_USB_PORT));
188 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
189 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
190 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
191 setbits_le32(&ehci->usbmode, CM_HOST);
193 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
194 setbits_le32(&ehci->portsc, USB_EN);
201 int ehci_hcd_stop(int index)