2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
12 #include <usb/ehci-fsl.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/imx-common/iomux-v3.h>
20 #define USB_OTGREGS_OFFSET 0x000
21 #define USB_H1REGS_OFFSET 0x200
22 #define USB_H2REGS_OFFSET 0x400
23 #define USB_H3REGS_OFFSET 0x600
24 #define USB_OTHERREGS_OFFSET 0x800
26 #define USB_H1_CTRL_OFFSET 0x04
28 #define USBPHY_CTRL 0x00000030
29 #define USBPHY_CTRL_SET 0x00000034
30 #define USBPHY_CTRL_CLR 0x00000038
31 #define USBPHY_CTRL_TOG 0x0000003c
33 #define USBPHY_PWD 0x00000000
34 #define USBPHY_CTRL_SFTRST 0x80000000
35 #define USBPHY_CTRL_CLKGATE 0x40000000
36 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
37 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
38 #define USBPHY_CTRL_OTG_ID 0x08000000
40 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
41 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
43 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
44 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
45 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
46 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
49 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
50 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
53 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
54 #define UCMD_RESET (1 << 1) /* controller reset */
56 static const unsigned phy_bases[] = {
61 static void usb_internal_phy_clock_gate(int index, int on)
63 void __iomem *phy_reg;
65 if (index >= ARRAY_SIZE(phy_bases))
68 phy_reg = (void __iomem *)phy_bases[index];
69 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
70 writel(USBPHY_CTRL_CLKGATE, phy_reg);
73 static void usb_power_config(int index)
75 struct anatop_regs __iomem *anatop =
76 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
77 void __iomem *chrg_detect;
78 void __iomem *pll_480_ctrl_clr;
79 void __iomem *pll_480_ctrl_set;
83 chrg_detect = &anatop->usb1_chrg_detect;
84 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
85 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
88 chrg_detect = &anatop->usb2_chrg_detect;
89 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
90 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
96 * Some phy and power's special controls
97 * 1. The external charger detector needs to be disabled
98 * or the signal at DP will be poor
99 * 2. The PLL's power and output to usb
100 * is totally controlled by IC, so the Software only needs
101 * to enable them at initializtion.
103 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
104 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
107 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
110 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
111 ANADIG_USB2_PLL_480_CTRL_POWER |
112 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
116 /* Return 0 : host node, <>0 : device mode */
117 static int usb_phy_enable(int index, struct usb_ehci *ehci)
119 void __iomem *phy_reg;
120 void __iomem *phy_ctrl;
121 void __iomem *usb_cmd;
123 if (index >= ARRAY_SIZE(phy_bases))
126 phy_reg = (void __iomem *)phy_bases[index];
127 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
128 usb_cmd = (void __iomem *)&ehci->usbcmd;
130 /* Stop then Reset */
131 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
132 while (readl(usb_cmd) & UCMD_RUN_STOP)
135 setbits_le32(usb_cmd, UCMD_RESET);
136 while (readl(usb_cmd) & UCMD_RESET)
139 /* Reset USBPHY module */
140 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
143 /* Remove CLKGATE and SFTRST */
144 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
147 /* Power up the PHY */
148 writel(0, phy_reg + USBPHY_PWD);
149 /* enable FS/LS device */
150 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
151 USBPHY_CTRL_ENUTMILEVEL3);
156 /* Base address for this IP block is 0x02184800 */
158 u32 ctrl[4]; /* otg/host1-3 */
165 static void usb_oc_config(int index)
167 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
168 USB_OTHERREGS_OFFSET);
169 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
171 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
172 /* mx6qarm2 seems to required a different setting*/
173 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
175 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
178 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
181 int usb_phy_mode(int port)
183 void __iomem *phy_reg;
184 void __iomem *phy_ctrl;
187 phy_reg = (void __iomem *)phy_bases[port];
188 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
190 val = readl(phy_ctrl);
192 if (val & USBPHY_CTRL_OTG_ID)
193 return USB_INIT_DEVICE;
195 return USB_INIT_HOST;
199 * board_ehci_hcd_init - override usb phy mode
200 * @port: usb host/otg port
202 * Target board specific, override usb_phy_mode.
203 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
204 * left disconnected in this case usb_phy_mode will not be able to identify
205 * the phy mode that usb port is used.
206 * Machine file overrides board_usb_phy_mode.
208 * Return: USB_INIT_DEVICE or USB_INIT_HOST
210 int __weak board_usb_phy_mode(int port)
212 return usb_phy_mode(port);
216 * board_ehci_hcd_init - set usb vbus voltage
217 * @port: usb otg port
219 * Target board specific, setup iomux pad to setup supply vbus voltage
220 * for usb otg port. Machine board file overrides board_ehci_hcd_init
224 int __weak board_ehci_hcd_init(int port)
230 * board_ehci_power - enables/disables usb vbus voltage
231 * @port: usb otg port
232 * @on: on/off vbus voltage
234 * Enables/disables supply vbus voltage for usb otg port.
235 * Machine board file overrides board_ehci_power
239 int __weak board_ehci_power(int port, int on)
244 int ehci_hcd_init(int index, enum usb_init_type init,
245 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
247 enum usb_init_type type;
248 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
253 enable_usboh3_clk(1);
256 /* Do board specific initialization */
257 board_ehci_hcd_init(index);
259 usb_power_config(index);
260 usb_oc_config(index);
261 usb_internal_phy_clock_gate(index, 1);
262 usb_phy_enable(index, ehci);
263 type = board_usb_phy_mode(index);
265 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
266 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
267 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
269 if ((type == init) || (type == USB_INIT_DEVICE))
270 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
273 if (type == USB_INIT_DEVICE)
275 setbits_le32(&ehci->usbmode, CM_HOST);
276 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
277 setbits_le32(&ehci->portsc, USB_EN);
284 int ehci_hcd_stop(int index)