2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
13 #include <usb/ehci-ci.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/sys_proto.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define USB_OTGREGS_OFFSET 0x000
26 #define USB_H1REGS_OFFSET 0x200
27 #define USB_H2REGS_OFFSET 0x400
28 #define USB_H3REGS_OFFSET 0x600
29 #define USB_OTHERREGS_OFFSET 0x800
31 #define USB_H1_CTRL_OFFSET 0x04
33 #define USBPHY_CTRL 0x00000030
34 #define USBPHY_CTRL_SET 0x00000034
35 #define USBPHY_CTRL_CLR 0x00000038
36 #define USBPHY_CTRL_TOG 0x0000003c
38 #define USBPHY_PWD 0x00000000
39 #define USBPHY_CTRL_SFTRST 0x80000000
40 #define USBPHY_CTRL_CLKGATE 0x40000000
41 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
42 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
43 #define USBPHY_CTRL_OTG_ID 0x08000000
45 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
46 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
48 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
49 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
50 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
51 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
53 #define USBNC_OFFSET 0x200
54 #define USBNC_PHY_STATUS_OFFSET 0x23C
55 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
56 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
57 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
58 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
59 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
62 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
63 #define UCMD_RESET (1 << 1) /* controller reset */
65 #if defined(CONFIG_MX6)
66 static const unsigned phy_bases[] = {
71 static void usb_internal_phy_clock_gate(int index, int on)
73 void __iomem *phy_reg;
75 if (index >= ARRAY_SIZE(phy_bases))
78 phy_reg = (void __iomem *)phy_bases[index];
79 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
80 writel(USBPHY_CTRL_CLKGATE, phy_reg);
83 static void usb_power_config(int index)
85 struct anatop_regs __iomem *anatop =
86 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
87 void __iomem *chrg_detect;
88 void __iomem *pll_480_ctrl_clr;
89 void __iomem *pll_480_ctrl_set;
93 chrg_detect = &anatop->usb1_chrg_detect;
94 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
95 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
98 chrg_detect = &anatop->usb2_chrg_detect;
99 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
100 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
106 * Some phy and power's special controls
107 * 1. The external charger detector needs to be disabled
108 * or the signal at DP will be poor
109 * 2. The PLL's power and output to usb
110 * is totally controlled by IC, so the Software only needs
111 * to enable them at initializtion.
113 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
114 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
117 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
120 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
121 ANADIG_USB2_PLL_480_CTRL_POWER |
122 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
126 /* Return 0 : host node, <>0 : device mode */
127 static int usb_phy_enable(int index, struct usb_ehci *ehci)
129 void __iomem *phy_reg;
130 void __iomem *phy_ctrl;
131 void __iomem *usb_cmd;
134 if (index >= ARRAY_SIZE(phy_bases))
137 phy_reg = (void __iomem *)phy_bases[index];
138 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
139 usb_cmd = (void __iomem *)&ehci->usbcmd;
141 /* Stop then Reset */
142 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
143 ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000,
148 setbits_le32(usb_cmd, UCMD_RESET);
149 ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false);
153 /* Reset USBPHY module */
154 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
157 /* Remove CLKGATE and SFTRST */
158 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
161 /* Power up the PHY */
162 writel(0, phy_reg + USBPHY_PWD);
163 /* enable FS/LS device */
164 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
165 USBPHY_CTRL_ENUTMILEVEL3);
170 int usb_phy_mode(int port)
172 void __iomem *phy_reg;
173 void __iomem *phy_ctrl;
176 phy_reg = (void __iomem *)phy_bases[port];
177 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
179 val = readl(phy_ctrl);
181 if (val & USBPHY_CTRL_OTG_ID)
182 return USB_INIT_DEVICE;
184 return USB_INIT_HOST;
187 /* Base address for this IP block is 0x02184800 */
189 u32 ctrl[4]; /* otg/host1-3 */
195 #elif defined(CONFIG_MX7)
210 static void usb_power_config(int index)
212 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
213 (0x10000 * index) + USBNC_OFFSET);
214 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
215 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
218 * Clear the ACAENB to enable usb_otg_id detection,
219 * otherwise it is the ACA detection enabled.
221 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
223 /* Set power polarity to high active */
224 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
225 setbits_le32(ctrl, UCTRL_PWR_POL);
227 clrbits_le32(ctrl, UCTRL_PWR_POL);
231 int usb_phy_mode(int port)
233 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
234 (0x10000 * port) + USBNC_OFFSET);
235 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
240 if (val & USBNC_PHYSTATUS_ID_DIG)
241 return USB_INIT_DEVICE;
243 return USB_INIT_HOST;
247 static void usb_oc_config(int index)
249 #if defined(CONFIG_MX6)
250 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
251 USB_OTHERREGS_OFFSET);
252 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
253 #elif defined(CONFIG_MX7)
254 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
255 (0x10000 * index) + USBNC_OFFSET);
256 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
259 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
260 /* mx6qarm2 seems to required a different setting*/
261 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
263 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
266 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
270 * board_usb_phy_mode - override usb phy mode
271 * @port: usb host/otg port
273 * Target board specific, override usb_phy_mode.
274 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
275 * left disconnected in this case usb_phy_mode will not be able to identify
276 * the phy mode that usb port is used.
277 * Machine file overrides board_usb_phy_mode.
279 * Return: USB_INIT_DEVICE or USB_INIT_HOST
281 int __weak board_usb_phy_mode(int port)
283 return usb_phy_mode(port);
287 * board_ehci_hcd_init - set usb vbus voltage
288 * @port: usb otg port
290 * Target board specific, setup iomux pad to setup supply vbus voltage
291 * for usb otg port. Machine board file overrides board_ehci_hcd_init
295 int __weak board_ehci_hcd_init(int port)
301 * board_ehci_power - enables/disables usb vbus voltage
302 * @port: usb otg port
303 * @on: on/off vbus voltage
305 * Enables/disables supply vbus voltage for usb otg port.
306 * Machine board file overrides board_ehci_power
310 int __weak board_ehci_power(int port, int on)
315 int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
319 enable_usboh3_clk(1);
322 /* Do board specific initialization */
323 ret = board_ehci_hcd_init(index);
327 usb_power_config(index);
328 usb_oc_config(index);
330 #if defined(CONFIG_MX6)
331 usb_internal_phy_clock_gate(index, 1);
332 usb_phy_enable(index, ehci);
338 #ifndef CONFIG_DM_USB
339 int ehci_hcd_init(int index, enum usb_init_type init,
340 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
342 enum usb_init_type type;
343 #if defined(CONFIG_MX6)
344 u32 controller_spacing = 0x200;
345 #elif defined(CONFIG_MX7)
346 u32 controller_spacing = 0x10000;
348 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
349 (controller_spacing * index));
355 ret = ehci_mx6_common_init(ehci, index);
359 type = board_usb_phy_mode(index);
362 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
363 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
364 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
367 if ((type == init) || (type == USB_INIT_DEVICE))
368 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
371 if (type == USB_INIT_DEVICE)
374 setbits_le32(&ehci->usbmode, CM_HOST);
375 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
376 setbits_le32(&ehci->portsc, USB_EN);
383 int ehci_hcd_stop(int index)
388 struct ehci_mx6_priv_data {
389 struct ehci_ctrl ctrl;
390 struct usb_ehci *ehci;
391 enum usb_init_type init_type;
395 static int mx6_init_after_reset(struct ehci_ctrl *dev)
397 struct ehci_mx6_priv_data *priv = dev->priv;
398 enum usb_init_type type = priv->init_type;
399 struct usb_ehci *ehci = priv->ehci;
402 ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
406 board_ehci_power(priv->portnr, (type == USB_INIT_DEVICE) ? 0 : 1);
408 if (type == USB_INIT_DEVICE)
411 setbits_le32(&ehci->usbmode, CM_HOST);
412 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
413 setbits_le32(&ehci->portsc, USB_EN);
420 static const struct ehci_ops mx6_ehci_ops = {
421 .init_after_reset = mx6_init_after_reset
424 static int ehci_usb_phy_mode(struct udevice *dev)
426 struct usb_platdata *plat = dev_get_platdata(dev);
427 void *__iomem addr = (void *__iomem)dev_get_addr(dev);
428 void *__iomem phy_ctrl, *__iomem phy_status;
429 const void *blob = gd->fdt_blob;
430 int offset = dev->of_offset, phy_off;
434 * About fsl,usbphy, Refer to
435 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
438 phy_off = fdtdec_lookup_phandle(blob,
444 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
446 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
449 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
450 val = readl(phy_ctrl);
452 if (val & USBPHY_CTRL_OTG_ID)
453 plat->init_type = USB_INIT_DEVICE;
455 plat->init_type = USB_INIT_HOST;
456 } else if (is_mx7()) {
457 phy_status = (void __iomem *)(addr +
458 USBNC_PHY_STATUS_OFFSET);
459 val = readl(phy_status);
461 if (val & USBNC_PHYSTATUS_ID_DIG)
462 plat->init_type = USB_INIT_DEVICE;
464 plat->init_type = USB_INIT_HOST;
472 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
474 struct usb_platdata *plat = dev_get_platdata(dev);
477 mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "dr_mode", NULL);
479 if (strcmp(mode, "peripheral") == 0)
480 plat->init_type = USB_INIT_DEVICE;
481 else if (strcmp(mode, "host") == 0)
482 plat->init_type = USB_INIT_HOST;
483 else if (strcmp(mode, "otg") == 0)
484 return ehci_usb_phy_mode(dev);
491 return ehci_usb_phy_mode(dev);
494 static int ehci_usb_probe(struct udevice *dev)
496 struct usb_platdata *plat = dev_get_platdata(dev);
497 struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev);
498 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
499 struct ehci_hccr *hccr;
500 struct ehci_hcor *hcor;
504 priv->portnr = dev->seq;
505 priv->init_type = plat->init_type;
507 ret = ehci_mx6_common_init(ehci, priv->portnr);
511 board_ehci_power(priv->portnr, (priv->init_type == USB_INIT_DEVICE) ? 0 : 1);
513 if (priv->init_type == USB_INIT_HOST) {
514 setbits_le32(&ehci->usbmode, CM_HOST);
515 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
516 setbits_le32(&ehci->portsc, USB_EN);
521 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
522 hcor = (struct ehci_hcor *)((uint32_t)hccr +
523 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
525 return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
528 static const struct udevice_id mx6_usb_ids[] = {
529 { .compatible = "fsl,imx27-usb" },
533 U_BOOT_DRIVER(usb_mx6) = {
536 .of_match = mx6_usb_ids,
537 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
538 .probe = ehci_usb_probe,
539 .remove = ehci_deregister,
540 .ops = &ehci_usb_ops,
541 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
542 .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
543 .flags = DM_FLAG_ALLOC_PRIV_DMA,