2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <asm/arch/imx-regs.h>
24 #include <usb/ehci-fsl.h>
29 #define USBCTRL_OTGBASE_OFFSET 0x600
31 #define MX25_OTG_SIC_SHIFT 29
32 #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
33 #define MX25_OTG_PM_BIT (1 << 24)
34 #define MX25_OTG_PP_BIT (1 << 11)
35 #define MX25_OTG_OCPOL_BIT (1 << 3)
37 #define MX25_H1_SIC_SHIFT 21
38 #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
39 #define MX25_H1_PP_BIT (1 << 18)
40 #define MX25_H1_PM_BIT (1 << 16)
41 #define MX25_H1_IPPUE_UP_BIT (1 << 7)
42 #define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
43 #define MX25_H1_TLL_BIT (1 << 5)
44 #define MX25_H1_USBTE_BIT (1 << 4)
45 #define MX25_H1_OCPOL_BIT (1 << 2)
47 #define MX31_OTG_SIC_SHIFT 29
48 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
49 #define MX31_OTG_PM_BIT (1 << 24)
51 #define MX31_H2_SIC_SHIFT 21
52 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
53 #define MX31_H2_PM_BIT (1 << 16)
54 #define MX31_H2_DT_BIT (1 << 5)
56 #define MX31_H1_SIC_SHIFT 13
57 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
58 #define MX31_H1_PM_BIT (1 << 8)
59 #define MX31_H1_DT_BIT (1 << 4)
61 #define MX35_OTG_SIC_SHIFT 29
62 #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
63 #define MX35_OTG_PM_BIT (1 << 24)
64 #define MX35_OTG_PP_BIT (1 << 11)
65 #define MX35_OTG_OCPOL_BIT (1 << 3)
67 #define MX35_H1_SIC_SHIFT 21
68 #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
69 #define MX35_H1_PP_BIT (1 << 18)
70 #define MX35_H1_PM_BIT (1 << 16)
71 #define MX35_H1_IPPUE_UP_BIT (1 << 7)
72 #define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
73 #define MX35_H1_TLL_BIT (1 << 5)
74 #define MX35_H1_USBTE_BIT (1 << 4)
75 #define MX35_H1_OCPOL_BIT (1 << 2)
77 static int mxc_set_usbcontrol(int port, unsigned int flags)
81 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
82 #if defined(CONFIG_MX25)
84 case 0: /* OTG port */
85 v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
87 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
89 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
92 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
95 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
96 v |= MX25_OTG_OCPOL_BIT;
100 v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
101 MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
102 MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
103 MX25_H1_IPPUE_UP_BIT);
104 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
106 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
109 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
112 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
113 v |= MX25_H1_OCPOL_BIT;
115 if (!(flags & MXC_EHCI_TTL_ENABLED))
116 v |= MX25_H1_TLL_BIT;
118 if (flags & MXC_EHCI_INTERNAL_PHY)
119 v |= MX25_H1_USBTE_BIT;
121 if (flags & MXC_EHCI_IPPUE_DOWN)
122 v |= MX25_H1_IPPUE_DOWN_BIT;
124 if (flags & MXC_EHCI_IPPUE_UP)
125 v |= MX25_H1_IPPUE_UP_BIT;
131 #elif defined(CONFIG_MX31)
133 case 0: /* OTG port */
134 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
135 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
137 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
138 v |= MX31_OTG_PM_BIT;
141 case 1: /* H1 port */
142 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
143 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
145 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
148 if (!(flags & MXC_EHCI_TTL_ENABLED))
152 case 2: /* H2 port */
153 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
154 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
156 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
159 if (!(flags & MXC_EHCI_TTL_ENABLED))
166 #elif defined(CONFIG_MX35)
168 case 0: /* OTG port */
169 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
171 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
173 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
174 v |= MX35_OTG_PM_BIT;
176 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
177 v |= MX35_OTG_PP_BIT;
179 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
180 v |= MX35_OTG_OCPOL_BIT;
183 case 1: /* H1 port */
184 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
185 MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
186 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
187 MX35_H1_IPPUE_UP_BIT);
188 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
190 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
193 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
196 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
197 v |= MX35_H1_OCPOL_BIT;
199 if (!(flags & MXC_EHCI_TTL_ENABLED))
200 v |= MX35_H1_TLL_BIT;
202 if (flags & MXC_EHCI_INTERNAL_PHY)
203 v |= MX35_H1_USBTE_BIT;
205 if (flags & MXC_EHCI_IPPUE_DOWN)
206 v |= MX35_H1_IPPUE_DOWN_BIT;
208 if (flags & MXC_EHCI_IPPUE_UP)
209 v |= MX35_H1_IPPUE_UP_BIT;
216 #error MXC EHCI USB driver not supported on this platform
218 writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
223 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
225 struct usb_ehci *ehci;
227 struct clock_control_regs *sc_regs =
228 (struct clock_control_regs *)CCM_BASE;
230 __raw_readl(&sc_regs->ccmr);
231 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
236 ehci = (struct usb_ehci *)(IMX_USB_BASE +
237 IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
238 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
239 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
240 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
241 setbits_le32(&ehci->usbmode, CM_HOST);
242 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
243 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
245 /* Workaround for ENGcm11601 */
246 __raw_writel(0, &ehci->sbuscfg);
255 * Destroy the appropriate control structures corresponding
256 * the the EHCI host controller.
258 int ehci_hcd_stop(int index)