2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <asm/arch/imx-regs.h>
24 #include <usb/ehci-fsl.h>
29 #define USBCTRL_OTGBASE_OFFSET 0x600
32 #define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
33 #define MX25_USB_CTRL_HSTD_BIT (1<<5)
34 #define MX25_USB_CTRL_USBTE_BIT (1<<4)
35 #define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
39 #define MX31_OTG_SIC_SHIFT 29
40 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
41 #define MX31_OTG_PM_BIT (1 << 24)
43 #define MX31_H2_SIC_SHIFT 21
44 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
45 #define MX31_H2_PM_BIT (1 << 16)
46 #define MX31_H2_DT_BIT (1 << 5)
48 #define MX31_H1_SIC_SHIFT 13
49 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
50 #define MX31_H1_PM_BIT (1 << 8)
51 #define MX31_H1_DT_BIT (1 << 4)
54 static int mxc_set_usbcontrol(int port, unsigned int flags)
59 v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
60 MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
64 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
67 case 0: /* OTG port */
68 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
69 v |= (flags & MXC_EHCI_INTERFACE_MASK)
70 << MX31_OTG_SIC_SHIFT;
71 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
76 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
78 v |= (flags & MXC_EHCI_INTERFACE_MASK)
80 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
83 if (!(flags & MXC_EHCI_TTL_ENABLED))
88 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
90 v |= (flags & MXC_EHCI_INTERFACE_MASK)
92 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
95 if (!(flags & MXC_EHCI_TTL_ENABLED))
104 writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
108 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
110 struct usb_ehci *ehci;
112 struct clock_control_regs *sc_regs =
113 (struct clock_control_regs *)CCM_BASE;
115 __raw_readl(&sc_regs->ccmr);
116 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
121 ehci = (struct usb_ehci *)(IMX_USB_BASE +
122 (0x200 * CONFIG_MXC_USB_PORT));
123 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
124 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
125 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
126 setbits_le32(&ehci->usbmode, CM_HOST);
127 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
128 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
136 * Destroy the appropriate control structures corresponding
137 * the the EHCI host controller.
139 int ehci_hcd_stop(int index)