2 * Freescale i.MX28 USB Host driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <asm/arch/regs-common.h>
25 #include <asm/arch/regs-base.h>
26 #include <asm/arch/regs-clkctrl-mx28.h>
27 #include <asm/arch/regs-usb.h>
28 #include <asm/arch/regs-usbphy.h>
32 #if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1)
33 #error "MXS EHCI: Invalid port selected!"
36 #ifndef CONFIG_EHCI_MXS_PORT
37 #error "MXS EHCI: Please define correct port using CONFIG_EHCI_MXS_PORT!"
40 static struct ehci_mxs {
41 struct mxs_usb_regs *usb_regs;
42 struct mxs_usbphy_regs *phy_regs;
45 int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)
47 uint32_t usb_base, phy_base;
50 usb_base = MXS_USBCTRL0_BASE;
51 phy_base = MXS_USBPHY0_BASE;
54 usb_base = MXS_USBCTRL1_BASE;
55 phy_base = MXS_USBPHY1_BASE;
58 printf("CONFIG_EHCI_MXS_PORT (port = %d)\n", port);
62 mxs_usb->usb_regs = (struct mxs_usb_regs *)usb_base;
63 mxs_usb->phy_regs = (struct mxs_usbphy_regs *)phy_base;
67 /* This DIGCTL register ungates clock to USB */
68 #define HW_DIGCTL_CTRL 0x8001c000
69 #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
70 #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
72 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
76 uint32_t usb_base, cap_base;
77 struct mxs_register_32 *digctl_ctrl =
78 (struct mxs_register_32 *)HW_DIGCTL_CTRL;
79 struct mxs_clkctrl_regs *clkctrl_regs =
80 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
82 ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
86 /* Reset the PHY block */
87 writel(USBPHY_CTRL_SFTRST, &ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
89 writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
90 &ehci_mxs.phy_regs->hw_usbphy_ctrl_clr);
92 /* Enable USB clock */
93 writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
94 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
95 writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
96 &clkctrl_regs->hw_clkctrl_pll1ctrl0_set);
98 writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
99 &digctl_ctrl->reg_clr);
102 writel(0, &ehci_mxs.phy_regs->hw_usbphy_pwd);
104 /* Enable UTMI+ Level 2 and Level 3 compatibility */
105 writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
106 &ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
108 usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
109 *hccr = (struct ehci_hccr *)usb_base;
111 cap_base = ehci_readl(&(*hccr)->cr_capbase);
112 *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
117 int ehci_hcd_stop(int index)
120 uint32_t usb_base, cap_base, tmp;
121 struct mxs_register_32 *digctl_ctrl =
122 (struct mxs_register_32 *)HW_DIGCTL_CTRL;
123 struct mxs_clkctrl_regs *clkctrl_regs =
124 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
125 struct ehci_hccr *hccr;
126 struct ehci_hcor *hcor;
128 ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
132 /* Stop the USB port */
133 usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
134 hccr = (struct ehci_hccr *)usb_base;
135 cap_base = ehci_readl(&hccr->cr_capbase);
136 hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
138 tmp = ehci_readl(&hcor->or_usbcmd);
140 ehci_writel(tmp, &hcor->or_usbcmd);
142 /* Disable the PHY */
143 tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
144 USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
145 USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
147 writel(tmp, &ehci_mxs.phy_regs->hw_usbphy_pwd);
149 /* Disable USB clock */
150 writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
151 &clkctrl_regs->hw_clkctrl_pll0ctrl0_clr);
152 writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
153 &clkctrl_regs->hw_clkctrl_pll1ctrl0_clr);
155 /* Gate off the USB clock */
156 writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
157 &digctl_ctrl->reg_set);