2 * Freescale i.MX28 USB Host driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <asm/arch/imx-regs.h>
28 #if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1)
29 #error "MXS EHCI: Invalid port selected!"
32 #ifndef CONFIG_EHCI_MXS_PORT
33 #error "MXS EHCI: Please define correct port using CONFIG_EHCI_MXS_PORT!"
36 static struct ehci_mxs {
37 struct mxs_usb_regs *usb_regs;
38 struct mxs_usbphy_regs *phy_regs;
41 int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)
43 uint32_t usb_base, phy_base;
46 usb_base = MXS_USBCTRL0_BASE;
47 phy_base = MXS_USBPHY0_BASE;
50 usb_base = MXS_USBCTRL1_BASE;
51 phy_base = MXS_USBPHY1_BASE;
54 printf("CONFIG_EHCI_MXS_PORT (port = %d)\n", port);
58 mxs_usb->usb_regs = (struct mxs_usb_regs *)usb_base;
59 mxs_usb->phy_regs = (struct mxs_usbphy_regs *)phy_base;
63 /* This DIGCTL register ungates clock to USB */
64 #define HW_DIGCTL_CTRL 0x8001c000
65 #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
66 #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
68 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
72 uint32_t usb_base, cap_base;
73 struct mxs_register_32 *digctl_ctrl =
74 (struct mxs_register_32 *)HW_DIGCTL_CTRL;
75 struct mxs_clkctrl_regs *clkctrl_regs =
76 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
78 ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
82 /* Reset the PHY block */
83 writel(USBPHY_CTRL_SFTRST, &ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
85 writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
86 &ehci_mxs.phy_regs->hw_usbphy_ctrl_clr);
88 /* Enable USB clock */
89 writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
90 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
91 writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
92 &clkctrl_regs->hw_clkctrl_pll1ctrl0_set);
94 writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
95 &digctl_ctrl->reg_clr);
98 writel(0, &ehci_mxs.phy_regs->hw_usbphy_pwd);
100 /* Enable UTMI+ Level 2 and Level 3 compatibility */
101 writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
102 &ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
104 usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
105 *hccr = (struct ehci_hccr *)usb_base;
107 cap_base = ehci_readl(&(*hccr)->cr_capbase);
108 *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
113 int ehci_hcd_stop(int index)
116 uint32_t usb_base, cap_base, tmp;
117 struct mxs_register_32 *digctl_ctrl =
118 (struct mxs_register_32 *)HW_DIGCTL_CTRL;
119 struct mxs_clkctrl_regs *clkctrl_regs =
120 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
121 struct ehci_hccr *hccr;
122 struct ehci_hcor *hcor;
124 ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
128 /* Stop the USB port */
129 usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
130 hccr = (struct ehci_hccr *)usb_base;
131 cap_base = ehci_readl(&hccr->cr_capbase);
132 hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
134 tmp = ehci_readl(&hcor->or_usbcmd);
136 ehci_writel(tmp, &hcor->or_usbcmd);
138 /* Disable the PHY */
139 tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
140 USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
141 USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
143 writel(tmp, &ehci_mxs.phy_regs->hw_usbphy_pwd);
145 /* Disable USB clock */
146 writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
147 &clkctrl_regs->hw_clkctrl_pll0ctrl0_clr);
148 writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
149 &clkctrl_regs->hw_clkctrl_pll1ctrl0_clr);
151 /* Gate off the USB clock */
152 writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
153 &digctl_ctrl->reg_set);