2 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
3 * (C) Copyright 2004-2008
4 * Texas Instruments, <www.ti.com>
6 * Derived from Beagle Board code by
7 * Sunil Kumar <sunilsaini05@gmail.com>
8 * Shashi Ranjan <shashiranjanmca05@gmail.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
34 #include <asm/arch/ehci.h>
35 #include <asm/ehci-omap.h>
39 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
40 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
41 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
43 static int omap_uhh_reset(void)
45 unsigned long init = get_timer(0);
47 /* perform UHH soft reset, and wait until reset is complete */
48 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
50 /* Wait for UHH reset to complete */
51 while (!(readl(&uhh->syss) & OMAP_UHH_SYSSTATUS_EHCI_RESETDONE))
52 if (get_timer(init) > CONFIG_SYS_HZ) {
53 debug("OMAP UHH error: timeout resetting ehci\n");
60 static int omap_ehci_tll_reset(void)
62 unsigned long init = get_timer(0);
64 /* perform TLL soft reset, and wait until reset is complete */
65 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
67 /* Wait for TLL reset to complete */
68 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
69 if (get_timer(init) > CONFIG_SYS_HZ) {
70 debug("OMAP EHCI error: timeout resetting TLL\n");
77 static void omap_usbhs_hsic_init(int port)
81 /* Enable channels now */
82 reg = readl(&usbtll->channel_conf + port);
84 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
85 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
86 | OMAP_TLL_CHANNEL_CONF_DRVVBUS
87 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
88 | OMAP_TLL_CHANNEL_CONF_CHANEN));
90 writel(reg, &usbtll->channel_conf + port);
93 static void omap_ehci_soft_phy_reset(int port)
95 struct ulpi_viewport ulpi_vp;
97 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
98 ulpi_vp.port_num = port;
100 ulpi_reset(&ulpi_vp);
103 inline int __board_usb_init(void)
107 int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
109 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
110 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
111 /* controls PHY(s) reset signal(s) */
112 static inline void omap_ehci_phy_reset(int on, int delay)
116 * Hold the PHY in RESET for enough time till
117 * PHY is settled and ready
121 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
122 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
123 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
125 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
126 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
127 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
130 /* Hold the PHY in RESET for enough time till DIR is high */
136 #define omap_ehci_phy_reset(on, delay) do {} while (0)
139 /* Reset is needed otherwise the kernel-driver will throw an error. */
140 int omap_ehci_hcd_stop(void)
142 debug("Resetting OMAP EHCI\n");
143 omap_ehci_phy_reset(1, 0);
145 if (omap_uhh_reset() < 0)
148 if (omap_ehci_tll_reset() < 0)
155 * Initialize the OMAP EHCI controller and PHY.
156 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
157 * See there for additional Copyrights.
159 int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
160 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
163 unsigned int i, reg = 0, rev = 0;
165 debug("Initializing OMAP EHCI\n");
167 ret = board_usb_init();
171 /* Put the PHY in RESET */
172 omap_ehci_phy_reset(1, 10);
174 ret = omap_uhh_reset();
178 ret = omap_ehci_tll_reset();
182 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
183 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
184 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
186 /* Put UHH in NoIdle/NoStandby mode */
187 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
189 /* setup ULPI bypass and burst configurations */
190 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
191 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
192 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
193 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
195 rev = readl(&uhh->rev);
196 if (rev == OMAP_USBHS_REV1) {
197 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
198 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
200 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
202 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
203 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
205 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
207 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
208 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
210 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
211 } else if (rev == OMAP_USBHS_REV2) {
212 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
213 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
215 /* Clear port mode fields for PHY mode*/
217 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
218 setbits_le32(®, OMAP_P1_MODE_HSIC);
220 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
221 setbits_le32(®, OMAP_P2_MODE_HSIC);
223 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
224 setbits_le32(®, OMAP_P3_MODE_HSIC);
227 debug("OMAP UHH_REVISION 0x%x\n", rev);
228 writel(reg, &uhh->hostconfig);
230 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
231 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
232 omap_usbhs_hsic_init(i);
234 omap_ehci_phy_reset(0, 10);
237 * An undocumented "feature" in the OMAP3 EHCI controller,
238 * causes suspended ports to be taken out of suspend when
239 * the USBCMD.Run/Stop bit is cleared (for example when
240 * we do ehci_bus_suspend).
241 * This breaks suspend-resume if the root-hub is allowed
242 * to suspend. Writing 1 to this undocumented register bit
243 * disables this feature and restores normal behavior.
245 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
247 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
248 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
249 omap_ehci_soft_phy_reset(i);
251 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
252 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
254 debug("OMAP EHCI init done\n");