2 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
3 * (C) Copyright 2004-2008
4 * Texas Instruments, <www.ti.com>
6 * Derived from Beagle Board code by
7 * Sunil Kumar <sunilsaini05@gmail.com>
8 * Shashi Ranjan <shashiranjanmca05@gmail.com>
11 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/ehci.h>
21 #include <asm/ehci-omap.h>
25 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
26 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
27 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
29 static int omap_uhh_reset(void)
34 rev = readl(&uhh->rev);
37 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
41 /* Wait for soft RESET to complete */
42 while (!(readl(&uhh->syss) & 0x1)) {
44 printf("%s: RESET timeout\n", __func__);
51 /* Set No-Idle, No-Standby */
52 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
55 default: /* Rev. 2 onwards */
57 udelay(2); /* Need to wait before accessing SYSCONFIG back */
59 /* Wait for soft RESET to complete */
60 while ((readl(&uhh->sysc) & 0x1)) {
62 printf("%s: RESET timeout\n", __func__);
69 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
76 static int omap_ehci_tll_reset(void)
78 unsigned long init = get_timer(0);
80 /* perform TLL soft reset, and wait until reset is complete */
81 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
83 /* Wait for TLL reset to complete */
84 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
85 if (get_timer(init) > CONFIG_SYS_HZ) {
86 debug("OMAP EHCI error: timeout resetting TLL\n");
93 static void omap_usbhs_hsic_init(int port)
97 /* Enable channels now */
98 reg = readl(&usbtll->channel_conf + port);
100 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
101 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
102 | OMAP_TLL_CHANNEL_CONF_DRVVBUS
103 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
104 | OMAP_TLL_CHANNEL_CONF_CHANEN));
106 writel(reg, &usbtll->channel_conf + port);
109 #ifdef CONFIG_USB_ULPI
110 static void omap_ehci_soft_phy_reset(int port)
112 struct ulpi_viewport ulpi_vp;
114 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
115 ulpi_vp.port_num = port;
117 ulpi_reset(&ulpi_vp);
120 static void omap_ehci_soft_phy_reset(int port)
126 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
127 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
128 defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
129 /* controls PHY(s) reset signal(s) */
130 static inline void omap_ehci_phy_reset(int on, int delay)
134 * Hold the PHY in RESET for enough time till
135 * PHY is settled and ready
139 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
140 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
141 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
143 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
144 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
145 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
147 #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
148 gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
149 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
152 /* Hold the PHY in RESET for enough time till DIR is high */
158 #define omap_ehci_phy_reset(on, delay) do {} while (0)
161 /* Reset is needed otherwise the kernel-driver will throw an error. */
162 int omap_ehci_hcd_stop(void)
164 debug("Resetting OMAP EHCI\n");
165 omap_ehci_phy_reset(1, 0);
167 if (omap_uhh_reset() < 0)
170 if (omap_ehci_tll_reset() < 0)
177 * Initialize the OMAP EHCI controller and PHY.
178 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
179 * See there for additional Copyrights.
181 int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
182 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
185 unsigned int i, reg = 0, rev = 0;
187 debug("Initializing OMAP EHCI\n");
189 ret = board_usb_init(index, USB_INIT_HOST);
193 /* Put the PHY in RESET */
194 omap_ehci_phy_reset(1, 10);
196 ret = omap_uhh_reset();
200 ret = omap_ehci_tll_reset();
204 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
205 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
206 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
208 /* Put UHH in NoIdle/NoStandby mode */
209 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
211 /* setup ULPI bypass and burst configurations */
212 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
213 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
214 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
215 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
217 rev = readl(&uhh->rev);
218 if (rev == OMAP_USBHS_REV1) {
219 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
220 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
222 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
224 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
225 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
227 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
229 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
230 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
232 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
233 } else if (rev == OMAP_USBHS_REV2) {
235 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
236 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
238 /* Clear port mode fields for PHY mode */
240 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
241 setbits_le32(®, OMAP_P1_MODE_HSIC);
243 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
244 setbits_le32(®, OMAP_P2_MODE_HSIC);
246 } else if (rev == OMAP_USBHS_REV2_1) {
248 clrsetbits_le32(®,
249 (OMAP_P1_MODE_CLEAR |
252 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
254 /* Clear port mode fields for PHY mode */
256 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
257 setbits_le32(®, OMAP_P1_MODE_HSIC);
259 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
260 setbits_le32(®, OMAP_P2_MODE_HSIC);
262 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
263 setbits_le32(®, OMAP_P3_MODE_HSIC);
266 debug("OMAP UHH_REVISION 0x%x\n", rev);
267 writel(reg, &uhh->hostconfig);
269 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
270 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
271 omap_usbhs_hsic_init(i);
273 omap_ehci_phy_reset(0, 10);
276 * An undocumented "feature" in the OMAP3 EHCI controller,
277 * causes suspended ports to be taken out of suspend when
278 * the USBCMD.Run/Stop bit is cleared (for example when
279 * we do ehci_bus_suspend).
280 * This breaks suspend-resume if the root-hub is allowed
281 * to suspend. Writing 1 to this undocumented register bit
282 * disables this feature and restores normal behavior.
284 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
286 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
287 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
288 omap_ehci_soft_phy_reset(i);
290 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
291 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
293 debug("OMAP EHCI init done\n");