2 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
3 * (C) Copyright 2004-2008
4 * Texas Instruments, <www.ti.com>
6 * Derived from Beagle Board code by
7 * Sunil Kumar <sunilsaini05@gmail.com>
8 * Shashi Ranjan <shashiranjanmca05@gmail.com>
11 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/ehci.h>
21 #include <asm/ehci-omap.h>
25 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
26 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
27 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
29 static int omap_uhh_reset(void)
31 unsigned long init = get_timer(0);
33 /* perform UHH soft reset, and wait until reset is complete */
34 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
36 /* Wait for UHH reset to complete */
37 while (!(readl(&uhh->syss) & OMAP_UHH_SYSSTATUS_EHCI_RESETDONE))
38 if (get_timer(init) > CONFIG_SYS_HZ) {
39 debug("OMAP UHH error: timeout resetting ehci\n");
46 static int omap_ehci_tll_reset(void)
48 unsigned long init = get_timer(0);
50 /* perform TLL soft reset, and wait until reset is complete */
51 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
53 /* Wait for TLL reset to complete */
54 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
55 if (get_timer(init) > CONFIG_SYS_HZ) {
56 debug("OMAP EHCI error: timeout resetting TLL\n");
63 static void omap_usbhs_hsic_init(int port)
67 /* Enable channels now */
68 reg = readl(&usbtll->channel_conf + port);
70 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
71 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
72 | OMAP_TLL_CHANNEL_CONF_DRVVBUS
73 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
74 | OMAP_TLL_CHANNEL_CONF_CHANEN));
76 writel(reg, &usbtll->channel_conf + port);
79 static void omap_ehci_soft_phy_reset(int port)
81 struct ulpi_viewport ulpi_vp;
83 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
84 ulpi_vp.port_num = port;
89 inline int __board_usb_init(void)
93 int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
95 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
96 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
97 /* controls PHY(s) reset signal(s) */
98 static inline void omap_ehci_phy_reset(int on, int delay)
102 * Hold the PHY in RESET for enough time till
103 * PHY is settled and ready
107 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
108 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
109 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
111 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
112 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
113 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
116 /* Hold the PHY in RESET for enough time till DIR is high */
122 #define omap_ehci_phy_reset(on, delay) do {} while (0)
125 /* Reset is needed otherwise the kernel-driver will throw an error. */
126 int omap_ehci_hcd_stop(void)
128 debug("Resetting OMAP EHCI\n");
129 omap_ehci_phy_reset(1, 0);
131 if (omap_uhh_reset() < 0)
134 if (omap_ehci_tll_reset() < 0)
141 * Initialize the OMAP EHCI controller and PHY.
142 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
143 * See there for additional Copyrights.
145 int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
146 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
149 unsigned int i, reg = 0, rev = 0;
151 debug("Initializing OMAP EHCI\n");
153 ret = board_usb_init();
157 /* Put the PHY in RESET */
158 omap_ehci_phy_reset(1, 10);
160 ret = omap_uhh_reset();
164 ret = omap_ehci_tll_reset();
168 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
169 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
170 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
172 /* Put UHH in NoIdle/NoStandby mode */
173 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
175 /* setup ULPI bypass and burst configurations */
176 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
177 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
178 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
179 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
181 rev = readl(&uhh->rev);
182 if (rev == OMAP_USBHS_REV1) {
183 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
184 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
186 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
188 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
189 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
191 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
193 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
194 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
196 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
197 } else if (rev == OMAP_USBHS_REV2) {
198 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
199 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
201 /* Clear port mode fields for PHY mode*/
203 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
204 setbits_le32(®, OMAP_P1_MODE_HSIC);
206 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
207 setbits_le32(®, OMAP_P2_MODE_HSIC);
209 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
210 setbits_le32(®, OMAP_P3_MODE_HSIC);
213 debug("OMAP UHH_REVISION 0x%x\n", rev);
214 writel(reg, &uhh->hostconfig);
216 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
217 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
218 omap_usbhs_hsic_init(i);
220 omap_ehci_phy_reset(0, 10);
223 * An undocumented "feature" in the OMAP3 EHCI controller,
224 * causes suspended ports to be taken out of suspend when
225 * the USBCMD.Run/Stop bit is cleared (for example when
226 * we do ehci_bus_suspend).
227 * This breaks suspend-resume if the root-hub is allowed
228 * to suspend. Writing 1 to this undocumented register bit
229 * disables this feature and restores normal behavior.
231 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
233 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
234 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
235 omap_ehci_soft_phy_reset(i);
237 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
238 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
240 debug("OMAP EHCI init done\n");