2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (c) 2009-2012 NVIDIA Corporation
4 * Copyright (c) 2013 Lucas Stach
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/errno.h>
28 #include <asm-generic/gpio.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch-tegra/usb.h>
38 #ifdef CONFIG_USB_ULPI
39 #ifndef CONFIG_USB_ULPI_VIEWPORT
40 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
41 define CONFIG_USB_ULPI_VIEWPORT"
46 USB_PORTS_MAX = 3, /* Maximum ports we allow */
49 /* Parameters we need for USB */
51 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
52 PARAM_DIVM, /* PLL INPUT DIVIDER */
53 PARAM_DIVP, /* POST DIVIDER (2^N) */
54 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
55 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
56 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
57 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
58 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
59 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
60 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
61 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
66 /* Possible port types (dual role mode) */
69 DR_MODE_HOST, /* supports host operation */
70 DR_MODE_DEVICE, /* supports device operation */
71 DR_MODE_OTG, /* supports both */
74 /* Information about a USB port */
76 struct usb_ctlr *reg; /* address of registers in physical memory */
77 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
78 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
79 unsigned enabled:1; /* 1 to enable, 0 to disable */
80 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
81 unsigned initialized:1; /* has this port already been initialized? */
82 enum dr_mode dr_mode; /* dual role mode */
83 enum periph_id periph_id;/* peripheral id */
84 struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
85 struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
88 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
89 static unsigned port_count; /* Number of available ports */
92 * This table has USB timing parameters for each Oscillator frequency we
93 * support. There are four sets of values:
95 * 1. PLLU configuration information (reference clock is osc/clk_m and
96 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
98 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
99 * ----------------------------------------------------------------------
100 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
101 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
102 * Filter frequency (MHz) 1 4.8 6 2
103 * CPCON 1100b 0011b 1100b 1100b
106 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
108 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
109 * ---------------------------------------------------------------------------
110 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
111 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
112 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
113 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
115 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
116 * SessEnd. Each of these signals have their own debouncer and for each of
117 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
120 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
121 * 0xffff -> No debouncing at all
122 * <n> ms = <n> *1000 / (1/19.2MHz) / 4
124 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
125 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
127 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
128 * values, so we can keep those to default.
130 * 4. The 20 microsecond delay after bias cell operation.
132 static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
133 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
134 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
135 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
136 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
137 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
140 /* UTMIP Idle Wait Delay */
141 static const u8 utmip_idle_wait_delay = 17;
143 /* UTMIP Elastic limit */
144 static const u8 utmip_elastic_limit = 16;
146 /* UTMIP High Speed Sync Start Delay */
147 static const u8 utmip_hs_sync_start_delay = 9;
150 * A known hardware issue where Connect Status Change bit of PORTSC register
151 * of USB1 controller will be set after Port Reset.
152 * We have to clear it in order for later device enumeration to proceed.
153 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup
156 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
159 if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE)
161 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
162 if (ehci_readl(status_reg) & EHCI_PS_CSC)
166 /* Put the port into host mode */
167 static void set_host_mode(struct fdt_usb *config)
170 * If we are an OTG port, check if remote host is driving VBus and
171 * bail out in this case.
173 if (config->dr_mode == DR_MODE_OTG &&
174 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
178 * If not driving, we set the GPIO to enable VBUS. We assume
179 * that the pinmux is set up correctly for this.
181 if (fdt_gpio_isvalid(&config->vbus_gpio)) {
182 fdtdec_setup_gpio(&config->vbus_gpio);
183 gpio_direction_output(config->vbus_gpio.gpio,
184 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
186 debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
187 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
192 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
194 /* Reset the USB controller with 2us delay */
195 reset_periph(config->periph_id, 2);
198 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
201 if (config->has_legacy_mode)
202 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
204 /* Put UTMIP1/3 in reset */
205 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
207 /* Enable the UTMIP PHY */
209 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
212 /* set up the UTMI USB controller with the parameters provided */
213 static int init_utmi_usb_controller(struct fdt_usb *config)
217 const unsigned *timing;
218 struct usb_ctlr *usbctlr = config->reg;
220 clock_enable(config->periph_id);
222 /* Reset the usb controller */
223 usbf_reset_controller(config, usbctlr);
225 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
226 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
228 /* Follow the crystal clock disable by >100ns delay */
232 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
233 * mux must be switched to actually use a_sess_vld threshold.
235 if (fdt_gpio_isvalid(&config->vbus_gpio)) {
236 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
238 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
242 * PLL Delay CONFIGURATION settings. The following parameters control
243 * the bring up of the plls.
245 timing = usb_pll[clock_get_osc_freq()];
247 val = readl(&usbctlr->utmip_misc_cfg1);
248 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
249 timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
250 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
251 timing[PARAM_ACTIVE_DELAY_COUNT] <<
252 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
253 writel(val, &usbctlr->utmip_misc_cfg1);
255 /* Set PLL enable delay count and crystal frequency count */
256 val = readl(&usbctlr->utmip_pll_cfg1);
257 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
258 timing[PARAM_ENABLE_DELAY_COUNT] <<
259 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
260 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
261 timing[PARAM_XTAL_FREQ_COUNT] <<
262 UTMIP_XTAL_FREQ_COUNT_SHIFT);
263 writel(val, &usbctlr->utmip_pll_cfg1);
265 /* Setting the tracking length time */
266 clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
267 UTMIP_BIAS_PDTRK_COUNT_MASK,
268 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
270 /* Program debounce time for VBUS to become valid */
271 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
272 UTMIP_DEBOUNCE_CFG0_MASK,
273 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
275 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
277 /* Disable battery charge enabling bit */
278 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
280 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
281 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
284 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
285 * Setting these fields, together with default values of the
286 * other fields, results in programming the registers below as
288 * UTMIP_HSRX_CFG0 = 0x9168c000
289 * UTMIP_HSRX_CFG1 = 0x13
292 /* Set PLL enable delay count and Crystal frequency count */
293 val = readl(&usbctlr->utmip_hsrx_cfg0);
294 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
295 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
296 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
297 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
298 writel(val, &usbctlr->utmip_hsrx_cfg0);
300 /* Configure the UTMIP_HS_SYNC_START_DLY */
301 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
302 UTMIP_HS_SYNC_START_DLY_MASK,
303 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
305 /* Preceed the crystal clock disable by >100ns delay. */
308 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
309 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
311 /* Finished the per-controller init. */
313 /* De-assert UTMIP_RESET to bring out of reset. */
314 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
316 /* Wait for the phy clock to become valid in 100 ms */
317 for (loop_count = 100000; loop_count != 0; loop_count--) {
318 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
325 /* Disable ICUSB FS/LS transceiver */
326 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
328 /* Select UTMI parallel interface */
329 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
330 PTS_UTMI << PTS_SHIFT);
331 clrbits_le32(&usbctlr->port_sc1, STS);
333 /* Deassert power down state */
334 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
335 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
336 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
337 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
342 #ifdef CONFIG_USB_ULPI
343 /* if board file does not set a ULPI reference frequency we default to 24MHz */
344 #ifndef CONFIG_ULPI_REF_CLK
345 #define CONFIG_ULPI_REF_CLK 24000000
348 /* set up the ULPI USB controller with the parameters provided */
349 static int init_ulpi_usb_controller(struct fdt_usb *config)
353 struct ulpi_viewport ulpi_vp;
354 struct usb_ctlr *usbctlr = config->reg;
356 /* set up ULPI reference clock on pllp_out4 */
357 clock_enable(PERIPH_ID_DEV2_OUT);
358 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
361 if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
362 fdtdec_setup_gpio(&config->phy_reset_gpio);
363 gpio_direction_output(config->phy_reset_gpio.gpio, 0);
365 gpio_set_value(config->phy_reset_gpio.gpio, 1);
368 /* Reset the usb controller */
369 clock_enable(config->periph_id);
370 usbf_reset_controller(config, usbctlr);
372 /* enable pinmux bypass */
373 setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
374 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
376 /* Select ULPI parallel interface */
377 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
379 /* enable ULPI transceiver */
380 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
382 /* configure ULPI transceiver timings */
384 writel(val, &usbctlr->ulpi_timing_ctrl_1);
386 val |= ULPI_DATA_TRIMMER_SEL(4);
387 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
388 val |= ULPI_DIR_TRIMMER_SEL(4);
389 writel(val, &usbctlr->ulpi_timing_ctrl_1);
392 val |= ULPI_DATA_TRIMMER_LOAD;
393 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
394 val |= ULPI_DIR_TRIMMER_LOAD;
395 writel(val, &usbctlr->ulpi_timing_ctrl_1);
397 /* set up phy for host operation with external vbus supply */
398 ulpi_vp.port_num = 0;
399 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
401 if (ulpi_init(&ulpi_vp)) {
402 printf("Tegra ULPI viewport init failed\n");
406 ulpi_set_vbus(&ulpi_vp, 1, 1);
407 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
409 /* enable wakeup events */
410 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
412 /* Enable and wait for the phy clock to become valid in 100 ms */
413 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
414 for (loop_count = 100000; loop_count != 0; loop_count--) {
415 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
421 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
426 static int init_ulpi_usb_controller(struct fdt_usb *config)
428 printf("No code to set up ULPI controller, please enable"
429 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
434 static void config_clock(const u32 timing[])
436 clock_start_pll(CLOCK_ID_USB,
437 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
438 timing[PARAM_CPCON], timing[PARAM_LFCON]);
441 int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
443 const char *phy, *mode;
445 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
446 mode = fdt_getprop(blob, node, "dr_mode", NULL);
448 if (0 == strcmp(mode, "host"))
449 config->dr_mode = DR_MODE_HOST;
450 else if (0 == strcmp(mode, "peripheral"))
451 config->dr_mode = DR_MODE_DEVICE;
452 else if (0 == strcmp(mode, "otg"))
453 config->dr_mode = DR_MODE_OTG;
455 debug("%s: Cannot decode dr_mode '%s'\n", __func__,
457 return -FDT_ERR_NOTFOUND;
460 config->dr_mode = DR_MODE_HOST;
463 phy = fdt_getprop(blob, node, "phy_type", NULL);
464 config->utmi = phy && 0 == strcmp("utmi", phy);
465 config->ulpi = phy && 0 == strcmp("ulpi", phy);
466 config->enabled = fdtdec_get_is_enabled(blob, node);
467 config->has_legacy_mode = fdtdec_get_bool(blob, node,
468 "nvidia,has-legacy-mode");
469 config->periph_id = clock_decode_periph_id(blob, node);
470 if (config->periph_id == PERIPH_ID_NONE) {
471 debug("%s: Missing/invalid peripheral ID\n", __func__);
472 return -FDT_ERR_NOTFOUND;
474 fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
475 fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
476 &config->phy_reset_gpio);
477 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
478 "vbus=%d, phy_reset=%d, dr_mode=%d\n",
479 config->enabled, config->has_legacy_mode, config->utmi,
480 config->ulpi, config->periph_id, config->vbus_gpio.gpio,
481 config->phy_reset_gpio.gpio, config->dr_mode);
486 int board_usb_init(const void *blob)
488 struct fdt_usb config;
489 enum clock_osc_freq freq;
490 int node_list[USB_PORTS_MAX];
493 /* Set up the USB clocks correctly based on our oscillator frequency */
494 freq = clock_get_osc_freq();
495 config_clock(usb_pll[freq]);
497 /* count may return <0 on error */
498 count = fdtdec_find_aliases_for_id(blob, "usb",
499 COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
500 for (i = 0; i < count; i++) {
501 if (port_count == USB_PORTS_MAX) {
502 printf("tegrausb: Cannot register more than %d ports\n",
507 debug("USB %d: ", i);
511 if (fdt_decode_usb(blob, node, &config)) {
512 debug("Cannot decode USB node %s\n",
513 fdt_get_name(blob, node, NULL));
516 config.initialized = 0;
518 /* add new USB port to the list of available ports */
519 port[port_count++] = config;
526 * Start up the given port number (ports are numbered from 0 on each board).
527 * This returns values for the appropriate hccr and hcor addresses to use for
528 * USB EHCI operations.
530 * @param index port number to start
531 * @param hccr returns start address of EHCI HCCR registers
532 * @param hcor returns start address of EHCI HCOR registers
533 * @return 0 if ok, -1 on error (generally invalid port number)
535 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
537 struct fdt_usb *config;
538 struct usb_ctlr *usbctlr;
540 if (index >= port_count)
543 config = &port[index];
545 /* skip init, if the port is already initialized */
546 if (config->initialized)
549 if (config->utmi && init_utmi_usb_controller(config)) {
550 printf("tegrausb: Cannot init port %d\n", index);
554 if (config->ulpi && init_ulpi_usb_controller(config)) {
555 printf("tegrausb: Cannot init port %d\n", index);
559 set_host_mode(config);
561 config->initialized = 1;
564 usbctlr = config->reg;
565 *hccr = (struct ehci_hccr *)&usbctlr->cap_length;
566 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd;
571 * Bring down the specified USB controller
573 int ehci_hcd_stop(int index)
575 struct usb_ctlr *usbctlr;
577 usbctlr = port[index].reg;
579 /* Stop controller */
580 writel(0, &usbctlr->usb_cmd);
583 /* Initiate controller reset */
584 writel(2, &usbctlr->usb_cmd);
587 port[index].initialized = 0;